drm/framebuffer: Format modifier for Intel Gen-12 media compression

Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.

v2: Update code comment describing the color plane order for YUV
semiplanar formats.

Cc: Nanley G Chery <[e-mail]>
Cc: Matt Roper <[e-mail]>
Cc: Ville Syrjälä <[e-mail]>
Cc: Mika Kahola <[e-mail]>
Cc: [e-mail]
Signed-off-by: Dhinakaran Pandiyan <[e-mail]>
Signed-off-by: Lucas De Marchi <[e-mail]>
Signed-off-by: Imre Deak <[e-mail]>
Reviewed-by: Mika Kahola <[e-mail]>
Link: https://patchwork.freedesktop.org/patch/msgid/[e-mail]

include/uapi/drm/drm_fourcc.h

···
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
 
 /*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
+ * planes 2 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
+/*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
  * Macroblocks are laid in a Z-shape, and each pixel data is following the