tjh.dev / kernel
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mtd: nand: denali: avoid magic numbers and rename for clarification

Introduce some macros and helpers to avoid magic numbers and
rename macros/functions for clarification.

- We see '| 2' in several places. This means Data Cycle in MAP11 mode.
The Denali User's Guide says bit[1:0] of MAP11 is like follows:

b'00 = Command Cycle
b'01 = Address Cycle
b'10 = Data Cycle

So, this commit added DENALI_MAP11_{CMD,ADDR,DATA} macros.

- We see 'denali->flash_mem + 0x10' in several places, but 0x10 is a
magic number. Actually, this accesses the data port of the Host
Data/Command Interface. So, this commit added DENALI_HOST_DATA.
On the other hand, 'denali->flash_mem' gets access to the address
port, so DENALI_HOST_ADDR was also added.

- We see 'index_addr(denali, cmd, 0x1)' in denali_erase(), but 0x1
is a magic number. 0x1 means the erase operation. Replace 0x1
with DENALI_ERASE.

- Rename index_addr() to denali_host_write() for clarification

- Denali User's Guide says MAP{00,01,10,11} for access mode. Match
the macros with terminology in the IP document.

- Rename struct members as follows:
flash_bank -> active_bank (currently selected bank)
flash_reg -> reg (base address of registers)
flash_mem -> host (base address of host interface)
devnum -> devs_per_cs (devices connected in parallel)
bbtskipbytes -> oob_skip_bytes (number of bytes to skip in OOB)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

authored by

Masahiro Yamada and committed by
Boris Brezillon 0d3a966d 777f2d49

+144 -146
+125 -122
drivers/mtd/nand/denali.c
··· 31 31 32 32 #define DENALI_NAND_NAME "denali-nand" 33 33 34 - /* 35 - * indicates whether or not the internal value for the flash bank is 36 - * valid or not 37 - */ 38 - #define CHIP_SELECT_INVALID -1 34 + /* Host Data/Command Interface */ 35 + #define DENALI_HOST_ADDR 0x00 36 + #define DENALI_HOST_DATA 0x10 39 37 38 + #define DENALI_MAP00 (0 << 26) /* direct access to buffer */ 39 + #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */ 40 + #define DENALI_MAP10 (2 << 26) /* high-level control plane */ 41 + #define DENALI_MAP11 (3 << 26) /* direct controller access */ 42 + 43 + /* MAP11 access cycle type */ 44 + #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */ 45 + #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */ 46 + #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */ 47 + 48 + /* MAP10 commands */ 49 + #define DENALI_ERASE 0x01 50 + 51 + #define DENALI_BANK(denali) ((denali)->active_bank << 24) 52 + 53 + #define DENALI_INVALID_BANK -1 40 54 #define DENALI_NR_BANKS 4 41 55 42 56 /* ··· 70 56 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); 71 57 } 72 58 73 - /* 74 - * this is a helper macro that allows us to 75 - * format the bank into the proper bits for the controller 76 - */ 77 - #define BANK(x) ((x) << 24) 78 - 79 - /* 80 - * Certain operations for the denali NAND controller use an indexed mode to 81 - * read/write data. The operation is performed by writing the address value 82 - * of the command to the device memory followed by the data. This function 83 - * abstracts this common operation. 84 - */ 85 - static void index_addr(struct denali_nand_info *denali, 86 - uint32_t address, uint32_t data) 59 + static void denali_host_write(struct denali_nand_info *denali, 60 + uint32_t addr, uint32_t data) 87 61 { 88 - iowrite32(address, denali->flash_mem); 89 - iowrite32(data, denali->flash_mem + 0x10); 62 + iowrite32(addr, denali->host + DENALI_HOST_ADDR); 63 + iowrite32(data, denali->host + DENALI_HOST_DATA); 90 64 } 91 65 92 66 /* ··· 83 81 */ 84 82 static void detect_max_banks(struct denali_nand_info *denali) 85 83 { 86 - uint32_t features = ioread32(denali->flash_reg + FEATURES); 84 + uint32_t features = ioread32(denali->reg + FEATURES); 87 85 88 86 denali->max_banks = 1 << (features & FEATURES__N_BANKS); 89 87 ··· 97 95 int i; 98 96 99 97 for (i = 0; i < DENALI_NR_BANKS; i++) 100 - iowrite32(U32_MAX, denali->flash_reg + INTR_EN(i)); 101 - iowrite32(GLOBAL_INT_EN_FLAG, denali->flash_reg + GLOBAL_INT_ENABLE); 98 + iowrite32(U32_MAX, denali->reg + INTR_EN(i)); 99 + iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE); 102 100 } 103 101 104 102 static void denali_disable_irq(struct denali_nand_info *denali) ··· 106 104 int i; 107 105 108 106 for (i = 0; i < DENALI_NR_BANKS; i++) 109 - iowrite32(0, denali->flash_reg + INTR_EN(i)); 110 - iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); 107 + iowrite32(0, denali->reg + INTR_EN(i)); 108 + iowrite32(0, denali->reg + GLOBAL_INT_ENABLE); 111 109 } 112 110 113 111 static void denali_clear_irq(struct denali_nand_info *denali, 114 112 int bank, uint32_t irq_status) 115 113 { 116 114 /* write one to clear bits */ 117 - iowrite32(irq_status, denali->flash_reg + INTR_STATUS(bank)); 115 + iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); 118 116 } 119 117 120 118 static void denali_clear_irq_all(struct denali_nand_info *denali) ··· 135 133 spin_lock(&denali->irq_lock); 136 134 137 135 for (i = 0; i < DENALI_NR_BANKS; i++) { 138 - irq_status = ioread32(denali->flash_reg + INTR_STATUS(i)); 136 + irq_status = ioread32(denali->reg + INTR_STATUS(i)); 139 137 if (irq_status) 140 138 ret = IRQ_HANDLED; 141 139 142 140 denali_clear_irq(denali, i, irq_status); 143 141 144 - if (i != denali->flash_bank) 142 + if (i != denali->active_bank) 145 143 continue; 146 144 147 145 denali->irq_status |= irq_status; ··· 222 220 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; 223 221 224 222 /* Enable spare area/ECC per user's request. */ 225 - iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); 226 - iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); 223 + iowrite32(ecc_en_flag, denali->reg + ECC_ENABLE); 224 + iowrite32(transfer_spare_flag, denali->reg + TRANSFER_SPARE_REG); 227 225 } 228 226 229 227 static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) ··· 231 229 struct denali_nand_info *denali = mtd_to_denali(mtd); 232 230 int i; 233 231 234 - iowrite32(MODE_11 | BANK(denali->flash_bank) | 2, denali->flash_mem); 232 + iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali), 233 + denali->host + DENALI_HOST_ADDR); 235 234 236 235 for (i = 0; i < len; i++) 237 - buf[i] = ioread32(denali->flash_mem + 0x10); 236 + buf[i] = ioread32(denali->host + DENALI_HOST_DATA); 238 237 } 239 238 240 239 static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) ··· 243 240 struct denali_nand_info *denali = mtd_to_denali(mtd); 244 241 int i; 245 242 246 - iowrite32(MODE_11 | BANK(denali->flash_bank) | 2, denali->flash_mem); 243 + iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali), 244 + denali->host + DENALI_HOST_ADDR); 247 245 248 246 for (i = 0; i < len; i++) 249 - iowrite32(buf[i], denali->flash_mem + 0x10); 247 + iowrite32(buf[i], denali->host + DENALI_HOST_DATA); 250 248 } 251 249 252 250 static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) ··· 256 252 uint16_t *buf16 = (uint16_t *)buf; 257 253 int i; 258 254 259 - iowrite32(MODE_11 | BANK(denali->flash_bank) | 2, denali->flash_mem); 255 + iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali), 256 + denali->host + DENALI_HOST_ADDR); 260 257 261 258 for (i = 0; i < len / 2; i++) 262 - buf16[i] = ioread32(denali->flash_mem + 0x10); 259 + buf16[i] = ioread32(denali->host + DENALI_HOST_DATA); 263 260 } 264 261 265 262 static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf, ··· 270 265 const uint16_t *buf16 = (const uint16_t *)buf; 271 266 int i; 272 267 273 - iowrite32(MODE_11 | BANK(denali->flash_bank) | 2, denali->flash_mem); 268 + iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali), 269 + denali->host + DENALI_HOST_ADDR); 274 270 275 271 for (i = 0; i < len / 2; i++) 276 - iowrite32(buf16[i], denali->flash_mem + 0x10); 272 + iowrite32(buf16[i], denali->host + DENALI_HOST_DATA); 277 273 } 278 274 279 275 static uint8_t denali_read_byte(struct mtd_info *mtd) ··· 306 300 uint32_t type; 307 301 308 302 if (ctrl & NAND_CLE) 309 - type = 0; 303 + type = DENALI_MAP11_CMD; 310 304 else if (ctrl & NAND_ALE) 311 - type = 1; 305 + type = DENALI_MAP11_ADDR; 312 306 else 313 307 return; 314 308 ··· 319 313 if (ctrl & NAND_CTRL_CHANGE) 320 314 denali_reset_irq(denali); 321 315 322 - index_addr(denali, MODE_11 | BANK(denali->flash_bank) | type, dat); 316 + denali_host_write(denali, DENALI_BANK(denali) | type, dat); 323 317 } 324 318 325 319 static int denali_dev_ready(struct mtd_info *mtd) ··· 372 366 unsigned long *uncor_ecc_flags) 373 367 { 374 368 struct nand_chip *chip = mtd_to_nand(mtd); 375 - int bank = denali->flash_bank; 369 + int bank = denali->active_bank; 376 370 uint32_t ecc_cor; 377 371 unsigned int max_bitflips; 378 372 379 - ecc_cor = ioread32(denali->flash_reg + ECC_COR_INFO(bank)); 373 + ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank)); 380 374 ecc_cor >>= ECC_COR_INFO__SHIFT(bank); 381 375 382 376 if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) { ··· 425 419 denali_reset_irq(denali); 426 420 427 421 do { 428 - err_addr = ioread32(denali->flash_reg + ECC_ERROR_ADDRESS); 422 + err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS); 429 423 err_sector = ECC_SECTOR(err_addr); 430 424 err_byte = ECC_BYTE(err_addr); 431 425 432 - err_cor_info = ioread32(denali->flash_reg + ERR_CORRECTION_INFO); 426 + err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO); 433 427 err_cor_value = ECC_CORRECTION_VALUE(err_cor_info); 434 428 err_device = ECC_ERR_DEVICE(err_cor_info); 435 429 ··· 455 449 unsigned int flips_in_byte; 456 450 457 451 offset = (err_sector * ecc_size + err_byte) * 458 - denali->devnum + err_device; 452 + denali->devs_per_cs + err_device; 459 453 460 454 /* correct the ECC error */ 461 455 flips_in_byte = hweight8(buf[offset] ^ err_cor_value); ··· 484 478 /* programs the controller to either enable/disable DMA transfers */ 485 479 static void denali_enable_dma(struct denali_nand_info *denali, bool en) 486 480 { 487 - iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); 488 - ioread32(denali->flash_reg + DMA_ENABLE); 481 + iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->reg + DMA_ENABLE); 482 + ioread32(denali->reg + DMA_ENABLE); 489 483 } 490 484 491 485 static void denali_setup_dma64(struct denali_nand_info *denali, ··· 494 488 uint32_t mode; 495 489 const int page_count = 1; 496 490 497 - mode = MODE_10 | BANK(denali->flash_bank) | page; 491 + mode = DENALI_MAP10 | DENALI_BANK(denali) | page; 498 492 499 493 /* DMA is a three step process */ 500 494 ··· 502 496 * 1. setup transfer type, interrupt when complete, 503 497 * burst len = 64 bytes, the number of pages 504 498 */ 505 - index_addr(denali, mode, 506 - 0x01002000 | (64 << 16) | (write << 8) | page_count); 499 + denali_host_write(denali, mode, 500 + 0x01002000 | (64 << 16) | (write << 8) | page_count); 507 501 508 502 /* 2. set memory low address */ 509 - index_addr(denali, mode, dma_addr); 503 + denali_host_write(denali, mode, dma_addr); 510 504 511 505 /* 3. set memory high address */ 512 - index_addr(denali, mode, (uint64_t)dma_addr >> 32); 506 + denali_host_write(denali, mode, (uint64_t)dma_addr >> 32); 513 507 } 514 508 515 509 static void denali_setup_dma32(struct denali_nand_info *denali, ··· 518 512 uint32_t mode; 519 513 const int page_count = 1; 520 514 521 - mode = MODE_10 | BANK(denali->flash_bank); 515 + mode = DENALI_MAP10 | DENALI_BANK(denali); 522 516 523 517 /* DMA is a four step process */ 524 518 525 519 /* 1. setup transfer type and # of pages */ 526 - index_addr(denali, mode | page, 0x2000 | (write << 8) | page_count); 520 + denali_host_write(denali, mode | page, 521 + 0x2000 | (write << 8) | page_count); 527 522 528 523 /* 2. set memory high address bits 23:8 */ 529 - index_addr(denali, mode | ((dma_addr >> 16) << 8), 0x2200); 524 + denali_host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200); 530 525 531 526 /* 3. set memory low address bits 23:8 */ 532 - index_addr(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300); 527 + denali_host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300); 533 528 534 529 /* 4. interrupt when complete, burst len = 64 bytes */ 535 - index_addr(denali, mode | 0x14000, 0x2400); 530 + denali_host_write(denali, mode | 0x14000, 0x2400); 536 531 } 537 532 538 533 static void denali_setup_dma(struct denali_nand_info *denali, ··· 548 541 static int denali_pio_read(struct denali_nand_info *denali, void *buf, 549 542 size_t size, int page, int raw) 550 543 { 551 - uint32_t addr = BANK(denali->flash_bank) | page; 544 + uint32_t addr = DENALI_BANK(denali) | page; 552 545 uint32_t *buf32 = (uint32_t *)buf; 553 546 uint32_t irq_status, ecc_err_mask; 554 547 int i; ··· 560 553 561 554 denali_reset_irq(denali); 562 555 563 - iowrite32(MODE_01 | addr, denali->flash_mem); 556 + iowrite32(DENALI_MAP01 | addr, denali->host + DENALI_HOST_ADDR); 564 557 for (i = 0; i < size / 4; i++) 565 - *buf32++ = ioread32(denali->flash_mem + 0x10); 558 + *buf32++ = ioread32(denali->host + DENALI_HOST_DATA); 566 559 567 560 irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC); 568 561 if (!(irq_status & INTR__PAGE_XFER_INC)) ··· 577 570 static int denali_pio_write(struct denali_nand_info *denali, 578 571 const void *buf, size_t size, int page, int raw) 579 572 { 580 - uint32_t addr = BANK(denali->flash_bank) | page; 573 + uint32_t addr = DENALI_BANK(denali) | page; 581 574 const uint32_t *buf32 = (uint32_t *)buf; 582 575 uint32_t irq_status; 583 576 int i; 584 577 585 578 denali_reset_irq(denali); 586 579 587 - iowrite32(MODE_01 | addr, denali->flash_mem); 580 + iowrite32(DENALI_MAP01 | addr, denali->host + DENALI_HOST_ADDR); 588 581 for (i = 0; i < size / 4; i++) 589 - iowrite32(*buf32++, denali->flash_mem + 0x10); 582 + iowrite32(*buf32++, denali->host + DENALI_HOST_DATA); 590 583 591 584 irq_status = denali_wait_for_irq(denali, 592 585 INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL); ··· 679 672 int ecc_steps = chip->ecc.steps; 680 673 int ecc_size = chip->ecc.size; 681 674 int ecc_bytes = chip->ecc.bytes; 682 - int oob_skip = denali->bbtskipbytes; 675 + int oob_skip = denali->oob_skip_bytes; 683 676 size_t size = writesize + oobsize; 684 677 int i, pos, len; 685 678 ··· 737 730 int ecc_size = chip->ecc.size; 738 731 int ecc_bytes = chip->ecc.bytes; 739 732 void *dma_buf = denali->buf; 740 - int oob_skip = denali->bbtskipbytes; 733 + int oob_skip = denali->oob_skip_bytes; 741 734 size_t size = writesize + oobsize; 742 735 int ret, i, pos, len; 743 736 ··· 868 861 int ecc_size = chip->ecc.size; 869 862 int ecc_bytes = chip->ecc.bytes; 870 863 void *dma_buf = denali->buf; 871 - int oob_skip = denali->bbtskipbytes; 864 + int oob_skip = denali->oob_skip_bytes; 872 865 size_t size = writesize + oobsize; 873 866 int i, pos, len; 874 867 ··· 949 942 { 950 943 struct denali_nand_info *denali = mtd_to_denali(mtd); 951 944 952 - denali->flash_bank = chip; 945 + denali->active_bank = chip; 953 946 } 954 947 955 948 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) ··· 966 959 static int denali_erase(struct mtd_info *mtd, int page) 967 960 { 968 961 struct denali_nand_info *denali = mtd_to_denali(mtd); 969 - uint32_t cmd, irq_status; 962 + uint32_t irq_status; 970 963 971 964 denali_reset_irq(denali); 972 965 973 - /* setup page read request for access type */ 974 - cmd = MODE_10 | BANK(denali->flash_bank) | page; 975 - index_addr(denali, cmd, 0x1); 966 + denali_host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page, 967 + DENALI_ERASE); 976 968 977 969 /* wait for erase to complete or failure to occur */ 978 970 irq_status = denali_wait_for_irq(denali, ··· 1010 1004 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk); 1011 1005 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE); 1012 1006 1013 - tmp = ioread32(denali->flash_reg + ACC_CLKS); 1007 + tmp = ioread32(denali->reg + ACC_CLKS); 1014 1008 tmp &= ~ACC_CLKS__VALUE; 1015 1009 tmp |= acc_clks; 1016 - iowrite32(tmp, denali->flash_reg + ACC_CLKS); 1010 + iowrite32(tmp, denali->reg + ACC_CLKS); 1017 1011 1018 1012 /* tRWH -> RE_2_WE */ 1019 1013 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk); 1020 1014 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE); 1021 1015 1022 - tmp = ioread32(denali->flash_reg + RE_2_WE); 1016 + tmp = ioread32(denali->reg + RE_2_WE); 1023 1017 tmp &= ~RE_2_WE__VALUE; 1024 1018 tmp |= re_2_we; 1025 - iowrite32(tmp, denali->flash_reg + RE_2_WE); 1019 + iowrite32(tmp, denali->reg + RE_2_WE); 1026 1020 1027 1021 /* tRHZ -> RE_2_RE */ 1028 1022 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk); 1029 1023 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE); 1030 1024 1031 - tmp = ioread32(denali->flash_reg + RE_2_RE); 1025 + tmp = ioread32(denali->reg + RE_2_RE); 1032 1026 tmp &= ~RE_2_RE__VALUE; 1033 1027 tmp |= re_2_re; 1034 - iowrite32(tmp, denali->flash_reg + RE_2_RE); 1028 + iowrite32(tmp, denali->reg + RE_2_RE); 1035 1029 1036 1030 /* tWHR -> WE_2_RE */ 1037 1031 we_2_re = DIV_ROUND_UP(timings->tWHR_min, t_clk); 1038 1032 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE); 1039 1033 1040 - tmp = ioread32(denali->flash_reg + TWHR2_AND_WE_2_RE); 1034 + tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); 1041 1035 tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE; 1042 1036 tmp |= we_2_re; 1043 - iowrite32(tmp, denali->flash_reg + TWHR2_AND_WE_2_RE); 1037 + iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE); 1044 1038 1045 1039 /* tADL -> ADDR_2_DATA */ 1046 1040 ··· 1052 1046 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk); 1053 1047 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask); 1054 1048 1055 - tmp = ioread32(denali->flash_reg + TCWAW_AND_ADDR_2_DATA); 1049 + tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); 1056 1050 tmp &= ~addr_2_data_mask; 1057 1051 tmp |= addr_2_data; 1058 - iowrite32(tmp, denali->flash_reg + TCWAW_AND_ADDR_2_DATA); 1052 + iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA); 1059 1053 1060 1054 /* tREH, tWH -> RDWR_EN_HI_CNT */ 1061 1055 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), 1062 1056 t_clk); 1063 1057 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE); 1064 1058 1065 - tmp = ioread32(denali->flash_reg + RDWR_EN_HI_CNT); 1059 + tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); 1066 1060 tmp &= ~RDWR_EN_HI_CNT__VALUE; 1067 1061 tmp |= rdwr_en_hi; 1068 - iowrite32(tmp, denali->flash_reg + RDWR_EN_HI_CNT); 1062 + iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); 1069 1063 1070 1064 /* tRP, tWP -> RDWR_EN_LO_CNT */ 1071 1065 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), ··· 1076 1070 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi); 1077 1071 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE); 1078 1072 1079 - tmp = ioread32(denali->flash_reg + RDWR_EN_LO_CNT); 1073 + tmp = ioread32(denali->reg + RDWR_EN_LO_CNT); 1080 1074 tmp &= ~RDWR_EN_LO_CNT__VALUE; 1081 1075 tmp |= rdwr_en_lo; 1082 - iowrite32(tmp, denali->flash_reg + RDWR_EN_LO_CNT); 1076 + iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); 1083 1077 1084 1078 /* tCS, tCEA -> CS_SETUP_CNT */ 1085 1079 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo, ··· 1087 1081 0); 1088 1082 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE); 1089 1083 1090 - tmp = ioread32(denali->flash_reg + CS_SETUP_CNT); 1084 + tmp = ioread32(denali->reg + CS_SETUP_CNT); 1091 1085 tmp &= ~CS_SETUP_CNT__VALUE; 1092 1086 tmp |= cs_setup; 1093 - iowrite32(tmp, denali->flash_reg + CS_SETUP_CNT); 1087 + iowrite32(tmp, denali->reg + CS_SETUP_CNT); 1094 1088 1095 1089 return 0; 1096 1090 } ··· 1101 1095 int i; 1102 1096 1103 1097 for (i = 0; i < denali->max_banks; i++) { 1104 - denali->flash_bank = i; 1098 + denali->active_bank = i; 1105 1099 1106 1100 denali_reset_irq(denali); 1107 1101 1108 1102 iowrite32(DEVICE_RESET__BANK(i), 1109 - denali->flash_reg + DEVICE_RESET); 1103 + denali->reg + DEVICE_RESET); 1110 1104 1111 1105 irq_status = denali_wait_for_irq(denali, 1112 1106 INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT); ··· 1125 1119 * override it. 1126 1120 */ 1127 1121 if (!denali->revision) 1128 - denali->revision = 1129 - swab16(ioread32(denali->flash_reg + REVISION)); 1122 + denali->revision = swab16(ioread32(denali->reg + REVISION)); 1130 1123 1131 1124 /* 1132 1125 * tell driver how many bit controller will skip before ··· 1133 1128 * set by firmware. So we read this value out. 1134 1129 * if this value is 0, just let it be. 1135 1130 */ 1136 - denali->bbtskipbytes = ioread32(denali->flash_reg + 1137 - SPARE_AREA_SKIP_BYTES); 1131 + denali->oob_skip_bytes = ioread32(denali->reg + SPARE_AREA_SKIP_BYTES); 1138 1132 detect_max_banks(denali); 1139 - iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); 1140 - iowrite32(CHIP_EN_DONT_CARE__FLAG, 1141 - denali->flash_reg + CHIP_ENABLE_DONT_CARE); 1133 + iowrite32(0x0F, denali->reg + RB_PIN_ENABLED); 1134 + iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); 1142 1135 1143 - iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); 1136 + iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); 1144 1137 1145 1138 /* Should set value for these registers when init */ 1146 - iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); 1147 - iowrite32(1, denali->flash_reg + ECC_ENABLE); 1139 + iowrite32(0, denali->reg + TWO_ROW_ADDR_CYCLES); 1140 + iowrite32(1, denali->reg + ECC_ENABLE); 1148 1141 } 1149 1142 1150 1143 int denali_calc_ecc_bytes(int step_size, int strength) ··· 1155 1152 static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip, 1156 1153 struct denali_nand_info *denali) 1157 1154 { 1158 - int oobavail = mtd->oobsize - denali->bbtskipbytes; 1155 + int oobavail = mtd->oobsize - denali->oob_skip_bytes; 1159 1156 int ret; 1160 1157 1161 1158 /* ··· 1188 1185 if (section) 1189 1186 return -ERANGE; 1190 1187 1191 - oobregion->offset = denali->bbtskipbytes; 1188 + oobregion->offset = denali->oob_skip_bytes; 1192 1189 oobregion->length = chip->ecc.total; 1193 1190 1194 1191 return 0; ··· 1203 1200 if (section) 1204 1201 return -ERANGE; 1205 1202 1206 - oobregion->offset = chip->ecc.total + denali->bbtskipbytes; 1203 + oobregion->offset = chip->ecc.total + denali->oob_skip_bytes; 1207 1204 oobregion->length = mtd->oobsize - oobregion->offset; 1208 1205 1209 1206 return 0; ··· 1242 1239 * In this case, the core framework knows nothing about this fact, 1243 1240 * so we should tell it the _logical_ pagesize and anything necessary. 1244 1241 */ 1245 - denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); 1242 + denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED); 1246 1243 1247 1244 /* 1248 1245 * On some SoCs, DEVICES_CONNECTED is not auto-detected. 1249 1246 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case. 1250 1247 */ 1251 - if (denali->devnum == 0) { 1252 - denali->devnum = 1; 1253 - iowrite32(1, denali->flash_reg + DEVICES_CONNECTED); 1248 + if (denali->devs_per_cs == 0) { 1249 + denali->devs_per_cs = 1; 1250 + iowrite32(1, denali->reg + DEVICES_CONNECTED); 1254 1251 } 1255 1252 1256 - if (denali->devnum == 1) 1253 + if (denali->devs_per_cs == 1) 1257 1254 return 0; 1258 1255 1259 - if (denali->devnum != 2) { 1256 + if (denali->devs_per_cs != 2) { 1260 1257 dev_err(denali->dev, "unsupported number of devices %d\n", 1261 - denali->devnum); 1258 + denali->devs_per_cs); 1262 1259 return -EINVAL; 1263 1260 } 1264 1261 ··· 1276 1273 chip->ecc.size <<= 1; 1277 1274 chip->ecc.bytes <<= 1; 1278 1275 chip->ecc.strength <<= 1; 1279 - denali->bbtskipbytes <<= 1; 1276 + denali->oob_skip_bytes <<= 1; 1280 1277 1281 1278 return 0; 1282 1279 } ··· 1304 1301 denali_enable_irq(denali); 1305 1302 denali_reset_banks(denali); 1306 1303 1307 - denali->flash_bank = CHIP_SELECT_INVALID; 1304 + denali->active_bank = DENALI_INVALID_BANK; 1308 1305 1309 1306 nand_set_flash_node(chip, denali->dev->of_node); 1310 1307 /* Fallback to the default name if DT did not give "label" property */ ··· 1333 1330 if (ret) 1334 1331 goto disable_irq; 1335 1332 1336 - if (ioread32(denali->flash_reg + FEATURES) & FEATURES__DMA) 1333 + if (ioread32(denali->reg + FEATURES) & FEATURES__DMA) 1337 1334 denali->dma_avail = 1; 1338 1335 1339 1336 if (denali->dma_avail) { ··· 1377 1374 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); 1378 1375 1379 1376 iowrite32(MAKE_ECC_CORRECTION(chip->ecc.strength, 1), 1380 - denali->flash_reg + ECC_CORRECTION); 1377 + denali->reg + ECC_CORRECTION); 1381 1378 iowrite32(mtd->erasesize / mtd->writesize, 1382 - denali->flash_reg + PAGES_PER_BLOCK); 1379 + denali->reg + PAGES_PER_BLOCK); 1383 1380 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, 1384 - denali->flash_reg + DEVICE_WIDTH); 1385 - iowrite32(mtd->writesize, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); 1386 - iowrite32(mtd->oobsize, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); 1381 + denali->reg + DEVICE_WIDTH); 1382 + iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); 1383 + iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); 1387 1384 1388 - iowrite32(chip->ecc.size, denali->flash_reg + CFG_DATA_BLOCK_SIZE); 1389 - iowrite32(chip->ecc.size, denali->flash_reg + CFG_LAST_DATA_BLOCK_SIZE); 1385 + iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); 1386 + iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); 1390 1387 /* chip->ecc.steps is set by nand_scan_tail(); not available here */ 1391 1388 iowrite32(mtd->writesize / chip->ecc.size, 1392 - denali->flash_reg + CFG_NUM_DATA_BLOCKS); 1389 + denali->reg + CFG_NUM_DATA_BLOCKS); 1393 1390 1394 1391 mtd_set_ooblayout(mtd, &denali_ooblayout_ops); 1395 1392
+5 -10
drivers/mtd/nand/denali.h
··· 303 303 #define CHNL_ACTIVE__CHANNEL2 BIT(2) 304 304 #define CHNL_ACTIVE__CHANNEL3 BIT(3) 305 305 306 - #define MODE_00 0x00000000 307 - #define MODE_01 0x04000000 308 - #define MODE_10 0x08000000 309 - #define MODE_11 0x0C000000 310 - 311 306 struct denali_nand_info { 312 307 struct nand_chip nand; 313 308 unsigned long clk_x_rate; /* bus interface clock rate */ 314 - int flash_bank; /* currently selected chip */ 309 + int active_bank; /* currently selected bank */ 315 310 struct device *dev; 316 - void __iomem *flash_reg; /* Register Interface */ 317 - void __iomem *flash_mem; /* Host Data/Command Interface */ 311 + void __iomem *reg; /* Register Interface */ 312 + void __iomem *host; /* Host Data/Command Interface */ 318 313 319 314 /* elements used by ISR */ 320 315 struct completion complete; ··· 321 326 void *buf; 322 327 dma_addr_t dma_addr; 323 328 int dma_avail; 324 - int devnum; /* represent how many nands connected */ 325 - int bbtskipbytes; 329 + int devs_per_cs; /* devices connected in parallel */ 330 + int oob_skip_bytes; 326 331 int max_banks; 327 332 unsigned int revision; 328 333 unsigned int caps;
+6 -6
drivers/mtd/nand/denali_dt.c
··· 104 104 } 105 105 106 106 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "denali_reg"); 107 - denali->flash_reg = devm_ioremap_resource(&pdev->dev, res); 108 - if (IS_ERR(denali->flash_reg)) 109 - return PTR_ERR(denali->flash_reg); 107 + denali->reg = devm_ioremap_resource(&pdev->dev, res); 108 + if (IS_ERR(denali->reg)) 109 + return PTR_ERR(denali->reg); 110 110 111 111 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); 112 - denali->flash_mem = devm_ioremap_resource(&pdev->dev, res); 113 - if (IS_ERR(denali->flash_mem)) 114 - return PTR_ERR(denali->flash_mem); 112 + denali->host = devm_ioremap_resource(&pdev->dev, res); 113 + if (IS_ERR(denali->host)) 114 + return PTR_ERR(denali->host); 115 115 116 116 dt->clk = devm_clk_get(&pdev->dev, NULL); 117 117 if (IS_ERR(dt->clk)) {
+8 -8
drivers/mtd/nand/denali_pci.c
··· 78 78 return ret; 79 79 } 80 80 81 - denali->flash_reg = ioremap_nocache(csr_base, csr_len); 82 - if (!denali->flash_reg) { 81 + denali->reg = ioremap_nocache(csr_base, csr_len); 82 + if (!denali->reg) { 83 83 dev_err(&dev->dev, "Spectra: Unable to remap memory region\n"); 84 84 return -ENOMEM; 85 85 } 86 86 87 - denali->flash_mem = ioremap_nocache(mem_base, mem_len); 88 - if (!denali->flash_mem) { 87 + denali->host = ioremap_nocache(mem_base, mem_len); 88 + if (!denali->host) { 89 89 dev_err(&dev->dev, "Spectra: ioremap_nocache failed!"); 90 90 ret = -ENOMEM; 91 91 goto failed_remap_reg; ··· 100 100 return 0; 101 101 102 102 failed_remap_mem: 103 - iounmap(denali->flash_mem); 103 + iounmap(denali->host); 104 104 failed_remap_reg: 105 - iounmap(denali->flash_reg); 105 + iounmap(denali->reg); 106 106 return ret; 107 107 } 108 108 ··· 112 112 struct denali_nand_info *denali = pci_get_drvdata(dev); 113 113 114 114 denali_remove(denali); 115 - iounmap(denali->flash_reg); 116 - iounmap(denali->flash_mem); 115 + iounmap(denali->reg); 116 + iounmap(denali->host); 117 117 } 118 118 119 119 static struct pci_driver denali_pci_driver = {