Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_b

Since now there is support for configuring the HS Rate B mode properly,
let's move the register setting to tbls_hs_b struct for all SoCs.

This allows the PHY to be configured in Rate A initially and then in
Rate B if requested by the UFS driver.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-7-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Manivannan Sadhasivam and committed by
Vinod Koul
0cf7620e baf8d17e

+32 -5
+32 -5
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
··· 219 219 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 220 220 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), 221 221 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), 222 + }; 222 223 223 - /* Rate B */ 224 + static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = { 224 225 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), 225 226 }; 226 227 ··· 297 296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), 298 297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), 299 298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), 299 + }; 300 300 301 - /* Rate B */ 301 + static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = { 302 302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), 303 303 }; 304 304 ··· 364 362 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), 365 363 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 366 364 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 365 + }; 367 366 368 - /* Rate B */ 367 + static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = { 369 368 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), 370 369 }; 371 370 ··· 414 411 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 415 412 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 416 413 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 417 - 418 414 }; 419 415 420 416 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { ··· 451 449 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), 452 450 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 453 451 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 452 + }; 454 453 455 - /* Rate B */ 454 + static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = { 456 455 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), 457 456 }; 458 457 ··· 687 684 .pcs = sm8350_ufsphy_pcs, 688 685 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 689 686 }, 687 + .tbls_hs_b = { 688 + .serdes = sm8350_ufsphy_hs_b_serdes, 689 + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 690 + }, 690 691 .clk_list = sdm845_ufs_phy_clk_l, 691 692 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 692 693 .vreg_list = qmp_phy_vreg_l, ··· 710 703 .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx), 711 704 .pcs = sdm845_ufsphy_pcs, 712 705 .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs), 706 + }, 707 + .tbls_hs_b = { 708 + .serdes = sdm845_ufsphy_hs_b_serdes, 709 + .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), 713 710 }, 714 711 .clk_list = sdm845_ufs_phy_clk_l, 715 712 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ··· 739 728 .pcs = sm6115_ufsphy_pcs, 740 729 .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs), 741 730 }, 731 + .tbls_hs_b = { 732 + .serdes = sm6115_ufsphy_hs_b_serdes, 733 + .serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), 734 + }, 742 735 .clk_list = sdm845_ufs_phy_clk_l, 743 736 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 744 737 .vreg_list = qmp_phy_vreg_l, ··· 765 750 .pcs = sm8150_ufsphy_pcs, 766 751 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), 767 752 }, 753 + .tbls_hs_b = { 754 + .serdes = sm8150_ufsphy_hs_b_serdes, 755 + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 756 + }, 768 757 .clk_list = sdm845_ufs_phy_clk_l, 769 758 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 770 759 .vreg_list = qmp_phy_vreg_l, ··· 789 770 .pcs = sm8350_ufsphy_pcs, 790 771 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 791 772 }, 773 + .tbls_hs_b = { 774 + .serdes = sm8350_ufsphy_hs_b_serdes, 775 + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 776 + }, 792 777 .clk_list = sdm845_ufs_phy_clk_l, 793 778 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 794 779 .vreg_list = qmp_phy_vreg_l, ··· 812 789 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 813 790 .pcs = sm8350_ufsphy_pcs, 814 791 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 792 + }, 793 + .tbls_hs_b = { 794 + .serdes = sm8350_ufsphy_hs_b_serdes, 795 + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 815 796 }, 816 797 .clk_list = sm8450_ufs_phy_clk_l, 817 798 .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),