Initial blind fixup for arm for irq changes

Untested, but this should fix up the bulk of the totally mechanical
issues, and should make the actual detail fixing easier.

Signed-off-by: Linus Torvalds <[e-mail]>

arch/arm/common/locomo.c

···
 #define	LOCOMO_IRQ_LT_START	(IRQ_LOCOMO_LT)
 #define	LOCOMO_IRQ_SPI_START	(IRQ_LOCOMO_SPI_RFR)
 
-static void locomo_handler(unsigned int irq, struct irqdesc *desc,
-			struct pt_regs *regs)
+static void locomo_handler(unsigned int irq, struct irqdesc *desc)
 {
 	int req, i;
 	struct irqdesc *d;
···
 		d = irq_desc + irq;
 		for (i = 0; i <= 3; i++, d++, irq++) {
 			if (req & (0x0100 << i)) {
-				desc_handle_irq(irq, d, regs);
+				desc_handle_irq(irq, d);
 			}
 
 		}
···
 	.unmask	= locomo_unmask_irq,
 };
 
-static void locomo_key_handler(unsigned int irq, struct irqdesc *desc,
-			    struct pt_regs *regs)
+static void locomo_key_handler(unsigned int irq, struct irqdesc *desc)
 {
 	struct irqdesc *d;
 	void __iomem *mapbase = get_irq_chipdata(irq);
 
 	if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) {
 		d = irq_desc + LOCOMO_IRQ_KEY_START;
-		desc_handle_irq(LOCOMO_IRQ_KEY_START, d, regs);
+		desc_handle_irq(LOCOMO_IRQ_KEY_START, d);
 	}
 }
 
···
 	.unmask	= locomo_key_unmask_irq,
 };
 
-static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc,
-			     struct pt_regs *regs)
+static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc)
 {
 	int req, i;
 	struct irqdesc *d;
···
 		d = irq_desc + LOCOMO_IRQ_GPIO_START;
 		for (i = 0; i <= 15; i++, irq++, d++) {
 			if (req & (0x0001 << i)) {
-				desc_handle_irq(irq, d, regs);
+				desc_handle_irq(irq, d);
 			}
 		}
 	}
···
 	.unmask	= locomo_gpio_unmask_irq,
 };
 
-static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc,
-			   struct pt_regs *regs)
+static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc)
 {
 	struct irqdesc *d;
 	void __iomem *mapbase = get_irq_chipdata(irq);
 
 	if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) {
 		d = irq_desc + LOCOMO_IRQ_LT_START;
-		desc_handle_irq(LOCOMO_IRQ_LT_START, d, regs);
+		desc_handle_irq(LOCOMO_IRQ_LT_START, d);
 	}
 }
 
···
 	.unmask	= locomo_lt_unmask_irq,
 };
 
-static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc,
-			    struct pt_regs *regs)
+static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc)
 {
 	int req, i;
 	struct irqdesc *d;
···
 
 		for (i = 0; i <= 3; i++, irq++, d++) {
 			if (req & (0x0001 << i)) {
-				desc_handle_irq(irq, d, regs);
+				desc_handle_irq(irq, d);
 			}
 		}
 	}

arch/arm/common/sa1111.c

···
  * will call us again if there are more interrupts to process.
  */
 static void
-sa1111_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+sa1111_irq_handler(unsigned int irq, struct irqdesc *desc)
 {
 	unsigned int stat0, stat1, i;
 	void __iomem *base = get_irq_data(irq);
···
 	sa1111_writel(stat1, base + SA1111_INTSTATCLR1);
 
 	if (stat0 == 0 && stat1 == 0) {
-		do_bad_IRQ(irq, desc, regs);
+		do_bad_IRQ(irq, desc);
 		return;
 	}
 
 	for (i = IRQ_SA1111_START; stat0; i++, stat0 >>= 1)
 		if (stat0 & 1)
-			handle_edge_irq(i, irq_desc + i, regs);
+			handle_edge_irq(i, irq_desc + i);
 
 	for (i = IRQ_SA1111_START + 32; stat1; i++, stat1 >>= 1)
 		if (stat1 & 1)
-			handle_edge_irq(i, irq_desc + i, regs);
+			handle_edge_irq(i, irq_desc + i);
 
 	/* For level-based interrupts */
 	desc->chip->unmask(irq);

arch/arm/common/sharpsl_pm.c

···
 }
 
 
-irqreturn_t sharpsl_ac_isr(int irq, void *dev_id, struct pt_regs *fp)
+irqreturn_t sharpsl_ac_isr(int irq, void *dev_id)
 {
 	/* Delay the event slightly to debounce */
 	/* Must be a smaller delay than the chrg_full_isr below */
···
 /* Charging Finished Interrupt (Not present on Corgi) */
 /* Can trigger at the same time as an AC staus change so
    delay until after that has been processed */
-irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id, struct pt_regs *fp)
+irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id)
 {
 	if (sharpsl_pm.flags & SHARPSL_SUSPENDED)
 		return IRQ_HANDLED;
···
 	return IRQ_HANDLED;
 }
 
-irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id, struct pt_regs *fp)
+irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id)
 {
 	int is_fatal = 0;
 

arch/arm/common/time-acorn.c

···
 }
 
 static irqreturn_t
-ioc_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+ioc_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
-	timer_tick(regs);
+	timer_tick();
 	write_sequnlock(&xtime_lock);
 	return IRQ_HANDLED;
 }

arch/arm/kernel/ecard.c

···
 }
 
 static void
-ecard_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+ecard_irq_handler(unsigned int irq, struct irqdesc *desc)
 {
 	ecard_t *ec;
 	int called = 0;
···
 
 		if (pending) {
 			struct irqdesc *d = irq_desc + ec->irq;
-			desc_handle_irq(ec->irq, d, regs);
+			desc_handle_irq(ec->irq, d);
 			called ++;
 		}
 	}
···
 };
 
 static void
-ecard_irqexp_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+ecard_irqexp_handler(unsigned int irq, struct irqdesc *desc)
 {
 	const unsigned int statusmask = 15;
 	unsigned int status;
···
 			 * Serial cards should go in 0/1, ethernet/scsi in 2/3
 			 * otherwise you will lose serial data at high speeds!
 			 */
-			desc_handle_irq(ec->irq, d, regs);
+			desc_handle_irq(ec->irq, d);
 		} else {
 			printk(KERN_WARNING "card%d: interrupt from unclaimed "
 			       "card???\n", slot);

arch/arm/kernel/irq.c

···
 
 	irq_enter();
 
-	desc_handle_irq(irq, desc, regs);
+	set_irq_regs(regs);
+	desc_handle_irq(irq, desc);
 
 	/* AT91 specific workaround */
 	irq_finish(irq);

arch/arm/kernel/time.c

···
 /*
  * Kernel system timer support.
  */
-void timer_tick(struct pt_regs *regs)
+void timer_tick(void)
 {
+	struct pt_regs *regs = get_irq_regs();
 	profile_tick(CPU_PROFILING, regs);
 	do_leds();
 	do_set_rtc();

arch/arm/mach-aaec2000/core.c

···
 
 /* We enter here with IRQs enabled */
 static irqreturn_t
-aaec2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+aaec2000_timer_interrupt(int irq, void *dev_id)
 {
 	/* TODO: Check timer accuracy */
 	write_seqlock(&xtime_lock);
 
-	timer_tick(regs);
+	timer_tick();
 	TIMER1_CLEAR = 1;
 
 	write_sequnlock(&xtime_lock);

arch/arm/mach-at91rm9200/at91rm9200_time.c

···
 /*
  * IRQ handler for the timer.
  */
-static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
 {
 	if (at91_sys_read(AT91_ST_SR) & AT91_ST_PITS) {	/* This is a shared interrupt */
 		write_seqlock(&xtime_lock);
 
 		while (((read_CRTR() - last_crtr) & AT91_ST_ALMV) >= LATCH) {
-			timer_tick(regs);
+			timer_tick();
 			last_crtr = (last_crtr + LATCH) & AT91_ST_ALMV;
 		}
 

arch/arm/mach-at91rm9200/gpio.c

···
 	.set_wake	= gpio_irq_set_wake,
 };
 
-static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs *regs)
+static void gpio_irq_handler(unsigned irq, struct irqdesc *desc)
 {
 	unsigned	pin;
 	struct irqdesc	*gpio;
···
 					gpio_irq_mask(pin);
 				}
 				else
-					desc_handle_irq(pin, gpio, regs);
+					desc_handle_irq(pin, gpio);
 			}
 			pin++;
 			gpio++;

arch/arm/mach-clps711x/time.c

···
  * IRQ handler for the timer
  */
 static irqreturn_t
-p720t_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+p720t_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
-	timer_tick(regs);
+	timer_tick();
 	write_sequnlock(&xtime_lock);
 	return IRQ_HANDLED;
 }

arch/arm/mach-clps7500/core.c

···
 extern unsigned long ioc_timer_gettimeoffset(void);
 
 static irqreturn_t
-clps7500_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+clps7500_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
-	timer_tick(regs);
+	timer_tick();
 
 	/* Why not using do_leds interface?? */
 	{

arch/arm/mach-ebsa110/core.c

···
 }
 
 static irqreturn_t
-ebsa110_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+ebsa110_timer_interrupt(int irq, void *dev_id)
 {
 	u32 count;
 
···
 	__raw_writeb(count & 0xff, PIT_T1);
 	__raw_writeb(count >> 8, PIT_T1);
 
-	timer_tick(regs);
+	timer_tick();
 
 	write_sequnlock(&xtime_lock);
 

arch/arm/mach-ep93xx/core.c

···
 
 #define TIMER4_TICKS_PER_JIFFY		((CLOCK_TICK_RATE + (HZ/2)) / HZ)
 
-static int ep93xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+static int ep93xx_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
···
 		(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
 						>= TIMER4_TICKS_PER_JIFFY) {
 		last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
-		timer_tick(regs);
+		timer_tick();
 	}
 
 	write_sequnlock(&xtime_lock);
···
  * EP93xx IRQ handling
  *************************************************************************/
 static void ep93xx_gpio_ab_irq_handler(unsigned int irq,
-		struct irqdesc *desc, struct pt_regs *regs)
+		struct irqdesc *desc)
 {
 	unsigned char status;
 	int i;
···
 	for (i = 0; i < 8; i++) {
 		if (status & (1 << i)) {
 			desc = irq_desc + IRQ_EP93XX_GPIO(0) + i;
-			desc_handle_irq(IRQ_EP93XX_GPIO(0) + i, desc, regs);
+			desc_handle_irq(IRQ_EP93XX_GPIO(0) + i, desc);
 		}
 	}
 
···
 	for (i = 0; i < 8; i++) {
 		if (status & (1 << i)) {
 			desc = irq_desc + IRQ_EP93XX_GPIO(8) + i;
-			desc_handle_irq(IRQ_EP93XX_GPIO(8) + i, desc, regs);
+			desc_handle_irq(IRQ_EP93XX_GPIO(8) + i, desc);
 		}
 	}
 }

arch/arm/mach-footbridge/dc21285-timer.c

···
 }
 
 static irqreturn_t
-timer1_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+timer1_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
 	*CSR_TIMER1_CLR = 0;
 
-	timer_tick(regs);
+	timer_tick();
 
 	write_sequnlock(&xtime_lock);
 

arch/arm/mach-footbridge/dc21285.c

···
 /*
  * Warn on PCI errors.
  */
-static irqreturn_t dc21285_abort_irq(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t dc21285_abort_irq(int irq, void *dev_id)
 {
 	unsigned int cmd;
 	unsigned int status;
···
 
 	if (status & PCI_STATUS_REC_MASTER_ABORT) {
 		printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n",
-			instruction_pointer(regs));
+			instruction_pointer(get_irq_regs()));
 		cmd |= PCI_STATUS_REC_MASTER_ABORT << 16;
 	}
 
···
 	return IRQ_HANDLED;
 }
 
-static irqreturn_t dc21285_serr_irq(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t dc21285_serr_irq(int irq, void *dev_id)
 {
 	struct timer_list *timer = dev_id;
 	unsigned int cntl;
···
 	return IRQ_HANDLED;
 }
 
-static irqreturn_t dc21285_discard_irq(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t dc21285_discard_irq(int irq, void *dev_id)
 {
 	printk(KERN_DEBUG "PCI: discard timer expired\n");
 	*CSR_SA110_CNTL &= 0xffffde07;
···
 	return IRQ_HANDLED;
 }
 
-static irqreturn_t dc21285_dparity_irq(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t dc21285_dparity_irq(int irq, void *dev_id)
 {
 	unsigned int cmd;
 
···
 	return IRQ_HANDLED;
 }
 
-static irqreturn_t dc21285_parity_irq(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t dc21285_parity_irq(int irq, void *dev_id)
 {
 	struct timer_list *timer = dev_id;
 	unsigned int cmd;

arch/arm/mach-footbridge/isa-irq.c

···
 };
 
 static void
-isa_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+isa_irq_handler(unsigned int irq, struct irqdesc *desc)
 {
 	unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
 
 	if (isa_irq < _ISA_IRQ(0) || isa_irq >= _ISA_IRQ(16)) {
-		do_bad_IRQ(isa_irq, desc, regs);
+		do_bad_IRQ(isa_irq, desc);
 		return;
 	}
 
 	desc = irq_desc + isa_irq;
-	desc_handle_irq(isa_irq, desc, regs);
+	desc_handle_irq(isa_irq, desc);
 }
 
 static struct irqaction irq_cascade = {

arch/arm/mach-footbridge/isa-timer.c

···
 }
 
 static irqreturn_t
-isa_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+isa_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
-	timer_tick(regs);
+	timer_tick();
 	write_sequnlock(&xtime_lock);
 	return IRQ_HANDLED;
 }

arch/arm/mach-h720x/common.c

···
 
 static void
 h720x_gpio_handler(unsigned int mask, unsigned int irq,
-                 struct irqdesc *desc, struct pt_regs *regs)
+                 struct irqdesc *desc)
 {
 	IRQDBG("%s irq: %d\n",__FUNCTION__,irq);
 	desc = irq_desc + irq;
 	while (mask) {
 		if (mask & 1) {
 			IRQDBG("handling irq %d\n", irq);
-			desc_handle_irq(irq, desc, regs);
+			desc_handle_irq(irq, desc);
 		}
 		irq++;
 		desc++;
···
 }
 
 static void
-h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
-			struct pt_regs *regs)
+h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 {
 	unsigned int mask, irq;
 
 	mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
 	irq = IRQ_CHAINED_GPIOA(0);
 	IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
-	h720x_gpio_handler(mask, irq, desc, regs);
+	h720x_gpio_handler(mask, irq, desc);
 }
 
 static void
-h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
-			struct pt_regs *regs)
+h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 {
 	unsigned int mask, irq;
 	mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
 	irq = IRQ_CHAINED_GPIOB(0);
 	IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
-	h720x_gpio_handler(mask, irq, desc, regs);
+	h720x_gpio_handler(mask, irq, desc);
 }
 
 static void
-h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
-			struct pt_regs *regs)
+h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 {
 	unsigned int mask, irq;
 
 	mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
 	irq = IRQ_CHAINED_GPIOC(0);
 	IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
-	h720x_gpio_handler(mask, irq, desc, regs);
+	h720x_gpio_handler(mask, irq, desc);
 }
 
 static void
-h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
-			struct pt_regs *regs)
+h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 {
 	unsigned int mask, irq;
 
 	mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
 	irq = IRQ_CHAINED_GPIOD(0);
 	IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
-	h720x_gpio_handler(mask, irq, desc, regs);
+	h720x_gpio_handler(mask, irq, desc);
 }
 
 #ifdef CONFIG_CPU_H7202
 static void
-h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
-			struct pt_regs *regs)
+h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 {
 	unsigned int mask, irq;
 
 	mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
 	irq = IRQ_CHAINED_GPIOE(0);
 	IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
-	h720x_gpio_handler(mask, irq, desc, regs);
+	h720x_gpio_handler(mask, irq, desc);
 }
 #endif
 

arch/arm/mach-h720x/cpu-h7201.c

···
  * Timer interrupt handler
  */
 static irqreturn_t
-h7201_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+h7201_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
 	CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
-	timer_tick(regs);
+	timer_tick();
 
 	write_sequnlock(&xtime_lock);
 

arch/arm/mach-h720x/cpu-h7202.c

···
  * we have to handle all timer interrupts in one place.
  */
 static void
-h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
-			struct pt_regs *regs)
+h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 {
 	unsigned int mask, irq;
 
···
 
 	if ( mask & TSTAT_T0INT ) {
 		write_seqlock(&xtime_lock);
-		timer_tick(regs);
+		timer_tick();
 		write_sequnlock(&xtime_lock);
 		if( mask == TSTAT_T0INT )
 			return;
···
 	desc = irq_desc + irq;
 	while (mask) {
 		if (mask & 1)
-			desc_handle_irq(irq, desc, regs);
+			desc_handle_irq(irq, desc);
 		irq++;
 		desc++;
 		mask >>= 1;
···
  * Timer interrupt handler
  */
 static irqreturn_t
-h7202_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+h7202_timer_interrupt(int irq, void *dev_id)
 {
-	h7202_timerx_demux_handler(0, NULL, regs);
+	h7202_timerx_demux_handler(0, NULL);
 	return IRQ_HANDLED;
 }
 

arch/arm/mach-imx/dma.c

···
  */
 int
 imx_dma_setup_handlers(imx_dmach_t dma_ch,
-		       void (*irq_handler) (int, void *, struct pt_regs *),
-		       void (*err_handler) (int, void *, struct pt_regs *, int),
+		       void (*irq_handler) (int, void *),
+		       void (*err_handler) (int, void *, int),
 		       void *data)
 {
 	struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
···
 	return -ENODEV;
 }
 
-static irqreturn_t dma_err_handler(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t dma_err_handler(int irq, void *dev_id)
 {
 	int i, disr = DISR;
 	struct imx_dma_channel *channel;
···
 		/*imx_dma_channels[i].sg = NULL;*/
 
 		if (channel->name && channel->err_handler) {
-			channel->err_handler(i, channel->data, regs, errcode);
+			channel->err_handler(i, channel->data, errcode);
 			continue;
 		}
 
···
 	return IRQ_HANDLED;
 }
 
-static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 {
 	int i, disr = DISR;
 
···
 				} else {
 					if (channel->irq_handler)
 						channel->irq_handler(i,
-							channel->data, regs);
+							channel->data);
 				}
 			} else {
 				/*

arch/arm/mach-imx/irq.c

···
 
 static void
 imx_gpio_handler(unsigned int mask, unsigned int irq,
-                 struct irqdesc *desc, struct pt_regs *regs)
+                 struct irqdesc *desc)
 {
 	desc = irq_desc + irq;
 	while (mask) {
 		if (mask & 1) {
 			DEBUG_IRQ("handling irq %d\n", irq);
-			desc_handle_irq(irq, desc, regs);
+			desc_handle_irq(irq, desc);
 		}
 		irq++;
 		desc++;
···
 }
 
 static void
-imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
-			struct pt_regs *regs)
+imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 {
 	unsigned int mask, irq;
 
 	mask = ISR(0);
 	irq = IRQ_GPIOA(0);
-	imx_gpio_handler(mask, irq, desc, regs);
+	imx_gpio_handler(mask, irq, desc);
 }
 
 static void
-imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
-			struct pt_regs *regs)
+imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 {
 	unsigned int mask, irq;
 
 	mask = ISR(1);
 	irq = IRQ_GPIOB(0);
-	imx_gpio_handler(mask, irq, desc, regs);
+	imx_gpio_handler(mask, irq, desc);
 }
 
 static void
-imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
-			struct pt_regs *regs)
+imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 {
 	unsigned int mask, irq;
 
 	mask = ISR(2);
 	irq = IRQ_GPIOC(0);
-	imx_gpio_handler(mask, irq, desc, regs);
+	imx_gpio_handler(mask, irq, desc);
 }
 
 static void
-imx_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
-			struct pt_regs *regs)
+imx_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 {
 	unsigned int mask, irq;
 
 	mask = ISR(3);
 	irq = IRQ_GPIOD(0);
-	imx_gpio_handler(mask, irq, desc, regs);
+	imx_gpio_handler(mask, irq, desc);
 }
 
 static struct irq_chip imx_internal_chip = {

arch/arm/mach-imx/time.c

···
  * IRQ handler for the timer
  */
 static irqreturn_t
-imx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+imx_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
···
 	if (IMX_TSTAT(TIMER_BASE))
 		IMX_TSTAT(TIMER_BASE) = 0;
 
-	timer_tick(regs);
+	timer_tick();
 	write_sequnlock(&xtime_lock);
 
 	return IRQ_HANDLED;

arch/arm/mach-integrator/core.c

···
  * IRQ handler for the timer
  */
 static irqreturn_t
-integrator_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+integrator_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
···
 	 * primary CPU
 	 */
 	if (hard_smp_processor_id() == 0) {
-		timer_tick(regs);
+		timer_tick();
 #ifdef CONFIG_SMP
 		smp_send_timer();
 #endif
···
 	/*
 	 * this is the ARM equivalent of the APIC timer interrupt
 	 */
-	update_process_times(user_mode(regs));
+	update_process_times(user_mode(get_irq_regs()));
 #endif /* CONFIG_SMP */
 
 	write_sequnlock(&xtime_lock);

arch/arm/mach-integrator/integrator_cp.c

···
 };
 
 static void
-sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+sic_handle_irq(unsigned int irq, struct irqdesc *desc)
 {
 	unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
 
 	if (status == 0) {
-		do_bad_IRQ(irq, desc, regs);
+		do_bad_IRQ(irq, desc);
 		return;
 	}
 
···
 		irq += IRQ_SIC_START;
 
 		desc = irq_desc + irq;
-		desc_handle_irq(irq, desc, regs);
+		desc_handle_irq(irq, desc);
 	} while (status);
 }
 

arch/arm/mach-integrator/pci_v3.c

···
 	return 1;
 }
 
-static irqreturn_t v3_irq(int irq, void *devid, struct pt_regs *regs)
+static irqreturn_t v3_irq(int irq, void *devid)
 {
 #ifdef CONFIG_DEBUG_LL
+	struct pt_regs *regs = get_irq_regs();
 	unsigned long pc = instruction_pointer(regs);
 	unsigned long instr = *(unsigned long *)pc;
 	char buf[128];

arch/arm/mach-integrator/time.c

···
 	.set_alarm	= integrator_rtc_set_alarm,
 };
 
-static irqreturn_t arm_rtc_interrupt(int irq, void *dev_id,
-				     struct pt_regs *regs)
+static irqreturn_t arm_rtc_interrupt(int irq, void *dev_id)
 {
 	writel(0, rtc_base + RTC_EOI);
 	return IRQ_HANDLED;

arch/arm/mach-ixp2000/core.c

···
 	return offset / ticks_per_usec;
 }
 
-static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+static int ixp2000_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
···
 
 	while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
 							>= ticks_per_jiffy) {
-		timer_tick(regs);
+		timer_tick();
 		next_jiffy_time -= ticks_per_jiffy;
 	}
 
···
 /*************************************************************************
  * IRQ handling IXP2000
  *************************************************************************/
-static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc)
 {                               
 	int i;
 	unsigned long status = *IXP2000_GPIO_INST;
···
 	for (i = 0; i <= 7; i++) {
 		if (status & (1<<i)) {
 			desc = irq_desc + i + IRQ_IXP2000_GPIO0;
-			desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc, regs);
+			desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc);
 		}
 	}
 }
···
 /*
  * Error interrupts. These are used extensively by the microengine drivers
  */
-static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc,  struct pt_regs *regs)
+static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc)
 {
 	int i;
 	unsigned long status = *IXP2000_IRQ_ERR_STATUS;
···
 	for(i = 31; i >= 0; i--) {
 		if(status & (1 << i)) {
 			desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
-			desc_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc, regs);
+			desc_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc);
 		}
 	}
 }

arch/arm/mach-ixp2000/ixdp2x00.c

···
 		ixp2000_release_slowport(&old_cfg);
 }
 
-static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc)
 {
         volatile u32 ex_interrupt = 0;
 	static struct slowport_cfg old_cfg;
···
 			struct irqdesc *cpld_desc;
 			int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
 			cpld_desc = irq_desc + cpld_irq;
-			desc_handle_irq(cpld_irq, cpld_desc, regs);
+			desc_handle_irq(cpld_irq, cpld_desc);
 		}
 	}
 

arch/arm/mach-ixp2000/ixdp2x01.c

···
 
 static u32 valid_irq_mask;
 
-static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc)
 {
 	u32 ex_interrupt;
 	int i;
···
 			struct irqdesc *cpld_desc;
 			int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
 			cpld_desc = irq_desc + cpld_irq;
-			desc_handle_irq(cpld_irq, cpld_desc, regs);
+			desc_handle_irq(cpld_irq, cpld_desc);
 		}
 	}
 

arch/arm/mach-ixp23xx/core.c

···
 /*
  * TODO: Should this just be done at ASM level?
  */
-static void pci_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+static void pci_handler(unsigned int irq, struct irqdesc *desc)
 {
 	u32 pci_interrupt;
 	unsigned int irqno;
···
 	}
 
 	int_desc = irq_desc + irqno;
-	desc_handle_irq(irqno, int_desc, regs);
+	desc_handle_irq(irqno, int_desc);
 
 	desc->chip->unmask(irq);
 }
···
 }
 
 static irqreturn_t
-ixp23xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+ixp23xx_timer_interrupt(int irq, void *dev_id)
 {
 	/* Clear Pending Interrupt by writing '1' to it */
 	*IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
 	while ((signed long)(*IXP23XX_TIMER_CONT - next_jiffy_time) >= LATCH) {
-		timer_tick(regs);
+		timer_tick();
 		next_jiffy_time += LATCH;
 	}
 

arch/arm/mach-ixp23xx/ixdp2351.c

···
 	*IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
 }
 
-static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc)
 {
 	u16 ex_interrupt =
 		*IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
···
 			int cpld_irq =
 				IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
 			cpld_desc = irq_desc + cpld_irq;
-			desc_handle_irq(cpld_irq, cpld_desc, regs);
+			desc_handle_irq(cpld_irq, cpld_desc);
 		}
 	}
 
···
 	*IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
 }
 
-static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc)
 {
 	u16 ex_interrupt =
 		*IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
···
 			int cpld_irq =
 				IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
 			cpld_desc = irq_desc + cpld_irq;
-			desc_handle_irq(cpld_irq, cpld_desc, regs);
+			desc_handle_irq(cpld_irq, cpld_desc);
 		}
 	}
 

arch/arm/mach-ixp4xx/common.c

···
 
 #define CLOCK_TICKS_PER_USEC	((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
 
-static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
···
 	 * Catch up with the real idea of time
 	 */
 	while ((signed long)(*IXP4XX_OSTS - last_jiffy_time) >= LATCH) {
-		timer_tick(regs);
+		timer_tick();
 		last_jiffy_time += LATCH;
 	}
 

arch/arm/mach-ixp4xx/nas100d-power.c

···
 
 #include <asm/mach-types.h>
 
-static irqreturn_t nas100d_reset_handler(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t nas100d_reset_handler(int irq, void *dev_id)
 {
 	/* Signal init to do the ctrlaltdel action, this will bypass init if
 	 * it hasn't started and do a kernel_restart.

arch/arm/mach-ixp4xx/nslu2-power.c

···
 
 #include <asm/mach-types.h>
 
-static irqreturn_t nslu2_power_handler(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t nslu2_power_handler(int irq, void *dev_id)
 {
 	/* Signal init to do the ctrlaltdel action, this will bypass init if
 	 * it hasn't started and do a kernel_restart.
···
 	return IRQ_HANDLED;
 }
 
-static irqreturn_t nslu2_reset_handler(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t nslu2_reset_handler(int irq, void *dev_id)
 {
 	/* This is the paper-clip reset, it shuts the machine down directly.
 	 */

arch/arm/mach-lh7a40x/arch-kev7a400.c

···
 };
 
 
-static void kev7a400_cpld_handler (unsigned int irq, struct irqdesc *desc,
-				  struct pt_regs *regs)
+static void kev7a400_cpld_handler (unsigned int irq, struct irqdesc *desc)
 {
 	u32 mask = CPLD_LATCHED_INTS;
 	irq = IRQ_KEV7A400_CPLD;
 	for (; mask; mask >>= 1, ++irq) {
 		if (mask & 1)
-			desc[irq].handle (irq, desc, regs);
+			desc[irq].handle (irq, desc);
 	}
 }
 

arch/arm/mach-lh7a40x/arch-lpd7a40x.c

···
 	.unmask	= lh7a40x_unmask_cpld_irq,
 };
 
-static void lpd7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc,
-				  struct pt_regs *regs)
+static void lpd7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc)
 {
 	unsigned int mask = CPLD_INTERRUPTS;
 

arch/arm/mach-lh7a40x/irq-kev7a400.c

···
 };
 
 static void
-lh7a400_cpld_handler (unsigned int irq, struct irqdesc *desc,
-		      struct pt_regs *regs)
+lh7a400_cpld_handler (unsigned int irq, struct irqdesc *desc)
 {
 	u32 mask = CPLD_LATCHED_INTS;
 	irq = IRQ_KEV_7A400_CPLD;
 	for (; mask; mask >>= 1, ++irq) {
 		if (mask & 1)
-			desc[irq].handle (irq, desc, regs);
+			desc[irq].handle (irq, desc);
 	}
 }
 

arch/arm/mach-lh7a40x/irq-lpd7a40x.c

···
 	.unmask	= lh7a40x_unmask_cpld_irq,
 };
 
-static void lh7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc,
-				  struct pt_regs *regs)
+static void lh7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc)
 {
 	unsigned int mask = CPLD_INTERRUPTS;
 

arch/arm/mach-lh7a40x/time.c

···
 #endif
 
 static irqreturn_t
-lh7a40x_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+lh7a40x_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
 	TIMER_EOI = 0;
-	timer_tick(regs);
+	timer_tick();
 
 	write_sequnlock(&xtime_lock);
 

arch/arm/mach-netx/generic.c

···
 #endif
 
 static void
-netx_hif_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
-			struct pt_regs *regs)
+netx_hif_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
 {
 	unsigned int irq = NETX_IRQ_HIF_CHAINED(0);
 	unsigned int stat;
···
 	while (stat) {
 		if (stat & 1) {
 			DEBUG_IRQ("handling irq %d\n", irq);
-			desc_handle_irq(irq, desc, regs);
+			desc_handle_irq(irq, desc);
 		}
 		irq++;
 		desc++;

arch/arm/mach-netx/time.c

···
  * IRQ handler for the timer
  */
 static irqreturn_t
-netx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+netx_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
-	timer_tick(regs);
+	timer_tick();
 	write_sequnlock(&xtime_lock);
 
 	/* acknowledge interrupt */

arch/arm/mach-omap1/board-osk.c

···
 
 #ifdef	CONFIG_PM
 static irqreturn_t
-osk_mistral_wake_interrupt(int irq, void *ignored, struct pt_regs *regs)
+osk_mistral_wake_interrupt(int irq, void *ignored)
 {
 	return IRQ_HANDLED;
 }

arch/arm/mach-omap1/fpga.c

···
 	fpga_ack_irq(irq);
 }
 
-void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc,
-			      struct pt_regs *regs)
+void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc)
 {
 	struct irqdesc *d;
 	u32 stat;
···
 	     fpga_irq++, stat >>= 1) {
 		if (stat & 1) {
 			d = irq_desc + fpga_irq;
-			desc_handle_irq(fpga_irq, d, regs);
+			desc_handle_irq(fpga_irq, d);
 		}
 	}
 }

arch/arm/mach-omap1/pm.c

···
 }
 
 
-static irqreturn_t  omap_wakeup_interrupt(int  irq, void *  dev,
-				     struct pt_regs *  regs)
+static irqreturn_t  omap_wakeup_interrupt(int irq, void *dev)
 {
 	return IRQ_HANDLED;
 }

arch/arm/mach-omap1/serial.c

···
 
 #ifdef CONFIG_OMAP_SERIAL_WAKE
 
-static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id,
-					      struct pt_regs *regs)
+static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id)
 {
 	/* Need to do something with serial port right after wake-up? */
 	return IRQ_HANDLED;

arch/arm/mach-omap1/time.c

···
  * Latency during the interrupt is calculated using timer1.
  * Both timer0 and timer1 are counting at 6MHz (P2 6.5MHz).
  */
-static irqreturn_t omap_mpu_timer_interrupt(int irq, void *dev_id,
-					struct pt_regs *regs)
+static irqreturn_t omap_mpu_timer_interrupt(int irq, void *dev_id)
 {
 	unsigned long now, latency;
 
···
 	now = 0 - omap_mpu_timer_read(0);
 	latency = MPU_TICKS_PER_SEC / HZ - omap_mpu_timer_read(1);
 	omap_mpu_timer_last = now - latency;
-	timer_tick(regs);
+	timer_tick();
 	write_sequnlock(&xtime_lock);
 
 	return IRQ_HANDLED;
···
 };
 
 static unsigned long omap_mpu_timer1_overflows;
-static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id,
-					     struct pt_regs *regs)
+static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
 {
 	omap_mpu_timer1_overflows++;
 	return IRQ_HANDLED;

arch/arm/mach-omap2/board-apollon.c

···
 	omap_set_gpio_dataout(LED2_GPIO15, 0);
 }
 
-static irqreturn_t apollon_sw_interrupt(int irq, void *ignored, struct pt_regs *regs)
+static irqreturn_t apollon_sw_interrupt(int irq, void *ignored)
 {
 	static unsigned int led0, led1, led2;
 

arch/arm/mach-omap2/timer-gp.c

···
 	omap_dm_timer_start(gptimer);
 }
 
-static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
-					    struct pt_regs *regs)
+static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
 	omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
-	timer_tick(regs);
+	timer_tick();
 
 	write_sequnlock(&xtime_lock);
 

arch/arm/mach-pnx4008/dma.c

···
 
 static struct dma_channel {
 	char *name;
-	void (*irq_handler) (int, int, void *, struct pt_regs *);
+	void (*irq_handler) (int, int, void *);
 	void *data;
 	struct pnx4008_dma_ll *ll;
 	u32 ll_dma;
···
 #define VALID_CHANNEL(c)	(((c) >= 0) && ((c) < MAX_DMA_CHANNELS))
 
 int pnx4008_request_channel(char *name, int ch,
-			    void (*irq_handler) (int, int, void *,
-						 struct pt_regs *), void *data)
+			    void (*irq_handler) (int, int, void *), void *data)
 {
 	int i, found = 0;
 
···
 
 EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enabled);
 
-static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 {
 	int i;
 	unsigned long dint = __raw_readl(DMAC_INT_STAT);
···
 					cause |= DMA_ERR_INT;
 				if (tcint & i_bit)
 					cause |= DMA_TC_INT;
-				channel->irq_handler(i, cause, channel->data,
-						     regs);
+				channel->irq_handler(i, cause, channel->data);
 			} else {
 				/*
 				 * IRQ for an unregistered DMA channel

arch/arm/mach-pnx4008/time.c

···
 /*!
  * IRQ handler for the timer
  */
-static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id,
-					   struct pt_regs *regs)
+static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id)
 {
 	if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
 
 		write_seqlock(&xtime_lock);
 
 		do {
-			timer_tick(regs);
+			timer_tick();
 
 			/*
 			 * this algorithm takes care of possible delay

arch/arm/mach-pxa/corgi.c

···
  */
 static struct pxamci_platform_data corgi_mci_platform_data;
 
-static int corgi_mci_init(struct device *dev, irqreturn_t (*corgi_detect_int)(int, void *, struct pt_regs *), void *data)
+static int corgi_mci_init(struct device *dev, irqreturn_t (*corgi_detect_int)(int, void *), void *data)
 {
 	int err;
 

arch/arm/mach-pxa/dma.c

···
 
 static struct dma_channel {
 	char *name;
-	void (*irq_handler)(int, void *, struct pt_regs *);
+	void (*irq_handler)(int, void *);
 	void *data;
 } dma_channels[PXA_DMA_CHANNELS];
 
 
 int pxa_request_dma (char *name, pxa_dma_prio prio,
-			 void (*irq_handler)(int, void *, struct pt_regs *),
+			 void (*irq_handler)(int, void *),
 		 	 void *data)
 {
 	unsigned long flags;
···
 	local_irq_restore(flags);
 }
 
-static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 {
 	int i, dint = DINT;
 
···
 		if (dint & (1 << i)) {
 			struct dma_channel *channel = &dma_channels[i];
 			if (channel->name && channel->irq_handler) {
-				channel->irq_handler(i, channel->data, regs);
+				channel->irq_handler(i, channel->data);
 			} else {
 				/*
 				 * IRQ for an unregistered DMA channel:

arch/arm/mach-pxa/idp.c

···
 	.pxafb_lcd_power = &idp_lcd_power
 };
 
-static int idp_mci_init(struct device *dev, irqreturn_t (*idp_detect_int)(int, void *, struct pt_regs *), void *data)
+static int idp_mci_init(struct device *dev, irqreturn_t (*idp_detect_int)(int, void *), void *data)
 {
 	/* setup GPIO for PXA25x MMC controller	*/
 	pxa_gpio_mode(GPIO6_MMCCLK_MD);

arch/arm/mach-pxa/irq.c

···
  * Demux handler for GPIO>=2 edge detect interrupts
  */
 
-static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc,
-				   struct pt_regs *regs)
+static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc)
 {
 	unsigned int mask;
 	int loop;
···
 			mask >>= 2;
 			do {
 				if (mask & 1)
-					desc_handle_irq(irq, desc, regs);
+					desc_handle_irq(irq, desc);
 				irq++;
 				desc++;
 				mask >>= 1;
···
 			desc = irq_desc + irq;
 			do {
 				if (mask & 1)
-					desc_handle_irq(irq, desc, regs);
+					desc_handle_irq(irq, desc);
 				irq++;
 				desc++;
 				mask >>= 1;
···
 			desc = irq_desc + irq;
 			do {
 				if (mask & 1)
-					desc_handle_irq(irq, desc, regs);
+					desc_handle_irq(irq, desc);
 				irq++;
 				desc++;
 				mask >>= 1;
···
 			desc = irq_desc + irq;
 			do {
 				if (mask & 1)
-					desc_handle_irq(irq, desc, regs);
+					desc_handle_irq(irq, desc);
 				irq++;
 				desc++;
 				mask >>= 1;

arch/arm/mach-pxa/lpd270.c

···
 	.unmask		= lpd270_unmask_irq,
 };
 
-static void lpd270_irq_handler(unsigned int irq, struct irqdesc *desc,
-				  struct pt_regs *regs)
+static void lpd270_irq_handler(unsigned int irq, struct irqdesc *desc)
 {
 	unsigned long pending;
 
···
 		if (likely(pending)) {
 			irq = LPD270_IRQ(0) + __ffs(pending);
 			desc = irq_desc + irq;
-			desc_handle_irq(irq, desc, regs);
+			desc_handle_irq(irq, desc);
 
 			pending = __raw_readw(LPD270_INT_STATUS) &
 						lpd270_irq_enabled;

arch/arm/mach-pxa/lubbock.c

···
 	.unmask		= lubbock_unmask_irq,
 };
 
-static void lubbock_irq_handler(unsigned int irq, struct irqdesc *desc,
-				struct pt_regs *regs)
+static void lubbock_irq_handler(unsigned int irq, struct irqdesc *desc)
 {
 	unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
 	do {
···
 		if (likely(pending)) {
 			irq = LUBBOCK_IRQ(0) + __ffs(pending);
 			desc = irq_desc + irq;
-			desc_handle_irq(irq, desc, regs);
+			desc_handle_irq(irq, desc);
 		}
 		pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
 	} while (pending);
···
 #define	MMC_POLL_RATE		msecs_to_jiffies(1000)
 
 static void lubbock_mmc_poll(unsigned long);
-static irqreturn_t (*mmc_detect_int)(int, void *, struct pt_regs *);
+static irqreturn_t (*mmc_detect_int)(int, void *);
 
 static struct timer_list mmc_timer = {
 	.function	= lubbock_mmc_poll,
···
 	}
 }
 
-static irqreturn_t lubbock_detect_int(int irq, void *data, struct pt_regs *regs)
+static irqreturn_t lubbock_detect_int(int irq, void *data)
 {
 	/* IRQ is level triggered; disable, and poll for removal */
 	disable_irq(irq);
 	mod_timer(&mmc_timer, jiffies + MMC_POLL_RATE);
 
-	return mmc_detect_int(irq, data, regs);
+	return mmc_detect_int(irq, data);
 }
 
 static int lubbock_mci_init(struct device *dev,
-		irqreturn_t (*detect_int)(int, void *, struct pt_regs *),
+		irqreturn_t (*detect_int)(int, void *),
 		void *data)
 {
 	/* setup GPIO for PXA25x MMC controller	*/

arch/arm/mach-pxa/mainstone.c

···
 	.unmask		= mainstone_unmask_irq,
 };
 
-static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc,
-				  struct pt_regs *regs)
+static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc)
 {
 	unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
 	do {
···
 		if (likely(pending)) {
 			irq = MAINSTONE_IRQ(0) + __ffs(pending);
 			desc = irq_desc + irq;
-			desc_handle_irq(irq, desc, regs);
+			desc_handle_irq(irq, desc);
 		}
 		pending = MST_INTSETCLR & mainstone_irq_enabled;
 	} while (pending);
···
 	.pxafb_backlight_power	= mainstone_backlight_power,
 };
 
-static int mainstone_mci_init(struct device *dev, irqreturn_t (*mstone_detect_int)(int, void *, struct pt_regs *), void *data)
+static int mainstone_mci_init(struct device *dev, irqreturn_t (*mstone_detect_int)(int, void *), void *data)
 {
 	int err;
 

arch/arm/mach-pxa/poodle.c

···
  */
 static struct pxamci_platform_data poodle_mci_platform_data;
 
-static int poodle_mci_init(struct device *dev, irqreturn_t (*poodle_detect_int)(int, void *, struct pt_regs *), void *data)
+static int poodle_mci_init(struct device *dev, irqreturn_t (*poodle_detect_int)(int, void *), void *data)
 {
 	int err;
 

arch/arm/mach-pxa/spitz.c

···
 
 static struct pxamci_platform_data spitz_mci_platform_data;
 
-static int spitz_mci_init(struct device *dev, irqreturn_t (*spitz_detect_int)(int, void *, struct pt_regs *), void *data)
+static int spitz_mci_init(struct device *dev, irqreturn_t (*spitz_detect_int)(int, void *), void *data)
 {
 	int err;
 

arch/arm/mach-pxa/ssp.c

···
 static DEFINE_MUTEX(mutex);
 static int use_count[PXA_SSP_PORTS] = {0, 0, 0};
 
-static irqreturn_t ssp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t ssp_interrupt(int irq, void *dev_id)
 {
 	struct ssp_dev *dev = (struct ssp_dev*) dev_id;
 	unsigned int status = SSSR_P(dev->port);

arch/arm/mach-pxa/time.c

···
 #endif
 
 static irqreturn_t
-pxa_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+pxa_timer_interrupt(int irq, void *dev_id)
 {
 	int next_match;
 
···
 	 * exactly one tick period which should be a pretty rare event.
 	 */
 	do {
-		timer_tick(regs);
+		timer_tick();
 		OSSR = OSSR_M0;  /* Clear match on timer 0 */
 		next_match = (OSMR0 += LATCH);
 	} while( (signed long)(next_match - OSCR) <= 8 );
···
 }
 
 static irqreturn_t
-pxa_dyn_tick_handler(int irq, void *dev_id, struct pt_regs *regs)
+pxa_dyn_tick_handler(int irq, void *dev_id)
 {
 	if (match_posponed) {
 		match_posponed = 0;
 		OSMR0 = initial_match;
 		if ( (signed long)(initial_match - OSCR) <= 8 )
-			return pxa_timer_interrupt(irq, dev_id, regs);
+			return pxa_timer_interrupt(irq, dev_id);
 	}
 	return IRQ_NONE;
 }

arch/arm/mach-pxa/tosa.c

···
  */
 static struct pxamci_platform_data tosa_mci_platform_data;
 
-static int tosa_mci_init(struct device *dev, irqreturn_t (*tosa_detect_int)(int, void *, struct pt_regs *), void *data)
+static int tosa_mci_init(struct device *dev, irqreturn_t (*tosa_detect_int)(int, void *), void *data)
 {
 	int err;
 

arch/arm/mach-pxa/trizeps4.c

···
 #endif		/* CONFIG_MACH_TRIZEPS4_CONXS */
 EXPORT_SYMBOL(board_pcmcia_power);
 
-static int trizeps4_mci_init(struct device *dev, irqreturn_t (*mci_detect_int)(int, void *, struct pt_regs *), void *data)
+static int trizeps4_mci_init(struct device *dev, irqreturn_t (*mci_detect_int)(int, void *), void *data)
 {
 	int err;
 	/* setup GPIO for PXA27x MMC controller */

arch/arm/mach-realview/core.c

···
 /*
  * IRQ handler for the timer
  */
-static irqreturn_t realview_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
 	// ...clear the interrupt
 	writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 
-	timer_tick(regs);
+	timer_tick();
 
 #if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS)
 	smp_send_timer();
-	update_process_times(user_mode(regs));
+	update_process_times(user_mode(get_irq_regs()));
 #endif
 
 	write_sequnlock(&xtime_lock);

arch/arm/mach-rpc/dma.c

···
 	sg->length |= flags;
 }
 
-static irqreturn_t iomd_dma_handle(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t iomd_dma_handle(int irq, void *dev_id)
 {
 	dma_t *dma = (dma_t *)dev_id;
 	unsigned long base = dma->dma_base;

arch/arm/mach-s3c2410/bast-irq.c

···
 
 static void
 bast_irq_pc104_demux(unsigned int irq,
-		     struct irqdesc *desc,
-		     struct pt_regs *regs)
+		     struct irqdesc *desc)
 {
 	unsigned int stat;
 	unsigned int irqno;
···
 			if (stat & 1) {
 				irqno = bast_pc104_irqs[i];
 				desc = irq_desc + irqno;
-				desc_handle_irq(irqno, desc, regs);
+				desc_handle_irq(irqno, desc);
 			}
 		}
 	}

arch/arm/mach-s3c2410/dma.c

···
 #define dmadbg2(x...)
 
 static irqreturn_t
-s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs)
+s3c2410_dma_irq(int irq, void *devpw)
 {
 	struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
 	struct s3c2410_dma_buf  *buf;

arch/arm/mach-s3c2410/irq.c

···
 
 /* irq demux for adc */
 static void s3c_irq_demux_adc(unsigned int irq,
-			      struct irqdesc *desc,
-			      struct pt_regs *regs)
+			      struct irqdesc *desc)
 {
 	unsigned int subsrc, submsk;
 	unsigned int offset = 9;
···
 	if (subsrc != 0) {
 		if (subsrc & 1) {
 			mydesc = irq_desc + IRQ_TC;
-			desc_handle_irq(IRQ_TC, mydesc, regs);
+			desc_handle_irq(IRQ_TC, mydesc);
 		}
 		if (subsrc & 2) {
 			mydesc = irq_desc + IRQ_ADC;
-			desc_handle_irq(IRQ_ADC, mydesc, regs);
+			desc_handle_irq(IRQ_ADC, mydesc);
 		}
 	}
 }
 
-static void s3c_irq_demux_uart(unsigned int start,
-			       struct pt_regs *regs)
+static void s3c_irq_demux_uart(unsigned int start)
 {
 	unsigned int subsrc, submsk;
 	unsigned int offset = start - IRQ_S3CUART_RX0;
···
 		desc = irq_desc + start;
 
 		if (subsrc & 1)
-			desc_handle_irq(start, desc, regs);
+			desc_handle_irq(start, desc);
 
 		desc++;
 
 		if (subsrc & 2)
-			desc_handle_irq(start+1, desc, regs);
+			desc_handle_irq(start+1, desc);
 
 		desc++;
 
 		if (subsrc & 4)
-			desc_handle_irq(start+2, desc, regs);
+			desc_handle_irq(start+2, desc);
 	}
 }
 
···
 
 static void
 s3c_irq_demux_uart0(unsigned int irq,
-		    struct irqdesc *desc,
-		    struct pt_regs *regs)
+		    struct irqdesc *desc)
 {
 	irq = irq;
-	s3c_irq_demux_uart(IRQ_S3CUART_RX0, regs);
+	s3c_irq_demux_uart(IRQ_S3CUART_RX0);
 }
 
 static void
 s3c_irq_demux_uart1(unsigned int irq,
-		    struct irqdesc *desc,
-		    struct pt_regs *regs)
+		    struct irqdesc *desc)
 {
 	irq = irq;
-	s3c_irq_demux_uart(IRQ_S3CUART_RX1, regs);
+	s3c_irq_demux_uart(IRQ_S3CUART_RX1);
 }
 
 static void
 s3c_irq_demux_uart2(unsigned int irq,
-		    struct irqdesc *desc,
-		    struct pt_regs *regs)
+		    struct irqdesc *desc)
 {
 	irq = irq;
-	s3c_irq_demux_uart(IRQ_S3CUART_RX2, regs);
+	s3c_irq_demux_uart(IRQ_S3CUART_RX2);
 }
 
 static void
 s3c_irq_demux_extint8(unsigned int irq,
-		      struct irqdesc *desc,
-		      struct pt_regs *regs)
+		      struct irqdesc *desc)
 {
 	unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
 	unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
···
 		eintpnd &= ~(1<<irq);
 
 		irq += (IRQ_EINT4 - 4);
-		desc_handle_irq(irq, irq_desc + irq, regs);
+		desc_handle_irq(irq, irq_desc + irq);
 	}
 
 }
 
 static void
 s3c_irq_demux_extint4t7(unsigned int irq,
-			struct irqdesc *desc,
-			struct pt_regs *regs)
+			struct irqdesc *desc)
 {
 	unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
 	unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
···
 
 		irq += (IRQ_EINT4 - 4);
 
-		desc_handle_irq(irq, irq_desc + irq, regs);
+		desc_handle_irq(irq, irq_desc + irq);
 	}
 }
 

arch/arm/mach-s3c2410/mach-amlm5900.c

···
 #endif
 
 static irqreturn_t
-amlm5900_wake_interrupt(int irq, void *ignored, struct pt_regs *regs)
+amlm5900_wake_interrupt(int irq, void *ignored)
 {
 	return IRQ_HANDLED;
 }

arch/arm/mach-s3c2410/s3c2440-irq.c

···
 /* WDT/AC97 */
 
 static void s3c_irq_demux_wdtac97(unsigned int irq,
-				  struct irqdesc *desc,
-				  struct pt_regs *regs)
+				  struct irqdesc *desc)
 {
 	unsigned int subsrc, submsk;
 	struct irqdesc *mydesc;
···
 	if (subsrc != 0) {
 		if (subsrc & 1) {
 			mydesc = irq_desc + IRQ_S3C2440_WDT;
-			desc_handle_irq(IRQ_S3C2440_WDT, mydesc, regs);
+			desc_handle_irq(IRQ_S3C2440_WDT, mydesc);
 		}
 		if (subsrc & 2) {
 			mydesc = irq_desc + IRQ_S3C2440_AC97;
-			desc_handle_irq(IRQ_S3C2440_AC97, mydesc, regs);
+			desc_handle_irq(IRQ_S3C2440_AC97, mydesc);
 		}
 	}
 }

arch/arm/mach-s3c2410/s3c244x-irq.c

···
 /* camera irq */
 
 static void s3c_irq_demux_cam(unsigned int irq,
-			      struct irqdesc *desc,
-			      struct pt_regs *regs)
+			      struct irqdesc *desc)
 {
 	unsigned int subsrc, submsk;
 	struct irqdesc *mydesc;
···
 	if (subsrc != 0) {
 		if (subsrc & 1) {
 			mydesc = irq_desc + IRQ_S3C2440_CAM_C;
-			desc_handle_irq(IRQ_S3C2440_CAM_C, mydesc, regs);
+			desc_handle_irq(IRQ_S3C2440_CAM_C, mydesc);
 		}
 		if (subsrc & 2) {
 			mydesc = irq_desc + IRQ_S3C2440_CAM_P;
-			desc_handle_irq(IRQ_S3C2440_CAM_P, mydesc, regs);
+			desc_handle_irq(IRQ_S3C2440_CAM_P, mydesc);
 		}
 	}
 }

arch/arm/mach-s3c2410/time.c

···
  * IRQ handler for the timer
  */
 static irqreturn_t
-s3c2410_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+s3c2410_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
-	timer_tick(regs);
+	timer_tick();
 	write_sequnlock(&xtime_lock);
 	return IRQ_HANDLED;
 }

arch/arm/mach-s3c2410/usb-simtec.c

···
 }
 
 static irqreturn_t
-usb_simtec_ocirq(int irq, void *pw, struct pt_regs *regs)
+usb_simtec_ocirq(int irq, void *pw)
 {
 	struct s3c2410_hcd_info *info = (struct s3c2410_hcd_info *)pw;
 

arch/arm/mach-sa1100/dma.c

···
 static spinlock_t dma_list_lock;
 
 
-static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 {
 	dma_regs_t *dma_regs = dev_id;
 	sa1100_dma_t *dma = dma_chan + (((u_int)dma_regs >> 5) & 7);

arch/arm/mach-sa1100/h3600.c

···
 	GPIO2_SD_CON_SLT,
 };
 
-static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc)
 {
 	int i;
 
···
 		if (0) printk("%s KPIO 0x%08X\n", __FUNCTION__, irq);
 		for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++)
 			if (irq & kpio_irq_mask[j])
-				do_edge_IRQ(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j, regs);
+				do_edge_IRQ(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j);
 
 		/* GPIO2 */
 		irq = H3800_ASIC2_GPIINTFLAG;
 		if (0) printk("%s GPIO 0x%08X\n", __FUNCTION__, irq);
 		for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++)
 			if (irq & gpio_irq_mask[j])
-				do_edge_IRQ(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j , regs);
+				do_edge_IRQ(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j);
 	}
 
 	if (i >= MAX_ASIC_ISR_LOOPS)

arch/arm/mach-sa1100/irq.c

···
  * and call the handler.
  */
 static void
-sa1100_high_gpio_handler(unsigned int irq, struct irqdesc *desc,
-			 struct pt_regs *regs)
+sa1100_high_gpio_handler(unsigned int irq, struct irqdesc *desc)
 {
 	unsigned int mask;
 
···
 		mask >>= 11;
 		do {
 			if (mask & 1)
-				desc_handle_irq(irq, desc, regs);
+				desc_handle_irq(irq, desc);
 			mask >>= 1;
 			irq++;
 			desc++;

arch/arm/mach-sa1100/neponset.c

···
  * is rather unfortunate.
  */
 static void
-neponset_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+neponset_irq_handler(unsigned int irq, struct irqdesc *desc)
 {
 	unsigned int irr;
 
···
 
 			if (irr & IRR_ETHERNET) {
 				d = irq_desc + IRQ_NEPONSET_SMC9196;
-				desc_handle_irq(IRQ_NEPONSET_SMC9196, d, regs);
+				desc_handle_irq(IRQ_NEPONSET_SMC9196, d);
 			}
 
 			if (irr & IRR_USAR) {
 				d = irq_desc + IRQ_NEPONSET_USAR;
-				desc_handle_irq(IRQ_NEPONSET_USAR, d, regs);
+				desc_handle_irq(IRQ_NEPONSET_USAR, d);
 			}
 
 			desc->chip->unmask(irq);
···
 
 		if (irr & IRR_SA1111) {
 			d = irq_desc + IRQ_NEPONSET_SA1111;
-			desc_handle_irq(IRQ_NEPONSET_SA1111, d, regs);
+			desc_handle_irq(IRQ_NEPONSET_SA1111, d);
 		}
 	}
 }

arch/arm/mach-sa1100/ssp.c

···
 
 #define TIMEOUT 100000
 
-static irqreturn_t ssp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t ssp_interrupt(int irq, void *dev_id)
 {
 	unsigned int status = Ser4SSSR;
 

arch/arm/mach-sa1100/time.c

···
 #endif
 
 static irqreturn_t
-sa1100_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+sa1100_timer_interrupt(int irq, void *dev_id)
 {
 	unsigned int next_match;
 
···
 	 * handlers.
 	 */
 	do {
-		timer_tick(regs);
+		timer_tick();
 		OSSR = OSSR_M0;  /* Clear match on timer 0 */
 		next_match = (OSMR0 += LATCH);
 	} while ((signed long)(next_match - OSCR) <= 0);
···
 }
 
 static irqreturn_t
-sa1100_dyn_tick_handler(int irq, void *dev_id, struct pt_regs *regs)
+sa1100_dyn_tick_handler(int irq, void *dev_id)
 {
 	if (match_posponed) {
 		match_posponed = 0;
 		OSMR0 = initial_match;
 		if ((signed long)(initial_match - OSCR) <= 0)
-			return sa1100_timer_interrupt(irq, dev_id, regs);
+			return sa1100_timer_interrupt(irq, dev_id);
 	}
 	return IRQ_NONE;
 }

arch/arm/mach-shark/core.c

···
 #define HZ_TIME ((1193180 + HZ/2) / HZ)
 
 static irqreturn_t
-shark_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+shark_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
-	timer_tick(regs);
+	timer_tick();
 	write_sequnlock(&xtime_lock);
 	return IRQ_HANDLED;
 }

arch/arm/mach-shark/irq.c

···
 
 static void shark_ack_8259A_irq(unsigned int irq){}
 
-static irqreturn_t bogus_int(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t bogus_int(int irq, void *dev_id)
 {
 	printk("Got interrupt %i!\n",irq);
 	return IRQ_NONE;

arch/arm/mach-versatile/core.c

···
 };
 
 static void
-sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+sic_handle_irq(unsigned int irq, struct irqdesc *desc)
 {
 	unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
 
 	if (status == 0) {
-		do_bad_IRQ(irq, desc, regs);
+		do_bad_IRQ(irq, desc);
 		return;
 	}
 
···
 		irq += IRQ_SIC_START;
 
 		desc = irq_desc + irq;
-		desc_handle_irq(irq, desc, regs);
+		desc_handle_irq(irq, desc);
 	} while (status);
 }
 
···
 /*
  * IRQ handler for the timer
  */
-static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
 	// ...clear the interrupt
 	writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 
-	timer_tick(regs);
+	timer_tick();
 
 	write_sequnlock(&xtime_lock);
 

arch/arm/oprofile/op_model_xscale.c

···
 	__asm__ __volatile__ ("mcr p14, 0, %0, c5, c1, 0" : : "r" (flag));
 }
 
-static irqreturn_t xscale_pmu_interrupt(int irq, void *arg, struct pt_regs *regs)
+static irqreturn_t xscale_pmu_interrupt(int irq, void *arg)
 {
 	int i;
 	u32 pmnc;
···
 			continue;
 
 		write_counter(i, -(u32)results[i].reset_counter);
-		oprofile_add_sample(regs, i);
+		oprofile_add_sample(get_irq_regs(), i);
 		results[i].ovf--;
 	}
 

arch/arm/plat-iop/time.c

···
 }
 
 static irqreturn_t
-iop3xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+iop3xx_timer_interrupt(int irq, void *dev_id)
 {
 	write_seqlock(&xtime_lock);
 
···
 
 	while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1)
 							>= ticks_per_jiffy) {
-		timer_tick(regs);
+		timer_tick();
 		next_jiffy_time -= ticks_per_jiffy;
 	}
 

arch/arm/plat-omap/dma.c

···
 	return 1;
 }
 
-static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id,
-					 struct pt_regs *regs)
+static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
 {
 	int ch = ((int) dev_id) - 1;
 	int handled = 0;
···
 }
 
 /* STATUS register count is from 1-32 while our is 0-31 */
-static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id,
-					 struct pt_regs *regs)
+static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
 {
 	u32 val;
 	int i;
···
 	omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
 }
 
-static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id,
-				       struct pt_regs *regs)
+static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
 {
 	u16 w;
 

arch/arm/plat-omap/gpio.c

···
  * line's interrupt handler has been run, we may miss some nested
  * interrupts.
  */
-static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
-			     struct pt_regs *regs)
+static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc)
 {
 	void __iomem *isr_reg = NULL;
 	u32 isr;
···
 				continue;
 			}
 
-			desc_handle_irq(gpio_irq, d, regs);
+			desc_handle_irq(gpio_irq, d);
 
 			if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
 				irq_mask = 1 <<

arch/arm/plat-omap/mcbsp.c

···
 	DBG("***********************\n");
 }
 
-static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 {
 	struct omap_mcbsp * mcbsp_tx = (struct omap_mcbsp *)(dev_id);
 
···
 	return IRQ_HANDLED;
 }
 
-static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 {
 	struct omap_mcbsp * mcbsp_rx = (struct omap_mcbsp *)(dev_id);
 

arch/arm/plat-omap/timer32k.c

···
  * issues with dynamic tick. In the dynamic tick case, we need to lock
  * with irqsave.
  */
-static inline irqreturn_t _omap_32k_timer_interrupt(int irq, void *dev_id,
-					struct pt_regs *regs)
+static inline irqreturn_t _omap_32k_timer_interrupt(int irq, void *dev_id)
 {
 	unsigned long now;
 
···
 	while ((signed long)(now - omap_32k_last_tick)
 						>= OMAP_32K_TICKS_PER_HZ) {
 		omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
-		timer_tick(regs);
+		timer_tick();
 	}
 
 	/* Restart timer so we don't drift off due to modulo or dynamic tick.
···
 	return IRQ_HANDLED;
 }
 
-static irqreturn_t omap_32k_timer_handler(int irq, void *dev_id,
-					struct pt_regs *regs)
+static irqreturn_t omap_32k_timer_handler(int irq, void *dev_id)
 {
-	return _omap_32k_timer_interrupt(irq, dev_id, regs);
+	return _omap_32k_timer_interrupt(irq, dev_id);
 }
 
-static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
-					    struct pt_regs *regs)
+static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
 {
 	unsigned long flags;
 
 	write_seqlock_irqsave(&xtime_lock, flags);
-	_omap_32k_timer_interrupt(irq, dev_id, regs);
+	_omap_32k_timer_interrupt(irq, dev_id);
 	write_sequnlock_irqrestore(&xtime_lock, flags);
 
 	return IRQ_HANDLED;

include/asm-arm/arch-clps711x/time.h

···
  * IRQ handler for the timer
  */
 static irqreturn_t
-p720t_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+p720t_timer_interrupt(int irq, void *dev_id)
 {
+	struct pt_regs *regs = get_irq_regs();
 	do_leds();
 	do_timer(1);
 #ifndef CONFIG_SMP

include/asm-arm/arch-imx/imx-dma.h

···
 
 struct imx_dma_channel {
 	const char *name;
-	void (*irq_handler) (int, void *, struct pt_regs *);
-	void (*err_handler) (int, void *, struct pt_regs *, int errcode);
+	void (*irq_handler) (int, void *);
+	void (*err_handler) (int, void *, int errcode);
 	void *data;
 	dmamode_t  dma_mode;
 	struct scatterlist *sg;
···
 
 int
 imx_dma_setup_handlers(imx_dmach_t dma_ch,
-		void (*irq_handler) (int, void *, struct pt_regs *),
-		void (*err_handler) (int, void *, struct pt_regs *, int), void *data);
+		void (*irq_handler) (int, void *),
+		void (*err_handler) (int, void *, int), void *data);
 
 void imx_dma_enable(imx_dmach_t dma_ch);
 

include/asm-arm/arch-l7200/time.h

···
  * Handler for RTC timer interrupt
  */
 static irqreturn_t
-timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+timer_interrupt(int irq, void *dev_id)
 {
+	struct pt_regs *regs = get_irq_regs();
 	do_timer(1);
 #ifndef CONFIG_SMP
 	update_process_times(user_mode(regs));

include/asm-arm/arch-pnx4008/dma.h

···
 extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
 
 extern int pnx4008_request_channel(char *, int,
-				   void (*)(int, int, void *, struct pt_regs *),
+				   void (*)(int, int, void *),
 				   void *);
 extern void pnx4008_free_channel(int);
 extern int pnx4008_config_dma(int, int, int);

include/asm-arm/arch-pxa/dma.h

···
 
 int pxa_request_dma (char *name,
 			 pxa_dma_prio prio,
-			 void (*irq_handler)(int, void *, struct pt_regs *),
+			 void (*irq_handler)(int, void *),
 			 void *data);
 
 void pxa_free_dma (int dma_ch);

include/asm-arm/arch-pxa/mmc.h

···
 struct pxamci_platform_data {
 	unsigned int ocr_mask;			/* available voltages */
 	unsigned long detect_delay;		/* delay in jiffies before detecting cards after interrupt */
-	int (*init)(struct device *, irqreturn_t (*)(int, void *, struct pt_regs *), void *);
+	int (*init)(struct device *, irqreturn_t (*)(int, void *), void *);
 	int (*get_ro)(struct device *);
 	void (*setpower)(struct device *, unsigned int);
 	void (*exit)(struct device *, void *);

include/asm-arm/hardware/sharpsl_pm.h

···
 
 void sharpsl_battery_kick(void);
 void sharpsl_pm_led(int val);
-irqreturn_t sharpsl_ac_isr(int irq, void *dev_id, struct pt_regs *fp);
-irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id, struct pt_regs *fp);
-irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id, struct pt_regs *fp);
+irqreturn_t sharpsl_ac_isr(int irq, void *dev_id);
+irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id);
+irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id);
 

include/asm-arm/irq_regs.h

···
+#include <asm-generic/irq_regs.h>

include/asm-arm/mach/irq.h

···
 /*
  * Obsolete inline function for calling irq descriptor handlers.
  */
-static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc,
-				   struct pt_regs *regs)
+static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc)
 {
-	desc->handle_irq(irq, desc, regs);
+	desc->handle_irq(irq, desc);
 }
 
 void set_irq_flags(unsigned int irq, unsigned int flags);
···
 #define irqdesc		irq_desc
 #define irqchip		irq_chip
 
-#define do_bad_IRQ(irq,desc,regs)			\
+#define do_bad_IRQ(irq,desc)				\
 do {							\
 	spin_lock(&desc->lock);				\
-	handle_bad_irq(irq, desc, regs);		\
+	handle_bad_irq(irq, desc);			\
 	spin_unlock(&desc->lock);			\
 } while(0)
 

include/asm-arm/mach/time.h

···
 	int		(*enable)(void);	/* Enables dynamic tick */
 	int		(*disable)(void);	/* Disables dynamic tick */
 	void		(*reprogram)(unsigned long); /* Reprograms the timer */
-	int		(*handler)(int, void *, struct pt_regs *);
+	int		(*handler)(int, void *);
 };
 
 void timer_dyn_reprogram(void);
···
 #endif
 
 extern struct sys_timer *system_timer;
-extern void timer_tick(struct pt_regs *);
+extern void timer_tick(void);
 
 /*
  * Kernel time keeping support.