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MIPS: CMP: Fix physical core number calculation logic

The CPUNum Field in EBase register is 10bit wide, so after 1 bit right
shift, the mask value should be 0x1ff.

Signed-off-by: jerin jacob <jerinjacobk@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4420/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

jerin jacob and committed by
Ralf Baechle 0cc40dac a1226540

+1 -1
+1 -1
arch/mips/kernel/smp-cmp.c
··· 97 97 98 98 /* Enable per-cpu interrupts: platform specific */ 99 99 100 - c->core = (read_c0_ebase() >> 1) & 0xff; 100 + c->core = (read_c0_ebase() >> 1) & 0x1ff; 101 101 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) 102 102 c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE; 103 103 #endif