tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: qcom: camcc-sdm845: convert to parent_hws/_data

Convert the clock driver to specify parent hws/data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-11-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson 0cc3bd80 b4e2d27e

+158 -142
+158 -142
drivers/clk/qcom/camcc-sdm845.c
··· 31 31 .clkr = { 32 32 .hw.init = &(struct clk_init_data){ 33 33 .name = "cam_cc_pll0", 34 - .parent_names = (const char *[]){ "bi_tcxo" }, 34 + .parent_data = &(const struct clk_parent_data){ 35 + .fw_name = "bi_tcxo", .name = "bi_tcxo", 36 + }, 35 37 .num_parents = 1, 36 38 .ops = &clk_alpha_pll_fabia_ops, 37 39 }, ··· 55 53 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 56 54 .clkr.hw.init = &(struct clk_init_data){ 57 55 .name = "cam_cc_pll0_out_even", 58 - .parent_names = (const char *[]){ "cam_cc_pll0" }, 56 + .parent_hws = (const struct clk_hw*[]){ 57 + &cam_cc_pll0.clkr.hw, 58 + }, 59 59 .num_parents = 1, 60 60 .ops = &clk_alpha_pll_postdiv_fabia_ops, 61 61 }, ··· 69 65 .clkr = { 70 66 .hw.init = &(struct clk_init_data){ 71 67 .name = "cam_cc_pll1", 72 - .parent_names = (const char *[]){ "bi_tcxo" }, 68 + .parent_data = &(const struct clk_parent_data){ 69 + .fw_name = "bi_tcxo", .name = "bi_tcxo", 70 + }, 73 71 .num_parents = 1, 74 72 .ops = &clk_alpha_pll_fabia_ops, 75 73 }, ··· 87 81 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 88 82 .clkr.hw.init = &(struct clk_init_data){ 89 83 .name = "cam_cc_pll1_out_even", 90 - .parent_names = (const char *[]){ "cam_cc_pll1" }, 84 + .parent_hws = (const struct clk_hw*[]){ 85 + &cam_cc_pll1.clkr.hw, 86 + }, 91 87 .num_parents = 1, 92 88 .ops = &clk_alpha_pll_postdiv_fabia_ops, 93 89 }, ··· 101 93 .clkr = { 102 94 .hw.init = &(struct clk_init_data){ 103 95 .name = "cam_cc_pll2", 104 - .parent_names = (const char *[]){ "bi_tcxo" }, 96 + .parent_data = &(const struct clk_parent_data){ 97 + .fw_name = "bi_tcxo", .name = "bi_tcxo", 98 + }, 105 99 .num_parents = 1, 106 100 .ops = &clk_alpha_pll_fabia_ops, 107 101 }, ··· 119 109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 120 110 .clkr.hw.init = &(struct clk_init_data){ 121 111 .name = "cam_cc_pll2_out_even", 122 - .parent_names = (const char *[]){ "cam_cc_pll2" }, 112 + .parent_hws = (const struct clk_hw*[]){ 113 + &cam_cc_pll2.clkr.hw, 114 + }, 123 115 .num_parents = 1, 124 116 .ops = &clk_alpha_pll_postdiv_fabia_ops, 125 117 }, ··· 133 121 .clkr = { 134 122 .hw.init = &(struct clk_init_data){ 135 123 .name = "cam_cc_pll3", 136 - .parent_names = (const char *[]){ "bi_tcxo" }, 124 + .parent_data = &(const struct clk_parent_data){ 125 + .fw_name = "bi_tcxo", .name = "bi_tcxo", 126 + }, 137 127 .num_parents = 1, 138 128 .ops = &clk_alpha_pll_fabia_ops, 139 129 }, ··· 151 137 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 152 138 .clkr.hw.init = &(struct clk_init_data){ 153 139 .name = "cam_cc_pll3_out_even", 154 - .parent_names = (const char *[]){ "cam_cc_pll3" }, 140 + .parent_hws = (const struct clk_hw*[]){ 141 + &cam_cc_pll3.clkr.hw, 142 + }, 155 143 .num_parents = 1, 156 144 .ops = &clk_alpha_pll_postdiv_fabia_ops, 157 145 }, ··· 167 151 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 168 152 }; 169 153 170 - static const char * const cam_cc_parent_names_0[] = { 171 - "bi_tcxo", 172 - "cam_cc_pll2_out_even", 173 - "cam_cc_pll1_out_even", 174 - "cam_cc_pll3_out_even", 175 - "cam_cc_pll0_out_even", 154 + static const struct clk_parent_data cam_cc_parent_data_0[] = { 155 + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 156 + { .hw = &cam_cc_pll2_out_even.clkr.hw }, 157 + { .hw = &cam_cc_pll1_out_even.clkr.hw }, 158 + { .hw = &cam_cc_pll3_out_even.clkr.hw }, 159 + { .hw = &cam_cc_pll0_out_even.clkr.hw }, 176 160 }; 177 161 178 162 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { ··· 202 186 .freq_tbl = ftbl_cam_cc_bps_clk_src, 203 187 .clkr.hw.init = &(struct clk_init_data){ 204 188 .name = "cam_cc_bps_clk_src", 205 - .parent_names = cam_cc_parent_names_0, 206 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 189 + .parent_data = cam_cc_parent_data_0, 190 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 207 191 .flags = CLK_SET_RATE_PARENT, 208 192 .ops = &clk_rcg2_shared_ops, 209 193 }, ··· 225 209 .freq_tbl = ftbl_cam_cc_cci_clk_src, 226 210 .clkr.hw.init = &(struct clk_init_data){ 227 211 .name = "cam_cc_cci_clk_src", 228 - .parent_names = cam_cc_parent_names_0, 229 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 212 + .parent_data = cam_cc_parent_data_0, 213 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 230 214 .ops = &clk_rcg2_ops, 231 215 }, 232 216 }; ··· 245 229 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 246 230 .clkr.hw.init = &(struct clk_init_data){ 247 231 .name = "cam_cc_cphy_rx_clk_src", 248 - .parent_names = cam_cc_parent_names_0, 249 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 232 + .parent_data = cam_cc_parent_data_0, 233 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 250 234 .ops = &clk_rcg2_ops, 251 235 }, 252 236 }; ··· 266 250 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 267 251 .clkr.hw.init = &(struct clk_init_data){ 268 252 .name = "cam_cc_csi0phytimer_clk_src", 269 - .parent_names = cam_cc_parent_names_0, 270 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 253 + .parent_data = cam_cc_parent_data_0, 254 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 271 255 .flags = CLK_SET_RATE_PARENT, 272 256 .ops = &clk_rcg2_ops, 273 257 }, ··· 281 265 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 282 266 .clkr.hw.init = &(struct clk_init_data){ 283 267 .name = "cam_cc_csi1phytimer_clk_src", 284 - .parent_names = cam_cc_parent_names_0, 285 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 268 + .parent_data = cam_cc_parent_data_0, 269 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 286 270 .flags = CLK_SET_RATE_PARENT, 287 271 .ops = &clk_rcg2_ops, 288 272 }, ··· 296 280 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 297 281 .clkr.hw.init = &(struct clk_init_data){ 298 282 .name = "cam_cc_csi2phytimer_clk_src", 299 - .parent_names = cam_cc_parent_names_0, 300 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 283 + .parent_data = cam_cc_parent_data_0, 284 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 301 285 .flags = CLK_SET_RATE_PARENT, 302 286 .ops = &clk_rcg2_ops, 303 287 }, ··· 311 295 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 312 296 .clkr.hw.init = &(struct clk_init_data){ 313 297 .name = "cam_cc_csi3phytimer_clk_src", 314 - .parent_names = cam_cc_parent_names_0, 315 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 298 + .parent_data = cam_cc_parent_data_0, 299 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 316 300 .flags = CLK_SET_RATE_PARENT, 317 301 .ops = &clk_rcg2_ops, 318 302 }, ··· 336 320 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 337 321 .clkr.hw.init = &(struct clk_init_data){ 338 322 .name = "cam_cc_fast_ahb_clk_src", 339 - .parent_names = cam_cc_parent_names_0, 340 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 323 + .parent_data = cam_cc_parent_data_0, 324 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 341 325 .ops = &clk_rcg2_ops, 342 326 }, 343 327 }; ··· 359 343 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 360 344 .clkr.hw.init = &(struct clk_init_data){ 361 345 .name = "cam_cc_fd_core_clk_src", 362 - .parent_names = cam_cc_parent_names_0, 363 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 346 + .parent_data = cam_cc_parent_data_0, 347 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 364 348 .ops = &clk_rcg2_shared_ops, 365 349 }, 366 350 }; ··· 382 366 .freq_tbl = ftbl_cam_cc_icp_clk_src, 383 367 .clkr.hw.init = &(struct clk_init_data){ 384 368 .name = "cam_cc_icp_clk_src", 385 - .parent_names = cam_cc_parent_names_0, 386 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 369 + .parent_data = cam_cc_parent_data_0, 370 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 387 371 .ops = &clk_rcg2_shared_ops, 388 372 }, 389 373 }; ··· 406 390 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 407 391 .clkr.hw.init = &(struct clk_init_data){ 408 392 .name = "cam_cc_ife_0_clk_src", 409 - .parent_names = cam_cc_parent_names_0, 410 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 393 + .parent_data = cam_cc_parent_data_0, 394 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 411 395 .flags = CLK_SET_RATE_PARENT, 412 396 .ops = &clk_rcg2_shared_ops, 413 397 }, ··· 429 413 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 430 414 .clkr.hw.init = &(struct clk_init_data){ 431 415 .name = "cam_cc_ife_0_csid_clk_src", 432 - .parent_names = cam_cc_parent_names_0, 433 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 416 + .parent_data = cam_cc_parent_data_0, 417 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 434 418 .ops = &clk_rcg2_shared_ops, 435 419 }, 436 420 }; ··· 443 427 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 444 428 .clkr.hw.init = &(struct clk_init_data){ 445 429 .name = "cam_cc_ife_1_clk_src", 446 - .parent_names = cam_cc_parent_names_0, 447 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 430 + .parent_data = cam_cc_parent_data_0, 431 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 448 432 .flags = CLK_SET_RATE_PARENT, 449 433 .ops = &clk_rcg2_shared_ops, 450 434 }, ··· 458 442 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 459 443 .clkr.hw.init = &(struct clk_init_data){ 460 444 .name = "cam_cc_ife_1_csid_clk_src", 461 - .parent_names = cam_cc_parent_names_0, 462 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 445 + .parent_data = cam_cc_parent_data_0, 446 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 463 447 .ops = &clk_rcg2_shared_ops, 464 448 }, 465 449 }; ··· 472 456 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 473 457 .clkr.hw.init = &(struct clk_init_data){ 474 458 .name = "cam_cc_ife_lite_clk_src", 475 - .parent_names = cam_cc_parent_names_0, 476 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 459 + .parent_data = cam_cc_parent_data_0, 460 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 477 461 .flags = CLK_SET_RATE_PARENT, 478 462 .ops = &clk_rcg2_shared_ops, 479 463 }, ··· 487 471 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 488 472 .clkr.hw.init = &(struct clk_init_data){ 489 473 .name = "cam_cc_ife_lite_csid_clk_src", 490 - .parent_names = cam_cc_parent_names_0, 491 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 474 + .parent_data = cam_cc_parent_data_0, 475 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 492 476 .ops = &clk_rcg2_shared_ops, 493 477 }, 494 478 }; ··· 512 496 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 513 497 .clkr.hw.init = &(struct clk_init_data){ 514 498 .name = "cam_cc_ipe_0_clk_src", 515 - .parent_names = cam_cc_parent_names_0, 516 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 499 + .parent_data = cam_cc_parent_data_0, 500 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 517 501 .flags = CLK_SET_RATE_PARENT, 518 502 .ops = &clk_rcg2_shared_ops, 519 503 }, ··· 527 511 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 528 512 .clkr.hw.init = &(struct clk_init_data){ 529 513 .name = "cam_cc_ipe_1_clk_src", 530 - .parent_names = cam_cc_parent_names_0, 531 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 514 + .parent_data = cam_cc_parent_data_0, 515 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 532 516 .flags = CLK_SET_RATE_PARENT, 533 517 .ops = &clk_rcg2_shared_ops, 534 518 }, ··· 542 526 .freq_tbl = ftbl_cam_cc_bps_clk_src, 543 527 .clkr.hw.init = &(struct clk_init_data){ 544 528 .name = "cam_cc_jpeg_clk_src", 545 - .parent_names = cam_cc_parent_names_0, 546 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 529 + .parent_data = cam_cc_parent_data_0, 530 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 547 531 .flags = CLK_SET_RATE_PARENT, 548 532 .ops = &clk_rcg2_shared_ops, 549 533 }, ··· 567 551 .freq_tbl = ftbl_cam_cc_lrme_clk_src, 568 552 .clkr.hw.init = &(struct clk_init_data){ 569 553 .name = "cam_cc_lrme_clk_src", 570 - .parent_names = cam_cc_parent_names_0, 571 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 554 + .parent_data = cam_cc_parent_data_0, 555 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 572 556 .flags = CLK_SET_RATE_PARENT, 573 557 .ops = &clk_rcg2_shared_ops, 574 558 }, ··· 590 574 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 591 575 .clkr.hw.init = &(struct clk_init_data){ 592 576 .name = "cam_cc_mclk0_clk_src", 593 - .parent_names = cam_cc_parent_names_0, 594 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 577 + .parent_data = cam_cc_parent_data_0, 578 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 595 579 .flags = CLK_SET_RATE_PARENT, 596 580 .ops = &clk_rcg2_ops, 597 581 }, ··· 605 589 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 606 590 .clkr.hw.init = &(struct clk_init_data){ 607 591 .name = "cam_cc_mclk1_clk_src", 608 - .parent_names = cam_cc_parent_names_0, 609 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 592 + .parent_data = cam_cc_parent_data_0, 593 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 610 594 .flags = CLK_SET_RATE_PARENT, 611 595 .ops = &clk_rcg2_ops, 612 596 }, ··· 620 604 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 621 605 .clkr.hw.init = &(struct clk_init_data){ 622 606 .name = "cam_cc_mclk2_clk_src", 623 - .parent_names = cam_cc_parent_names_0, 624 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 607 + .parent_data = cam_cc_parent_data_0, 608 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 625 609 .flags = CLK_SET_RATE_PARENT, 626 610 .ops = &clk_rcg2_ops, 627 611 }, ··· 635 619 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 636 620 .clkr.hw.init = &(struct clk_init_data){ 637 621 .name = "cam_cc_mclk3_clk_src", 638 - .parent_names = cam_cc_parent_names_0, 639 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 622 + .parent_data = cam_cc_parent_data_0, 623 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 640 624 .flags = CLK_SET_RATE_PARENT, 641 625 .ops = &clk_rcg2_ops, 642 626 }, ··· 659 643 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 660 644 .clkr.hw.init = &(struct clk_init_data){ 661 645 .name = "cam_cc_slow_ahb_clk_src", 662 - .parent_names = cam_cc_parent_names_0, 663 - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 646 + .parent_data = cam_cc_parent_data_0, 647 + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 664 648 .flags = CLK_SET_RATE_PARENT, 665 649 .ops = &clk_rcg2_ops, 666 650 }, ··· 674 658 .enable_mask = BIT(0), 675 659 .hw.init = &(struct clk_init_data){ 676 660 .name = "cam_cc_bps_ahb_clk", 677 - .parent_names = (const char *[]){ 678 - "cam_cc_slow_ahb_clk_src", 661 + .parent_hws = (const struct clk_hw*[]){ 662 + &cam_cc_slow_ahb_clk_src.clkr.hw, 679 663 }, 680 664 .num_parents = 1, 681 665 .flags = CLK_SET_RATE_PARENT, ··· 692 676 .enable_mask = BIT(0), 693 677 .hw.init = &(struct clk_init_data){ 694 678 .name = "cam_cc_bps_areg_clk", 695 - .parent_names = (const char *[]){ 696 - "cam_cc_fast_ahb_clk_src", 679 + .parent_hws = (const struct clk_hw*[]){ 680 + &cam_cc_fast_ahb_clk_src.clkr.hw, 697 681 }, 698 682 .num_parents = 1, 699 683 .flags = CLK_SET_RATE_PARENT, ··· 723 707 .enable_mask = BIT(0), 724 708 .hw.init = &(struct clk_init_data){ 725 709 .name = "cam_cc_bps_clk", 726 - .parent_names = (const char *[]){ 727 - "cam_cc_bps_clk_src", 710 + .parent_hws = (const struct clk_hw*[]){ 711 + &cam_cc_bps_clk_src.clkr.hw, 728 712 }, 729 713 .num_parents = 1, 730 714 .flags = CLK_SET_RATE_PARENT, ··· 767 751 .enable_mask = BIT(0), 768 752 .hw.init = &(struct clk_init_data){ 769 753 .name = "cam_cc_cci_clk", 770 - .parent_names = (const char *[]){ 771 - "cam_cc_cci_clk_src", 754 + .parent_hws = (const struct clk_hw*[]){ 755 + &cam_cc_cci_clk_src.clkr.hw, 772 756 }, 773 757 .num_parents = 1, 774 758 .flags = CLK_SET_RATE_PARENT, ··· 785 769 .enable_mask = BIT(0), 786 770 .hw.init = &(struct clk_init_data){ 787 771 .name = "cam_cc_cpas_ahb_clk", 788 - .parent_names = (const char *[]){ 789 - "cam_cc_slow_ahb_clk_src", 772 + .parent_hws = (const struct clk_hw*[]){ 773 + &cam_cc_slow_ahb_clk_src.clkr.hw, 790 774 }, 791 775 .num_parents = 1, 792 776 .flags = CLK_SET_RATE_PARENT, ··· 803 787 .enable_mask = BIT(0), 804 788 .hw.init = &(struct clk_init_data){ 805 789 .name = "cam_cc_csi0phytimer_clk", 806 - .parent_names = (const char *[]){ 807 - "cam_cc_csi0phytimer_clk_src", 790 + .parent_hws = (const struct clk_hw*[]){ 791 + &cam_cc_csi0phytimer_clk_src.clkr.hw, 808 792 }, 809 793 .num_parents = 1, 810 794 .flags = CLK_SET_RATE_PARENT, ··· 821 805 .enable_mask = BIT(0), 822 806 .hw.init = &(struct clk_init_data){ 823 807 .name = "cam_cc_csi1phytimer_clk", 824 - .parent_names = (const char *[]){ 825 - "cam_cc_csi1phytimer_clk_src", 808 + .parent_hws = (const struct clk_hw*[]){ 809 + &cam_cc_csi1phytimer_clk_src.clkr.hw, 826 810 }, 827 811 .num_parents = 1, 828 812 .flags = CLK_SET_RATE_PARENT, ··· 839 823 .enable_mask = BIT(0), 840 824 .hw.init = &(struct clk_init_data){ 841 825 .name = "cam_cc_csi2phytimer_clk", 842 - .parent_names = (const char *[]){ 843 - "cam_cc_csi2phytimer_clk_src", 826 + .parent_hws = (const struct clk_hw*[]){ 827 + &cam_cc_csi2phytimer_clk_src.clkr.hw, 844 828 }, 845 829 .num_parents = 1, 846 830 .flags = CLK_SET_RATE_PARENT, ··· 857 841 .enable_mask = BIT(0), 858 842 .hw.init = &(struct clk_init_data){ 859 843 .name = "cam_cc_csi3phytimer_clk", 860 - .parent_names = (const char *[]){ 861 - "cam_cc_csi3phytimer_clk_src", 844 + .parent_hws = (const struct clk_hw*[]){ 845 + &cam_cc_csi3phytimer_clk_src.clkr.hw, 862 846 }, 863 847 .num_parents = 1, 864 848 .flags = CLK_SET_RATE_PARENT, ··· 875 859 .enable_mask = BIT(0), 876 860 .hw.init = &(struct clk_init_data){ 877 861 .name = "cam_cc_csiphy0_clk", 878 - .parent_names = (const char *[]){ 879 - "cam_cc_cphy_rx_clk_src", 862 + .parent_hws = (const struct clk_hw*[]){ 863 + &cam_cc_cphy_rx_clk_src.clkr.hw, 880 864 }, 881 865 .num_parents = 1, 882 866 .flags = CLK_SET_RATE_PARENT, ··· 893 877 .enable_mask = BIT(0), 894 878 .hw.init = &(struct clk_init_data){ 895 879 .name = "cam_cc_csiphy1_clk", 896 - .parent_names = (const char *[]){ 897 - "cam_cc_cphy_rx_clk_src", 880 + .parent_hws = (const struct clk_hw*[]){ 881 + &cam_cc_cphy_rx_clk_src.clkr.hw, 898 882 }, 899 883 .num_parents = 1, 900 884 .flags = CLK_SET_RATE_PARENT, ··· 911 895 .enable_mask = BIT(0), 912 896 .hw.init = &(struct clk_init_data){ 913 897 .name = "cam_cc_csiphy2_clk", 914 - .parent_names = (const char *[]){ 915 - "cam_cc_cphy_rx_clk_src", 898 + .parent_hws = (const struct clk_hw*[]){ 899 + &cam_cc_cphy_rx_clk_src.clkr.hw, 916 900 }, 917 901 .num_parents = 1, 918 902 .flags = CLK_SET_RATE_PARENT, ··· 929 913 .enable_mask = BIT(0), 930 914 .hw.init = &(struct clk_init_data){ 931 915 .name = "cam_cc_csiphy3_clk", 932 - .parent_names = (const char *[]){ 933 - "cam_cc_cphy_rx_clk_src", 916 + .parent_hws = (const struct clk_hw*[]){ 917 + &cam_cc_cphy_rx_clk_src.clkr.hw, 934 918 }, 935 919 .num_parents = 1, 936 920 .flags = CLK_SET_RATE_PARENT, ··· 947 931 .enable_mask = BIT(0), 948 932 .hw.init = &(struct clk_init_data){ 949 933 .name = "cam_cc_fd_core_clk", 950 - .parent_names = (const char *[]){ 951 - "cam_cc_fd_core_clk_src", 934 + .parent_hws = (const struct clk_hw*[]){ 935 + &cam_cc_fd_core_clk_src.clkr.hw, 952 936 }, 953 937 .num_parents = 1, 954 938 .flags = CLK_SET_RATE_PARENT, ··· 965 949 .enable_mask = BIT(0), 966 950 .hw.init = &(struct clk_init_data){ 967 951 .name = "cam_cc_fd_core_uar_clk", 968 - .parent_names = (const char *[]){ 969 - "cam_cc_fd_core_clk_src", 952 + .parent_hws = (const struct clk_hw*[]){ 953 + &cam_cc_fd_core_clk_src.clkr.hw, 970 954 }, 971 955 .num_parents = 1, 972 956 .ops = &clk_branch2_ops, ··· 1008 992 .enable_mask = BIT(0), 1009 993 .hw.init = &(struct clk_init_data){ 1010 994 .name = "cam_cc_icp_clk", 1011 - .parent_names = (const char *[]){ 1012 - "cam_cc_icp_clk_src", 995 + .parent_hws = (const struct clk_hw*[]){ 996 + &cam_cc_icp_clk_src.clkr.hw, 1013 997 }, 1014 998 .num_parents = 1, 1015 999 .flags = CLK_SET_RATE_PARENT, ··· 1065 1049 .enable_mask = BIT(0), 1066 1050 .hw.init = &(struct clk_init_data){ 1067 1051 .name = "cam_cc_ife_0_clk", 1068 - .parent_names = (const char *[]){ 1069 - "cam_cc_ife_0_clk_src", 1052 + .parent_hws = (const struct clk_hw*[]){ 1053 + &cam_cc_ife_0_clk_src.clkr.hw, 1070 1054 }, 1071 1055 .num_parents = 1, 1072 1056 .flags = CLK_SET_RATE_PARENT, ··· 1083 1067 .enable_mask = BIT(0), 1084 1068 .hw.init = &(struct clk_init_data){ 1085 1069 .name = "cam_cc_ife_0_cphy_rx_clk", 1086 - .parent_names = (const char *[]){ 1087 - "cam_cc_cphy_rx_clk_src", 1070 + .parent_hws = (const struct clk_hw*[]){ 1071 + &cam_cc_cphy_rx_clk_src.clkr.hw, 1088 1072 }, 1089 1073 .num_parents = 1, 1090 1074 .flags = CLK_SET_RATE_PARENT, ··· 1101 1085 .enable_mask = BIT(0), 1102 1086 .hw.init = &(struct clk_init_data){ 1103 1087 .name = "cam_cc_ife_0_csid_clk", 1104 - .parent_names = (const char *[]){ 1105 - "cam_cc_ife_0_csid_clk_src", 1088 + .parent_hws = (const struct clk_hw*[]){ 1089 + &cam_cc_ife_0_csid_clk_src.clkr.hw, 1106 1090 }, 1107 1091 .num_parents = 1, 1108 1092 .flags = CLK_SET_RATE_PARENT, ··· 1119 1103 .enable_mask = BIT(0), 1120 1104 .hw.init = &(struct clk_init_data){ 1121 1105 .name = "cam_cc_ife_0_dsp_clk", 1122 - .parent_names = (const char *[]){ 1123 - "cam_cc_ife_0_clk_src", 1106 + .parent_hws = (const struct clk_hw*[]){ 1107 + &cam_cc_ife_0_clk_src.clkr.hw, 1124 1108 }, 1125 1109 .num_parents = 1, 1126 1110 .ops = &clk_branch2_ops, ··· 1149 1133 .enable_mask = BIT(0), 1150 1134 .hw.init = &(struct clk_init_data){ 1151 1135 .name = "cam_cc_ife_1_clk", 1152 - .parent_names = (const char *[]){ 1153 - "cam_cc_ife_1_clk_src", 1136 + .parent_hws = (const struct clk_hw*[]){ 1137 + &cam_cc_ife_1_clk_src.clkr.hw, 1154 1138 }, 1155 1139 .num_parents = 1, 1156 1140 .flags = CLK_SET_RATE_PARENT, ··· 1167 1151 .enable_mask = BIT(0), 1168 1152 .hw.init = &(struct clk_init_data){ 1169 1153 .name = "cam_cc_ife_1_cphy_rx_clk", 1170 - .parent_names = (const char *[]){ 1171 - "cam_cc_cphy_rx_clk_src", 1154 + .parent_hws = (const struct clk_hw*[]){ 1155 + &cam_cc_cphy_rx_clk_src.clkr.hw, 1172 1156 }, 1173 1157 .num_parents = 1, 1174 1158 .flags = CLK_SET_RATE_PARENT, ··· 1185 1169 .enable_mask = BIT(0), 1186 1170 .hw.init = &(struct clk_init_data){ 1187 1171 .name = "cam_cc_ife_1_csid_clk", 1188 - .parent_names = (const char *[]){ 1189 - "cam_cc_ife_1_csid_clk_src", 1172 + .parent_hws = (const struct clk_hw*[]){ 1173 + &cam_cc_ife_1_csid_clk_src.clkr.hw, 1190 1174 }, 1191 1175 .num_parents = 1, 1192 1176 .flags = CLK_SET_RATE_PARENT, ··· 1203 1187 .enable_mask = BIT(0), 1204 1188 .hw.init = &(struct clk_init_data){ 1205 1189 .name = "cam_cc_ife_1_dsp_clk", 1206 - .parent_names = (const char *[]){ 1207 - "cam_cc_ife_1_clk_src", 1190 + .parent_hws = (const struct clk_hw*[]){ 1191 + &cam_cc_ife_1_clk_src.clkr.hw, 1208 1192 }, 1209 1193 .num_parents = 1, 1210 1194 .ops = &clk_branch2_ops, ··· 1220 1204 .enable_mask = BIT(0), 1221 1205 .hw.init = &(struct clk_init_data){ 1222 1206 .name = "cam_cc_ife_lite_clk", 1223 - .parent_names = (const char *[]){ 1224 - "cam_cc_ife_lite_clk_src", 1207 + .parent_hws = (const struct clk_hw*[]){ 1208 + &cam_cc_ife_lite_clk_src.clkr.hw, 1225 1209 }, 1226 1210 .num_parents = 1, 1227 1211 .flags = CLK_SET_RATE_PARENT, ··· 1238 1222 .enable_mask = BIT(0), 1239 1223 .hw.init = &(struct clk_init_data){ 1240 1224 .name = "cam_cc_ife_lite_cphy_rx_clk", 1241 - .parent_names = (const char *[]){ 1242 - "cam_cc_cphy_rx_clk_src", 1225 + .parent_hws = (const struct clk_hw*[]){ 1226 + &cam_cc_cphy_rx_clk_src.clkr.hw, 1243 1227 }, 1244 1228 .num_parents = 1, 1245 1229 .flags = CLK_SET_RATE_PARENT, ··· 1256 1240 .enable_mask = BIT(0), 1257 1241 .hw.init = &(struct clk_init_data){ 1258 1242 .name = "cam_cc_ife_lite_csid_clk", 1259 - .parent_names = (const char *[]){ 1260 - "cam_cc_ife_lite_csid_clk_src", 1243 + .parent_hws = (const struct clk_hw*[]){ 1244 + &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1261 1245 }, 1262 1246 .num_parents = 1, 1263 1247 .flags = CLK_SET_RATE_PARENT, ··· 1274 1258 .enable_mask = BIT(0), 1275 1259 .hw.init = &(struct clk_init_data){ 1276 1260 .name = "cam_cc_ipe_0_ahb_clk", 1277 - .parent_names = (const char *[]){ 1278 - "cam_cc_slow_ahb_clk_src", 1261 + .parent_hws = (const struct clk_hw*[]){ 1262 + &cam_cc_slow_ahb_clk_src.clkr.hw, 1279 1263 }, 1280 1264 .num_parents = 1, 1281 1265 .flags = CLK_SET_RATE_PARENT, ··· 1292 1276 .enable_mask = BIT(0), 1293 1277 .hw.init = &(struct clk_init_data){ 1294 1278 .name = "cam_cc_ipe_0_areg_clk", 1295 - .parent_names = (const char *[]){ 1296 - "cam_cc_fast_ahb_clk_src", 1279 + .parent_hws = (const struct clk_hw*[]){ 1280 + &cam_cc_fast_ahb_clk_src.clkr.hw, 1297 1281 }, 1298 1282 .num_parents = 1, 1299 1283 .flags = CLK_SET_RATE_PARENT, ··· 1323 1307 .enable_mask = BIT(0), 1324 1308 .hw.init = &(struct clk_init_data){ 1325 1309 .name = "cam_cc_ipe_0_clk", 1326 - .parent_names = (const char *[]){ 1327 - "cam_cc_ipe_0_clk_src", 1310 + .parent_hws = (const struct clk_hw*[]){ 1311 + &cam_cc_ipe_0_clk_src.clkr.hw, 1328 1312 }, 1329 1313 .num_parents = 1, 1330 1314 .flags = CLK_SET_RATE_PARENT, ··· 1341 1325 .enable_mask = BIT(0), 1342 1326 .hw.init = &(struct clk_init_data){ 1343 1327 .name = "cam_cc_ipe_1_ahb_clk", 1344 - .parent_names = (const char *[]){ 1345 - "cam_cc_slow_ahb_clk_src", 1328 + .parent_hws = (const struct clk_hw*[]){ 1329 + &cam_cc_slow_ahb_clk_src.clkr.hw, 1346 1330 }, 1347 1331 .num_parents = 1, 1348 1332 .flags = CLK_SET_RATE_PARENT, ··· 1359 1343 .enable_mask = BIT(0), 1360 1344 .hw.init = &(struct clk_init_data){ 1361 1345 .name = "cam_cc_ipe_1_areg_clk", 1362 - .parent_names = (const char *[]){ 1363 - "cam_cc_fast_ahb_clk_src", 1346 + .parent_hws = (const struct clk_hw*[]){ 1347 + &cam_cc_fast_ahb_clk_src.clkr.hw, 1364 1348 }, 1365 1349 .num_parents = 1, 1366 1350 .flags = CLK_SET_RATE_PARENT, ··· 1390 1374 .enable_mask = BIT(0), 1391 1375 .hw.init = &(struct clk_init_data){ 1392 1376 .name = "cam_cc_ipe_1_clk", 1393 - .parent_names = (const char *[]){ 1394 - "cam_cc_ipe_1_clk_src", 1377 + .parent_hws = (const struct clk_hw*[]){ 1378 + &cam_cc_ipe_1_clk_src.clkr.hw, 1395 1379 }, 1396 1380 .num_parents = 1, 1397 1381 .flags = CLK_SET_RATE_PARENT, ··· 1408 1392 .enable_mask = BIT(0), 1409 1393 .hw.init = &(struct clk_init_data){ 1410 1394 .name = "cam_cc_jpeg_clk", 1411 - .parent_names = (const char *[]){ 1412 - "cam_cc_jpeg_clk_src", 1395 + .parent_hws = (const struct clk_hw*[]){ 1396 + &cam_cc_jpeg_clk_src.clkr.hw, 1413 1397 }, 1414 1398 .num_parents = 1, 1415 1399 .flags = CLK_SET_RATE_PARENT, ··· 1426 1410 .enable_mask = BIT(0), 1427 1411 .hw.init = &(struct clk_init_data){ 1428 1412 .name = "cam_cc_lrme_clk", 1429 - .parent_names = (const char *[]){ 1430 - "cam_cc_lrme_clk_src", 1413 + .parent_hws = (const struct clk_hw*[]){ 1414 + &cam_cc_lrme_clk_src.clkr.hw, 1431 1415 }, 1432 1416 .num_parents = 1, 1433 1417 .flags = CLK_SET_RATE_PARENT, ··· 1444 1428 .enable_mask = BIT(0), 1445 1429 .hw.init = &(struct clk_init_data){ 1446 1430 .name = "cam_cc_mclk0_clk", 1447 - .parent_names = (const char *[]){ 1448 - "cam_cc_mclk0_clk_src", 1431 + .parent_hws = (const struct clk_hw*[]){ 1432 + &cam_cc_mclk0_clk_src.clkr.hw, 1449 1433 }, 1450 1434 .num_parents = 1, 1451 1435 .flags = CLK_SET_RATE_PARENT, ··· 1462 1446 .enable_mask = BIT(0), 1463 1447 .hw.init = &(struct clk_init_data){ 1464 1448 .name = "cam_cc_mclk1_clk", 1465 - .parent_names = (const char *[]){ 1466 - "cam_cc_mclk1_clk_src", 1449 + .parent_hws = (const struct clk_hw*[]){ 1450 + &cam_cc_mclk1_clk_src.clkr.hw, 1467 1451 }, 1468 1452 .num_parents = 1, 1469 1453 .flags = CLK_SET_RATE_PARENT, ··· 1480 1464 .enable_mask = BIT(0), 1481 1465 .hw.init = &(struct clk_init_data){ 1482 1466 .name = "cam_cc_mclk2_clk", 1483 - .parent_names = (const char *[]){ 1484 - "cam_cc_mclk2_clk_src", 1467 + .parent_hws = (const struct clk_hw*[]){ 1468 + &cam_cc_mclk2_clk_src.clkr.hw, 1485 1469 }, 1486 1470 .num_parents = 1, 1487 1471 .flags = CLK_SET_RATE_PARENT, ··· 1498 1482 .enable_mask = BIT(0), 1499 1483 .hw.init = &(struct clk_init_data){ 1500 1484 .name = "cam_cc_mclk3_clk", 1501 - .parent_names = (const char *[]){ 1502 - "cam_cc_mclk3_clk_src", 1485 + .parent_hws = (const struct clk_hw*[]){ 1486 + &cam_cc_mclk3_clk_src.clkr.hw, 1503 1487 }, 1504 1488 .num_parents = 1, 1505 1489 .flags = CLK_SET_RATE_PARENT,