tjh.dev / kernel
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drm/amdgpu: Calling address translation functions to simplify codes

Use amdgpu_gmc_vram_pa and amdgpu_gmc_vram_cpu_pa
to simplify codes. No logic change.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Oak Zeng and committed by
Alex Deucher 0ca565ab dead5e42

+12 -25
+1 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
··· 205 205 struct drm_gem_object *gobj = NULL; 206 206 struct amdgpu_bo *abo = NULL; 207 207 int ret; 208 - unsigned long tmp; 209 208 210 209 memset(&mode_cmd, 0, sizeof(mode_cmd)); 211 210 mode_cmd.width = sizes->surface_width; ··· 245 246 246 247 info->fbops = &amdgpufb_ops; 247 248 248 - tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start; 249 - info->fix.smem_start = adev->gmc.aper_base + tmp; 249 + info->fix.smem_start = amdgpu_gmc_vram_cpu_pa(adev, abo); 250 250 info->fix.smem_len = amdgpu_bo_size(abo); 251 251 info->screen_base = amdgpu_bo_kptr(abo); 252 252 info->screen_size = amdgpu_bo_size(abo);
+1 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
··· 661 661 u64 vram_addr = adev->vm_manager.vram_base_offset - 662 662 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 663 663 u64 vram_end = vram_addr + vram_size; 664 - u64 gart_ptb_gpu_pa = amdgpu_bo_gpu_offset(adev->gart.bo) + 665 - adev->vm_manager.vram_base_offset - adev->gmc.vram_start; 664 + u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo); 666 665 667 666 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE; 668 667 flags |= AMDGPU_PTE_WRITEABLE;
+1 -2
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
··· 120 120 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 121 121 122 122 /* Set default page address. */ 123 - value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 124 - adev->vm_manager.vram_base_offset; 123 + value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 125 124 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 126 125 (u32)(value >> 12)); 127 126 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+1 -2
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
··· 165 165 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 166 166 167 167 /* Set default page address. */ 168 - value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 169 - + adev->vm_manager.vram_base_offset; 168 + value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 170 169 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 171 170 (u32)(value >> 12)); 172 171 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+1 -2
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
··· 164 164 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 165 165 166 166 /* Set default page address. */ 167 - value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 168 - + adev->vm_manager.vram_base_offset; 167 + value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 169 168 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 170 169 (u32)(value >> 12)); 171 170 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+1 -2
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
··· 568 568 uint64_t *addr, uint64_t *flags) 569 569 { 570 570 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 571 - *addr = adev->vm_manager.vram_base_offset + *addr - 572 - adev->gmc.vram_start; 571 + *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 573 572 BUG_ON(*addr & 0xFFFF00000000003FULL); 574 573 575 574 if (!adev->gmc.translate_further)
+1 -2
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
··· 1048 1048 uint64_t *addr, uint64_t *flags) 1049 1049 { 1050 1050 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1051 - *addr = adev->vm_manager.vram_base_offset + *addr - 1052 - adev->gmc.vram_start; 1051 + *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1053 1052 BUG_ON(*addr & 0xFFFF00000000003FULL); 1054 1053 1055 1054 if (!adev->gmc.translate_further)
+1 -2
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
··· 114 114 return; 115 115 116 116 /* Set default page address. */ 117 - value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 118 - adev->vm_manager.vram_base_offset; 117 + value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 119 118 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 120 119 (u32)(value >> 12)); 121 120 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+1 -2
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
··· 135 135 return; 136 136 137 137 /* Set default page address. */ 138 - value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 139 - adev->vm_manager.vram_base_offset; 138 + value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 140 139 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 141 140 (u32)(value >> 12)); 142 141 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+1 -2
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
··· 210 210 } 211 211 212 212 /* Set default page address. */ 213 - value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 214 - adev->vm_manager.vram_base_offset; 213 + value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 215 214 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 216 215 (u32)(value >> 12)); 217 216 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+1 -2
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
··· 162 162 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 163 163 164 164 /* Set default page address. */ 165 - value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 166 - adev->vm_manager.vram_base_offset; 165 + value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 167 166 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 168 167 (u32)(value >> 12)); 169 168 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+1 -2
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
··· 136 136 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 137 137 138 138 /* Set default page address. */ 139 - value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 140 - adev->vm_manager.vram_base_offset; 139 + value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 141 140 WREG32_SOC15_OFFSET( 142 141 MMHUB, 0, 143 142 mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,