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powerpc/8xx: Restore _PAGE_WRITETHRU

8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them to WRITETHRU.

Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE?

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

authored by

Joakim Tjernlund and committed by
Benjamin Herrenschmidt 0c466169 4a280a41

+11 -2
+3 -2
arch/powerpc/include/asm/pte-8xx.h
··· 35 35 #define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */ 36 36 #define _PAGE_DIRTY 0x0100 /* C: page changed */ 37 37 38 - /* These 3 software bits must be masked out when the entry is loaded 39 - * into the TLB, 2 SW bits left. 38 + /* These 4 software bits must be masked out when the entry is loaded 39 + * into the TLB, 1 SW bit left(0x0080). 40 40 */ 41 41 #define _PAGE_GUARDED 0x0010 /* software: guarded access */ 42 42 #define _PAGE_ACCESSED 0x0020 /* software: page referenced */ 43 + #define _PAGE_WRITETHRU 0x0040 /* software: caching is write through */ 43 44 44 45 /* Setting any bits in the nibble with the follow two controls will 45 46 * require a TLB exception handler change. It is assumed unused bits
+8
arch/powerpc/kernel/head_8xx.S
··· 422 422 * above. 423 423 */ 424 424 rlwimi r11, r10, 0, 27, 27 425 + /* Insert the WriteThru flag into the TWC from the Linux PTE. 426 + * It is bit 25 in the Linux PTE and bit 30 in the TWC 427 + */ 428 + rlwimi r11, r10, 32-5, 30, 30 425 429 DO_8xx_CPU6(0x3b80, r3) 426 430 mtspr SPRN_MD_TWC, r11 427 431 ··· 563 559 * It is bit 27 of both the Linux PTE and the TWC 564 560 */ 565 561 rlwimi r11, r10, 0, 27, 27 562 + /* Insert the WriteThru flag into the TWC from the Linux PTE. 563 + * It is bit 25 in the Linux PTE and bit 30 in the TWC 564 + */ 565 + rlwimi r11, r10, 32-5, 30, 30 566 566 DO_8xx_CPU6(0x3b80, r3) 567 567 mtspr SPRN_MD_TWC, r11 568 568 mfspr r11, SPRN_MD_TWC /* get the pte address again */