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ARM: dts: dm814x: dra62x: Fix NAND device nodes

Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.

The GPMC node will provide an interrupt controller for the
NAND IRQs.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

authored by

Roger Quadros and committed by
Tony Lindgren 0c3e192a 5fcc6730

+14 -2
+6 -1
arch/arm/boot/dts/dm8148-evm.dts
··· 6 6 /dts-v1/; 7 7 8 8 #include "dm814x.dtsi" 9 + #include <dt-bindings/interrupt-controller/irq.h> 9 10 10 11 / { 11 12 model = "DM8148 EVM"; ··· 40 39 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ 41 40 42 41 nand@0,0 { 43 - linux,mtd-name= "micron,mt29f2g16aadwp"; 42 + compatible = "ti,omap2-nand"; 44 43 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 44 + interrupt-parent = <&gpmc>; 45 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 46 + <1 IRQ_TYPE_NONE>; /* termcount */ 47 + linux,mtd-name= "micron,mt29f2g16aadwp"; 45 48 #address-cells = <1>; 46 49 #size-cells = <1>; 47 50 ti,nand-ecc-opt = "bch8";
+2
arch/arm/boot/dts/dm814x.dtsi
··· 566 566 gpmc,num-waitpins = <2>; 567 567 #address-cells = <2>; 568 568 #size-cells = <1>; 569 + interrupt-controller; 570 + #interrupt-cells = <2>; 569 571 }; 570 572 }; 571 573 };
+6 -1
arch/arm/boot/dts/dra62x-j5eco-evm.dts
··· 6 6 /dts-v1/; 7 7 8 8 #include "dra62x.dtsi" 9 + #include <dt-bindings/interrupt-controller/irq.h> 9 10 10 11 / { 11 12 model = "DRA62x J5 Eco EVM"; ··· 40 39 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ 41 40 42 41 nand@0,0 { 43 - linux,mtd-name= "micron,mt29f2g16aadwp"; 42 + compatible = "ti,omap2-nand"; 44 43 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 44 + interrupt-parent = <&gpmc>; 45 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 46 + <1 IRQ_TYPE_NONE>; /* termcount */ 47 + linux,mtd-name= "micron,mt29f2g16aadwp"; 45 48 #address-cells = <1>; 46 49 #size-cells = <1>; 47 50 ti,nand-ecc-opt = "bch8";