tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu/vcn2.5: implement indirect DPG SRAM mode

Implement indirect DPG SRAM mode for vcn2.5

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

James Zhu and committed by
Alex Deucher 0c0dab86 8484df96

+52 -20
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
··· 75 75 break; 76 76 case CHIP_ARCTURUS: 77 77 fw_name = FIRMWARE_ARCTURUS; 78 + if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && 79 + (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) 80 + adev->vcn.indirect_sram = true; 78 81 break; 79 82 case CHIP_RENOIR: 80 83 fw_name = FIRMWARE_RENOIR;
+49 -20
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
··· 433 433 434 434 /* cache window 0: fw */ 435 435 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 436 - WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 437 - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 438 - (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 439 - WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 440 - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 441 - (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 442 - WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 443 - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 436 + if (!indirect) { 437 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 438 + UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 439 + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 440 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 441 + UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 442 + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 443 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 444 + UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 445 + } else { 446 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 447 + UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 448 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 449 + UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 450 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 451 + UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 452 + } 444 453 offset = 0; 445 454 } else { 446 455 WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( ··· 464 455 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 465 456 } 466 457 467 - WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 468 - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 458 + if (!indirect) 459 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 460 + UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 461 + else 462 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 463 + UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 469 464 470 465 /* cache window 1: stack */ 471 - WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 472 - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 473 - lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 474 - WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 475 - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 476 - upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 477 - WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 478 - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 479 - 466 + if (!indirect) { 467 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 468 + UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 469 + lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 470 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 471 + UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 472 + upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 473 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 474 + UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 475 + } else { 476 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 477 + UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 478 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 479 + UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 480 + WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 481 + UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 482 + } 480 483 WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0( 481 484 UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 482 485 ··· 761 740 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 762 741 WREG32_SOC15(UVD, inst_idx, mmUVD_POWER_STATUS, tmp); 763 742 743 + if (indirect) 744 + adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 745 + 764 746 /* enable clock gating */ 765 747 vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 766 748 ··· 839 815 UVD, inst_idx, mmUVD_MASTINT_EN), 840 816 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 841 817 818 + if (indirect) 819 + psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 820 + (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 821 + (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 822 + 842 823 ring = &adev->vcn.inst[inst_idx].ring_dec; 843 824 /* force RBC into idle state */ 844 825 rb_bufsz = order_base_2(ring->ring_size); ··· 892 863 if (adev->vcn.harvest_config & (1 << i)) 893 864 continue; 894 865 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 895 - return vcn_v2_5_start_dpg_mode(adev, i, 0); 866 + return vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 896 867 897 868 /* disable register anti-hang mechanism */ 898 869 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,