tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/nouveau: Fix missing whitespace checkpatch.pl errors.

This patch fixes messages such as
ERROR: space required after that ','
ERROR: spaces required around that '='

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>

authored by

Emil Velikov and committed by
Ben Skeggs 0b89a072 f9ec8f6c

+22 -22
+2 -2
drivers/gpu/drm/nouveau/nouveau_drv.h
··· 883 883 extern void nouveau_channel_idle(struct nouveau_channel *chan); 884 884 885 885 /* nouveau_object.c */ 886 - #define NVOBJ_CLASS(d,c,e) do { \ 886 + #define NVOBJ_CLASS(d, c, e) do { \ 887 887 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 888 888 if (ret) \ 889 889 return ret; \ 890 890 } while (0) 891 891 892 - #define NVOBJ_MTHD(d,c,m,e) do { \ 892 + #define NVOBJ_MTHD(d, c, m, e) do { \ 893 893 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 894 894 if (ret) \ 895 895 return ret; \
+5 -5
drivers/gpu/drm/nouveau/nouveau_grctx.h
··· 87 87 cp_out(ctx, CP_BRA | (mod << 18) | ip | flag | 88 88 (state ? 0 : CP_BRA_IF_CLEAR)); 89 89 } 90 - #define cp_bra(c,f,s,n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n) 90 + #define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n) 91 91 #ifdef CP_BRA_MOD 92 - #define cp_cal(c,f,s,n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n) 93 - #define cp_ret(c,f,s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0) 92 + #define cp_cal(c, f, s, n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n) 93 + #define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0) 94 94 #endif 95 95 96 96 static inline void ··· 98 98 { 99 99 cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0)); 100 100 } 101 - #define cp_wait(c,f,s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s) 101 + #define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s) 102 102 103 103 static inline void 104 104 _cp_set(struct nouveau_grctx *ctx, int flag, int state) 105 105 { 106 106 cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0)); 107 107 } 108 - #define cp_set(c,f,s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s) 108 + #define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s) 109 109 110 110 static inline void 111 111 cp_pos(struct nouveau_grctx *ctx, int offset)
+2 -2
drivers/gpu/drm/nouveau/nouveau_mem.c
··· 600 600 /* Get "some number" from the timing reg for NV_40 601 601 * Used in calculations later */ 602 602 if (dev_priv->card_type == NV_40) { 603 - magic_number = (nv_rd32(dev,0x100228) & 0x0f000000) >> 24; 603 + magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24; 604 604 } 605 605 606 606 entry = mem + mem[1]; ··· 668 668 tUNK_13 << 8 | tUNK_13); 669 669 670 670 timing->reg_100234 = (tRAS << 24 | tRC); 671 - timing->reg_100234 += max(tUNK_10,tUNK_11) << 16; 671 + timing->reg_100234 += max(tUNK_10, tUNK_11) << 16; 672 672 673 673 if (dev_priv->chipset < 0xa3) { 674 674 timing->reg_100234 |= (tUNK_2 + 2) << 8;
+7 -7
drivers/gpu/drm/nouveau/nouveau_reg.h
··· 639 639 # define NV50_PCONNECTOR_I2C_PORT_4 0x0000e240 640 640 # define NV50_PCONNECTOR_I2C_PORT_5 0x0000e258 641 641 642 - #define NV50_AUXCH_DATA_OUT(i,n) ((n) * 4 + (i) * 0x50 + 0x0000e4c0) 642 + #define NV50_AUXCH_DATA_OUT(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4c0) 643 643 #define NV50_AUXCH_DATA_OUT__SIZE 4 644 - #define NV50_AUXCH_DATA_IN(i,n) ((n) * 4 + (i) * 0x50 + 0x0000e4d0) 644 + #define NV50_AUXCH_DATA_IN(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4d0) 645 645 #define NV50_AUXCH_DATA_IN__SIZE 4 646 646 #define NV50_AUXCH_ADDR(i) ((i) * 0x50 + 0x0000e4e0) 647 647 #define NV50_AUXCH_CTRL(i) ((i) * 0x50 + 0x0000e4e4) ··· 829 829 #define NV50_PDISPLAY_SOR_BACKLIGHT 0x0061c084 830 830 #define NV50_PDISPLAY_SOR_BACKLIGHT_ENABLE 0x80000000 831 831 #define NV50_PDISPLAY_SOR_BACKLIGHT_LEVEL 0x00000fff 832 - #define NV50_SOR_DP_CTRL(i,l) (0x0061c10c + (i) * 0x800 + (l) * 0x80) 832 + #define NV50_SOR_DP_CTRL(i, l) (0x0061c10c + (i) * 0x800 + (l) * 0x80) 833 833 #define NV50_SOR_DP_CTRL_ENABLED 0x00000001 834 834 #define NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED 0x00004000 835 835 #define NV50_SOR_DP_CTRL_LANE_MASK 0x001f0000 ··· 841 841 #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_DISABLED 0x00000000 842 842 #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_1 0x01000000 843 843 #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_2 0x02000000 844 - #define NV50_SOR_DP_UNK118(i,l) (0x0061c118 + (i) * 0x800 + (l) * 0x80) 845 - #define NV50_SOR_DP_UNK120(i,l) (0x0061c120 + (i) * 0x800 + (l) * 0x80) 846 - #define NV50_SOR_DP_UNK128(i,l) (0x0061c128 + (i) * 0x800 + (l) * 0x80) 847 - #define NV50_SOR_DP_UNK130(i,l) (0x0061c130 + (i) * 0x800 + (l) * 0x80) 844 + #define NV50_SOR_DP_UNK118(i, l) (0x0061c118 + (i) * 0x800 + (l) * 0x80) 845 + #define NV50_SOR_DP_UNK120(i, l) (0x0061c120 + (i) * 0x800 + (l) * 0x80) 846 + #define NV50_SOR_DP_UNK128(i, l) (0x0061c128 + (i) * 0x800 + (l) * 0x80) 847 + #define NV50_SOR_DP_UNK130(i, l) (0x0061c130 + (i) * 0x800 + (l) * 0x80) 848 848 849 849 #define NV50_PDISPLAY_USER(i) ((i) * 0x1000 + 0x00640000) 850 850 #define NV50_PDISPLAY_USER_PUT(i) ((i) * 0x1000 + 0x00640000)
+1 -1
drivers/gpu/drm/nouveau/nv50_graph.c
··· 662 662 nv_rd32(dev, addr + 0x20); 663 663 pc = nv_rd32(dev, addr + 0x24); 664 664 oplow = nv_rd32(dev, addr + 0x70); 665 - ophigh= nv_rd32(dev, addr + 0x74); 665 + ophigh = nv_rd32(dev, addr + 0x74); 666 666 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - " 667 667 "TP %d MP %d: ", tpid, i); 668 668 nouveau_enum_print(nv50_mp_exec_error_names, status);
+5 -5
drivers/gpu/drm/nouveau/nvc0_graph.h
··· 28 28 #define GPC_MAX 4 29 29 #define TP_MAX 32 30 30 31 - #define ROP_BCAST(r) (0x408800 + (r)) 32 - #define ROP_UNIT(u,r) (0x410000 + (u) * 0x400 + (r)) 33 - #define GPC_BCAST(r) (0x418000 + (r)) 34 - #define GPC_UNIT(t,r) (0x500000 + (t) * 0x8000 + (r)) 35 - #define TP_UNIT(t,m,r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r)) 31 + #define ROP_BCAST(r) (0x408800 + (r)) 32 + #define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r)) 33 + #define GPC_BCAST(r) (0x418000 + (r)) 34 + #define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r)) 35 + #define TP_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r)) 36 36 37 37 struct nvc0_graph_priv { 38 38 u8 gpc_nr;