Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband:
mlx4_core: Increase command timeout for INIT_HCA to 10 seconds
IPoIB/cm: Use common CQ for CM send completions
IB/uverbs: Fix checking of userspace object ownership
IB/mlx4: Sanity check userspace send queue sizes
IPoIB: Rewrite "if (!likely(...))" as "if (unlikely(!(...)))"
IB/ehca: Enable large page MRs by default
IB/ehca: Change meaning of hca_cap_mr_pgsize
IB/ehca: Fix ehca_encode_hwpage_size() and alloc_fmr()
IB/ehca: Fix masking error in {,re}reg_phys_mr()
IB/ehca: Supply QP token for SRQ base QPs
IPoIB: Use round_jiffies() for ah_reap_task
RDMA/cma: Fix deadlock destroying listen requests
RDMA/cma: Add locking around QP accesses
IB/mthca: Avoid alignment traps when writing doorbells
mlx4_core: Kill mlx4_write64_raw()

+287 -327
+83 -77
drivers/infiniband/core/cma.c
··· 114 115 struct rdma_bind_list *bind_list; 116 struct hlist_node node; 117 - struct list_head list; 118 - struct list_head listen_list; 119 struct cma_device *cma_dev; 120 struct list_head mc_list; 121 122 enum cma_state state; 123 spinlock_t lock; 124 struct completion comp; 125 atomic_t refcount; 126 wait_queue_head_t wait_remove; ··· 392 id_priv->id.event_handler = event_handler; 393 id_priv->id.ps = ps; 394 spin_lock_init(&id_priv->lock); 395 init_completion(&id_priv->comp); 396 atomic_set(&id_priv->refcount, 1); 397 init_waitqueue_head(&id_priv->wait_remove); ··· 478 479 void rdma_destroy_qp(struct rdma_cm_id *id) 480 { 481 - ib_destroy_qp(id->qp); 482 } 483 EXPORT_SYMBOL(rdma_destroy_qp); 484 485 - static int cma_modify_qp_rtr(struct rdma_cm_id *id) 486 { 487 struct ib_qp_attr qp_attr; 488 int qp_attr_mask, ret; 489 490 - if (!id->qp) 491 - return 0; 492 493 /* Need to update QP attributes from default values. */ 494 qp_attr.qp_state = IB_QPS_INIT; 495 - ret = rdma_init_qp_attr(id, &qp_attr, &qp_attr_mask); 496 if (ret) 497 - return ret; 498 499 - ret = ib_modify_qp(id->qp, &qp_attr, qp_attr_mask); 500 if (ret) 501 - return ret; 502 503 qp_attr.qp_state = IB_QPS_RTR; 504 - ret = rdma_init_qp_attr(id, &qp_attr, &qp_attr_mask); 505 if (ret) 506 - return ret; 507 508 - return ib_modify_qp(id->qp, &qp_attr, qp_attr_mask); 509 } 510 511 - static int cma_modify_qp_rts(struct rdma_cm_id *id) 512 { 513 struct ib_qp_attr qp_attr; 514 int qp_attr_mask, ret; 515 516 - if (!id->qp) 517 - return 0; 518 519 qp_attr.qp_state = IB_QPS_RTS; 520 - ret = rdma_init_qp_attr(id, &qp_attr, &qp_attr_mask); 521 if (ret) 522 - return ret; 523 524 - return ib_modify_qp(id->qp, &qp_attr, qp_attr_mask); 525 } 526 527 - static int cma_modify_qp_err(struct rdma_cm_id *id) 528 { 529 struct ib_qp_attr qp_attr; 530 531 - if (!id->qp) 532 - return 0; 533 534 qp_attr.qp_state = IB_QPS_ERR; 535 - return ib_modify_qp(id->qp, &qp_attr, IB_QP_STATE); 536 } 537 538 static int cma_ib_init_qp_attr(struct rdma_id_private *id_priv, ··· 746 } 747 } 748 749 - static inline int cma_internal_listen(struct rdma_id_private *id_priv) 750 - { 751 - return (id_priv->state == CMA_LISTEN) && id_priv->cma_dev && 752 - cma_any_addr(&id_priv->id.route.addr.src_addr); 753 - } 754 - 755 - static void cma_destroy_listen(struct rdma_id_private *id_priv) 756 - { 757 - cma_exch(id_priv, CMA_DESTROYING); 758 - 759 - if (id_priv->cma_dev) { 760 - switch (rdma_node_get_transport(id_priv->id.device->node_type)) { 761 - case RDMA_TRANSPORT_IB: 762 - if (id_priv->cm_id.ib && !IS_ERR(id_priv->cm_id.ib)) 763 - ib_destroy_cm_id(id_priv->cm_id.ib); 764 - break; 765 - case RDMA_TRANSPORT_IWARP: 766 - if (id_priv->cm_id.iw && !IS_ERR(id_priv->cm_id.iw)) 767 - iw_destroy_cm_id(id_priv->cm_id.iw); 768 - break; 769 - default: 770 - break; 771 - } 772 - cma_detach_from_dev(id_priv); 773 - } 774 - list_del(&id_priv->listen_list); 775 - 776 - cma_deref_id(id_priv); 777 - wait_for_completion(&id_priv->comp); 778 - 779 - kfree(id_priv); 780 - } 781 - 782 static void cma_cancel_listens(struct rdma_id_private *id_priv) 783 { 784 struct rdma_id_private *dev_id_priv; 785 786 mutex_lock(&lock); 787 list_del(&id_priv->list); 788 789 while (!list_empty(&id_priv->listen_list)) { 790 dev_id_priv = list_entry(id_priv->listen_list.next, 791 struct rdma_id_private, listen_list); 792 - cma_destroy_listen(dev_id_priv); 793 } 794 mutex_unlock(&lock); 795 } ··· 854 cma_deref_id(id_priv); 855 wait_for_completion(&id_priv->comp); 856 857 kfree(id_priv->id.route.path_rec); 858 kfree(id_priv); 859 } ··· 866 { 867 int ret; 868 869 - ret = cma_modify_qp_rtr(&id_priv->id); 870 if (ret) 871 goto reject; 872 873 - ret = cma_modify_qp_rts(&id_priv->id); 874 if (ret) 875 goto reject; 876 ··· 880 881 return 0; 882 reject: 883 - cma_modify_qp_err(&id_priv->id); 884 ib_send_cm_rej(id_priv->cm_id.ib, IB_CM_REJ_CONSUMER_DEFINED, 885 NULL, 0, NULL, 0); 886 return ret; ··· 956 /* ignore event */ 957 goto out; 958 case IB_CM_REJ_RECEIVED: 959 - cma_modify_qp_err(&id_priv->id); 960 event.status = ib_event->param.rej_rcvd.reason; 961 event.event = RDMA_CM_EVENT_REJECTED; 962 event.param.conn.private_data = ib_event->private_data; ··· 1413 1414 cma_attach_to_dev(dev_id_priv, cma_dev); 1415 list_add_tail(&dev_id_priv->listen_list, &id_priv->listen_list); 1416 1417 ret = rdma_listen(id, id_priv->backlog); 1418 if (ret) 1419 - goto err; 1420 - 1421 - return; 1422 - err: 1423 - cma_destroy_listen(dev_id_priv); 1424 } 1425 1426 static void cma_listen_on_all(struct rdma_id_private *id_priv) ··· 2272 sin = (struct sockaddr_in*) &id_priv->id.route.addr.dst_addr; 2273 cm_id->remote_addr = *sin; 2274 2275 - ret = cma_modify_qp_rtr(&id_priv->id); 2276 if (ret) 2277 goto out; 2278 ··· 2339 int qp_attr_mask, ret; 2340 2341 if (id_priv->id.qp) { 2342 - ret = cma_modify_qp_rtr(&id_priv->id); 2343 if (ret) 2344 goto out; 2345 ··· 2378 struct iw_cm_conn_param iw_param; 2379 int ret; 2380 2381 - ret = cma_modify_qp_rtr(&id_priv->id); 2382 if (ret) 2383 return ret; 2384 ··· 2450 2451 return 0; 2452 reject: 2453 - cma_modify_qp_err(id); 2454 rdma_reject(id, NULL, 0); 2455 return ret; 2456 } ··· 2520 2521 switch (rdma_node_get_transport(id->device->node_type)) { 2522 case RDMA_TRANSPORT_IB: 2523 - ret = cma_modify_qp_err(id); 2524 if (ret) 2525 goto out; 2526 /* Initiate or respond to a disconnect. */ ··· 2551 cma_disable_remove(id_priv, CMA_ADDR_RESOLVED)) 2552 return 0; 2553 2554 if (!status && id_priv->id.qp) 2555 status = ib_attach_mcast(id_priv->id.qp, &multicast->rec.mgid, 2556 multicast->rec.mlid); 2557 2558 memset(&event, 0, sizeof event); 2559 event.status = status; ··· 2767 id_priv = list_entry(cma_dev->id_list.next, 2768 struct rdma_id_private, list); 2769 2770 - if (cma_internal_listen(id_priv)) { 2771 - cma_destroy_listen(id_priv); 2772 - continue; 2773 - } 2774 - 2775 list_del_init(&id_priv->list); 2776 atomic_inc(&id_priv->refcount); 2777 mutex_unlock(&lock); 2778 2779 - ret = cma_remove_id_dev(id_priv); 2780 cma_deref_id(id_priv); 2781 if (ret) 2782 rdma_destroy_id(&id_priv->id);
··· 114 115 struct rdma_bind_list *bind_list; 116 struct hlist_node node; 117 + struct list_head list; /* listen_any_list or cma_device.list */ 118 + struct list_head listen_list; /* per device listens */ 119 struct cma_device *cma_dev; 120 struct list_head mc_list; 121 122 + int internal_id; 123 enum cma_state state; 124 spinlock_t lock; 125 + struct mutex qp_mutex; 126 + 127 struct completion comp; 128 atomic_t refcount; 129 wait_queue_head_t wait_remove; ··· 389 id_priv->id.event_handler = event_handler; 390 id_priv->id.ps = ps; 391 spin_lock_init(&id_priv->lock); 392 + mutex_init(&id_priv->qp_mutex); 393 init_completion(&id_priv->comp); 394 atomic_set(&id_priv->refcount, 1); 395 init_waitqueue_head(&id_priv->wait_remove); ··· 474 475 void rdma_destroy_qp(struct rdma_cm_id *id) 476 { 477 + struct rdma_id_private *id_priv; 478 + 479 + id_priv = container_of(id, struct rdma_id_private, id); 480 + mutex_lock(&id_priv->qp_mutex); 481 + ib_destroy_qp(id_priv->id.qp); 482 + id_priv->id.qp = NULL; 483 + mutex_unlock(&id_priv->qp_mutex); 484 } 485 EXPORT_SYMBOL(rdma_destroy_qp); 486 487 + static int cma_modify_qp_rtr(struct rdma_id_private *id_priv) 488 { 489 struct ib_qp_attr qp_attr; 490 int qp_attr_mask, ret; 491 492 + mutex_lock(&id_priv->qp_mutex); 493 + if (!id_priv->id.qp) { 494 + ret = 0; 495 + goto out; 496 + } 497 498 /* Need to update QP attributes from default values. */ 499 qp_attr.qp_state = IB_QPS_INIT; 500 + ret = rdma_init_qp_attr(&id_priv->id, &qp_attr, &qp_attr_mask); 501 if (ret) 502 + goto out; 503 504 + ret = ib_modify_qp(id_priv->id.qp, &qp_attr, qp_attr_mask); 505 if (ret) 506 + goto out; 507 508 qp_attr.qp_state = IB_QPS_RTR; 509 + ret = rdma_init_qp_attr(&id_priv->id, &qp_attr, &qp_attr_mask); 510 if (ret) 511 + goto out; 512 513 + ret = ib_modify_qp(id_priv->id.qp, &qp_attr, qp_attr_mask); 514 + out: 515 + mutex_unlock(&id_priv->qp_mutex); 516 + return ret; 517 } 518 519 + static int cma_modify_qp_rts(struct rdma_id_private *id_priv) 520 { 521 struct ib_qp_attr qp_attr; 522 int qp_attr_mask, ret; 523 524 + mutex_lock(&id_priv->qp_mutex); 525 + if (!id_priv->id.qp) { 526 + ret = 0; 527 + goto out; 528 + } 529 530 qp_attr.qp_state = IB_QPS_RTS; 531 + ret = rdma_init_qp_attr(&id_priv->id, &qp_attr, &qp_attr_mask); 532 if (ret) 533 + goto out; 534 535 + ret = ib_modify_qp(id_priv->id.qp, &qp_attr, qp_attr_mask); 536 + out: 537 + mutex_unlock(&id_priv->qp_mutex); 538 + return ret; 539 } 540 541 + static int cma_modify_qp_err(struct rdma_id_private *id_priv) 542 { 543 struct ib_qp_attr qp_attr; 544 + int ret; 545 546 + mutex_lock(&id_priv->qp_mutex); 547 + if (!id_priv->id.qp) { 548 + ret = 0; 549 + goto out; 550 + } 551 552 qp_attr.qp_state = IB_QPS_ERR; 553 + ret = ib_modify_qp(id_priv->id.qp, &qp_attr, IB_QP_STATE); 554 + out: 555 + mutex_unlock(&id_priv->qp_mutex); 556 + return ret; 557 } 558 559 static int cma_ib_init_qp_attr(struct rdma_id_private *id_priv, ··· 717 } 718 } 719 720 static void cma_cancel_listens(struct rdma_id_private *id_priv) 721 { 722 struct rdma_id_private *dev_id_priv; 723 724 + /* 725 + * Remove from listen_any_list to prevent added devices from spawning 726 + * additional listen requests. 727 + */ 728 mutex_lock(&lock); 729 list_del(&id_priv->list); 730 731 while (!list_empty(&id_priv->listen_list)) { 732 dev_id_priv = list_entry(id_priv->listen_list.next, 733 struct rdma_id_private, listen_list); 734 + /* sync with device removal to avoid duplicate destruction */ 735 + list_del_init(&dev_id_priv->list); 736 + list_del(&dev_id_priv->listen_list); 737 + mutex_unlock(&lock); 738 + 739 + rdma_destroy_id(&dev_id_priv->id); 740 + mutex_lock(&lock); 741 } 742 mutex_unlock(&lock); 743 } ··· 848 cma_deref_id(id_priv); 849 wait_for_completion(&id_priv->comp); 850 851 + if (id_priv->internal_id) 852 + cma_deref_id(id_priv->id.context); 853 + 854 kfree(id_priv->id.route.path_rec); 855 kfree(id_priv); 856 } ··· 857 { 858 int ret; 859 860 + ret = cma_modify_qp_rtr(id_priv); 861 if (ret) 862 goto reject; 863 864 + ret = cma_modify_qp_rts(id_priv); 865 if (ret) 866 goto reject; 867 ··· 871 872 return 0; 873 reject: 874 + cma_modify_qp_err(id_priv); 875 ib_send_cm_rej(id_priv->cm_id.ib, IB_CM_REJ_CONSUMER_DEFINED, 876 NULL, 0, NULL, 0); 877 return ret; ··· 947 /* ignore event */ 948 goto out; 949 case IB_CM_REJ_RECEIVED: 950 + cma_modify_qp_err(id_priv); 951 event.status = ib_event->param.rej_rcvd.reason; 952 event.event = RDMA_CM_EVENT_REJECTED; 953 event.param.conn.private_data = ib_event->private_data; ··· 1404 1405 cma_attach_to_dev(dev_id_priv, cma_dev); 1406 list_add_tail(&dev_id_priv->listen_list, &id_priv->listen_list); 1407 + atomic_inc(&id_priv->refcount); 1408 + dev_id_priv->internal_id = 1; 1409 1410 ret = rdma_listen(id, id_priv->backlog); 1411 if (ret) 1412 + printk(KERN_WARNING "RDMA CMA: cma_listen_on_dev, error %d, " 1413 + "listening on device %s", ret, cma_dev->device->name); 1414 } 1415 1416 static void cma_listen_on_all(struct rdma_id_private *id_priv) ··· 2264 sin = (struct sockaddr_in*) &id_priv->id.route.addr.dst_addr; 2265 cm_id->remote_addr = *sin; 2266 2267 + ret = cma_modify_qp_rtr(id_priv); 2268 if (ret) 2269 goto out; 2270 ··· 2331 int qp_attr_mask, ret; 2332 2333 if (id_priv->id.qp) { 2334 + ret = cma_modify_qp_rtr(id_priv); 2335 if (ret) 2336 goto out; 2337 ··· 2370 struct iw_cm_conn_param iw_param; 2371 int ret; 2372 2373 + ret = cma_modify_qp_rtr(id_priv); 2374 if (ret) 2375 return ret; 2376 ··· 2442 2443 return 0; 2444 reject: 2445 + cma_modify_qp_err(id_priv); 2446 rdma_reject(id, NULL, 0); 2447 return ret; 2448 } ··· 2512 2513 switch (rdma_node_get_transport(id->device->node_type)) { 2514 case RDMA_TRANSPORT_IB: 2515 + ret = cma_modify_qp_err(id_priv); 2516 if (ret) 2517 goto out; 2518 /* Initiate or respond to a disconnect. */ ··· 2543 cma_disable_remove(id_priv, CMA_ADDR_RESOLVED)) 2544 return 0; 2545 2546 + mutex_lock(&id_priv->qp_mutex); 2547 if (!status && id_priv->id.qp) 2548 status = ib_attach_mcast(id_priv->id.qp, &multicast->rec.mgid, 2549 multicast->rec.mlid); 2550 + mutex_unlock(&id_priv->qp_mutex); 2551 2552 memset(&event, 0, sizeof event); 2553 event.status = status; ··· 2757 id_priv = list_entry(cma_dev->id_list.next, 2758 struct rdma_id_private, list); 2759 2760 + list_del(&id_priv->listen_list); 2761 list_del_init(&id_priv->list); 2762 atomic_inc(&id_priv->refcount); 2763 mutex_unlock(&lock); 2764 2765 + ret = id_priv->internal_id ? 1 : cma_remove_id_dev(id_priv); 2766 cma_deref_id(id_priv); 2767 if (ret) 2768 rdma_destroy_id(&id_priv->id);
+6 -2
drivers/infiniband/core/uverbs_cmd.c
··· 147 148 spin_lock(&ib_uverbs_idr_lock); 149 uobj = idr_find(idr, id); 150 - if (uobj) 151 - kref_get(&uobj->ref); 152 spin_unlock(&ib_uverbs_idr_lock); 153 154 return uobj;
··· 147 148 spin_lock(&ib_uverbs_idr_lock); 149 uobj = idr_find(idr, id); 150 + if (uobj) { 151 + if (uobj->context == context) 152 + kref_get(&uobj->ref); 153 + else 154 + uobj = NULL; 155 + } 156 spin_unlock(&ib_uverbs_idr_lock); 157 158 return uobj;
-1
drivers/infiniband/hw/ehca/ehca_classes.h
··· 323 extern int ehca_port_act_time; 324 extern int ehca_use_hp_mr; 325 extern int ehca_scaling_code; 326 - extern int ehca_mr_largepage; 327 328 struct ipzu_queue_resp { 329 u32 qe_size; /* queue entry size */
··· 323 extern int ehca_port_act_time; 324 extern int ehca_use_hp_mr; 325 extern int ehca_scaling_code; 326 327 struct ipzu_queue_resp { 328 u32 qe_size; /* queue entry size */
+1
drivers/infiniband/hw/ehca/ehca_hca.c
··· 77 } 78 79 memset(props, 0, sizeof(struct ib_device_attr)); 80 props->fw_ver = rblock->hw_ver; 81 props->max_mr_size = rblock->max_mr_size; 82 props->vendor_id = rblock->vendor_id >> 8;
··· 77 } 78 79 memset(props, 0, sizeof(struct ib_device_attr)); 80 + props->page_size_cap = shca->hca_cap_mr_pgsize; 81 props->fw_ver = rblock->hw_ver; 82 props->max_mr_size = rblock->max_mr_size; 83 props->vendor_id = rblock->vendor_id >> 8;
+17 -3
drivers/infiniband/hw/ehca/ehca_main.c
··· 65 int ehca_poll_all_eqs = 1; 66 int ehca_static_rate = -1; 67 int ehca_scaling_code = 0; 68 - int ehca_mr_largepage = 0; 69 70 module_param_named(open_aqp1, ehca_open_aqp1, int, S_IRUGO); 71 module_param_named(debug_level, ehca_debug_level, int, S_IRUGO); ··· 260 { HCA_CAP_MINI_QP, "HCA_CAP_MINI_QP" }, 261 }; 262 263 - int ehca_sense_attributes(struct ehca_shca *shca) 264 { 265 int i, ret = 0; 266 u64 h_ret; 267 struct hipz_query_hca *rblock; 268 struct hipz_query_port *port; 269 270 rblock = ehca_alloc_fw_ctrlblock(GFP_KERNEL); 271 if (!rblock) { ··· 336 if (EHCA_BMASK_GET(hca_cap_descr[i].mask, shca->hca_cap)) 337 ehca_gen_dbg(" %s", hca_cap_descr[i].descr); 338 339 - shca->hca_cap_mr_pgsize = rblock->memory_page_size_supported; 340 341 port = (struct hipz_query_port *)rblock; 342 h_ret = hipz_h_query_port(shca->ipz_hca_handle, 1, port); 343 if (h_ret != H_SUCCESS) {
··· 65 int ehca_poll_all_eqs = 1; 66 int ehca_static_rate = -1; 67 int ehca_scaling_code = 0; 68 + int ehca_mr_largepage = 1; 69 70 module_param_named(open_aqp1, ehca_open_aqp1, int, S_IRUGO); 71 module_param_named(debug_level, ehca_debug_level, int, S_IRUGO); ··· 260 { HCA_CAP_MINI_QP, "HCA_CAP_MINI_QP" }, 261 }; 262 263 + static int ehca_sense_attributes(struct ehca_shca *shca) 264 { 265 int i, ret = 0; 266 u64 h_ret; 267 struct hipz_query_hca *rblock; 268 struct hipz_query_port *port; 269 + 270 + static const u32 pgsize_map[] = { 271 + HCA_CAP_MR_PGSIZE_4K, 0x1000, 272 + HCA_CAP_MR_PGSIZE_64K, 0x10000, 273 + HCA_CAP_MR_PGSIZE_1M, 0x100000, 274 + HCA_CAP_MR_PGSIZE_16M, 0x1000000, 275 + }; 276 277 rblock = ehca_alloc_fw_ctrlblock(GFP_KERNEL); 278 if (!rblock) { ··· 329 if (EHCA_BMASK_GET(hca_cap_descr[i].mask, shca->hca_cap)) 330 ehca_gen_dbg(" %s", hca_cap_descr[i].descr); 331 332 + /* translate supported MR page sizes; always support 4K */ 333 + shca->hca_cap_mr_pgsize = EHCA_PAGESIZE; 334 + if (ehca_mr_largepage) { /* support extra sizes only if enabled */ 335 + for (i = 0; i < ARRAY_SIZE(pgsize_map); i += 2) 336 + if (rblock->memory_page_size_supported & pgsize_map[i]) 337 + shca->hca_cap_mr_pgsize |= pgsize_map[i + 1]; 338 + } 339 340 + /* query max MTU from first port -- it's the same for all ports */ 341 port = (struct hipz_query_port *)rblock; 342 h_ret = hipz_h_query_port(shca->ipz_hca_handle, 1, port); 343 if (h_ret != H_SUCCESS) {
+25 -32
drivers/infiniband/hw/ehca/ehca_mrmw.c
··· 72 73 static u32 ehca_encode_hwpage_size(u32 pgsize) 74 { 75 - u32 idx = 0; 76 - pgsize >>= 12; 77 - /* 78 - * map mr page size into hw code: 79 - * 0, 1, 2, 3 for 4K, 64K, 1M, 64M 80 - */ 81 - while (!(pgsize & 1)) { 82 - idx++; 83 - pgsize >>= 4; 84 - } 85 - return idx; 86 } 87 88 static u64 ehca_get_max_hwpage_size(struct ehca_shca *shca) 89 { 90 - if (shca->hca_cap_mr_pgsize & HCA_CAP_MR_PGSIZE_16M) 91 - return EHCA_MR_PGSIZE16M; 92 - return EHCA_MR_PGSIZE4K; 93 } 94 95 static struct ehca_mr *ehca_mr_new(void) ··· 249 pginfo.u.phy.num_phys_buf = num_phys_buf; 250 pginfo.u.phy.phys_buf_array = phys_buf_array; 251 pginfo.next_hwpage = 252 - ((u64)iova_start & ~(hw_pgsize - 1)) / hw_pgsize; 253 254 ret = ehca_reg_mr(shca, e_mr, iova_start, size, mr_access_flags, 255 e_pd, &pginfo, &e_mr->ib.ib_mr.lkey, ··· 286 container_of(pd->device, struct ehca_shca, ib_device); 287 struct ehca_pd *e_pd = container_of(pd, struct ehca_pd, ib_pd); 288 struct ehca_mr_pginfo pginfo; 289 - int ret; 290 u32 num_kpages; 291 u32 num_hwpages; 292 u64 hwpage_size; ··· 341 /* determine number of MR pages */ 342 num_kpages = NUM_CHUNKS((virt % PAGE_SIZE) + length, PAGE_SIZE); 343 /* select proper hw_pgsize */ 344 - if (ehca_mr_largepage && 345 - (shca->hca_cap_mr_pgsize & HCA_CAP_MR_PGSIZE_16M)) { 346 - int page_shift = PAGE_SHIFT; 347 - if (e_mr->umem->hugetlb) { 348 - /* determine page_shift, clamp between 4K and 16M */ 349 - page_shift = (fls64(length - 1) + 3) & ~3; 350 - page_shift = min(max(page_shift, EHCA_MR_PGSHIFT4K), 351 - EHCA_MR_PGSHIFT16M); 352 - } 353 - hwpage_size = 1UL << page_shift; 354 - } else 355 - hwpage_size = EHCA_MR_PGSIZE4K; /* ehca1 only supports 4k */ 356 - ehca_dbg(pd->device, "hwpage_size=%lx", hwpage_size); 357 358 reg_user_mr_fallback: 359 num_hwpages = NUM_CHUNKS((virt % hwpage_size) + length, hwpage_size); ··· 538 pginfo.u.phy.num_phys_buf = num_phys_buf; 539 pginfo.u.phy.phys_buf_array = phys_buf_array; 540 pginfo.next_hwpage = 541 - ((u64)iova_start & ~(hw_pgsize - 1)) / hw_pgsize; 542 } 543 if (mr_rereg_mask & IB_MR_REREG_ACCESS) 544 new_acl = mr_access_flags; ··· 800 ib_fmr = ERR_PTR(-EINVAL); 801 goto alloc_fmr_exit0; 802 } 803 - hw_pgsize = ehca_get_max_hwpage_size(shca); 804 - if ((1 << fmr_attr->page_shift) != hw_pgsize) { 805 ehca_err(pd->device, "unsupported fmr_attr->page_shift=%x", 806 fmr_attr->page_shift); 807 ib_fmr = ERR_PTR(-EINVAL); ··· 818 819 /* register MR on HCA */ 820 memset(&pginfo, 0, sizeof(pginfo)); 821 /* 822 * pginfo.num_hwpages==0, ie register_rpages() will not be called 823 * but deferred to map_phys_fmr()
··· 72 73 static u32 ehca_encode_hwpage_size(u32 pgsize) 74 { 75 + int log = ilog2(pgsize); 76 + WARN_ON(log < 12 || log > 24 || log & 3); 77 + return (log - 12) / 4; 78 } 79 80 static u64 ehca_get_max_hwpage_size(struct ehca_shca *shca) 81 { 82 + return 1UL << ilog2(shca->hca_cap_mr_pgsize); 83 } 84 85 static struct ehca_mr *ehca_mr_new(void) ··· 259 pginfo.u.phy.num_phys_buf = num_phys_buf; 260 pginfo.u.phy.phys_buf_array = phys_buf_array; 261 pginfo.next_hwpage = 262 + ((u64)iova_start & ~PAGE_MASK) / hw_pgsize; 263 264 ret = ehca_reg_mr(shca, e_mr, iova_start, size, mr_access_flags, 265 e_pd, &pginfo, &e_mr->ib.ib_mr.lkey, ··· 296 container_of(pd->device, struct ehca_shca, ib_device); 297 struct ehca_pd *e_pd = container_of(pd, struct ehca_pd, ib_pd); 298 struct ehca_mr_pginfo pginfo; 299 + int ret, page_shift; 300 u32 num_kpages; 301 u32 num_hwpages; 302 u64 hwpage_size; ··· 351 /* determine number of MR pages */ 352 num_kpages = NUM_CHUNKS((virt % PAGE_SIZE) + length, PAGE_SIZE); 353 /* select proper hw_pgsize */ 354 + page_shift = PAGE_SHIFT; 355 + if (e_mr->umem->hugetlb) { 356 + /* determine page_shift, clamp between 4K and 16M */ 357 + page_shift = (fls64(length - 1) + 3) & ~3; 358 + page_shift = min(max(page_shift, EHCA_MR_PGSHIFT4K), 359 + EHCA_MR_PGSHIFT16M); 360 + } 361 + hwpage_size = 1UL << page_shift; 362 + 363 + /* now that we have the desired page size, shift until it's 364 + * supported, too. 4K is always supported, so this terminates. 365 + */ 366 + while (!(hwpage_size & shca->hca_cap_mr_pgsize)) 367 + hwpage_size >>= 4; 368 369 reg_user_mr_fallback: 370 num_hwpages = NUM_CHUNKS((virt % hwpage_size) + length, hwpage_size); ··· 547 pginfo.u.phy.num_phys_buf = num_phys_buf; 548 pginfo.u.phy.phys_buf_array = phys_buf_array; 549 pginfo.next_hwpage = 550 + ((u64)iova_start & ~PAGE_MASK) / hw_pgsize; 551 } 552 if (mr_rereg_mask & IB_MR_REREG_ACCESS) 553 new_acl = mr_access_flags; ··· 809 ib_fmr = ERR_PTR(-EINVAL); 810 goto alloc_fmr_exit0; 811 } 812 + 813 + hw_pgsize = 1 << fmr_attr->page_shift; 814 + if (!(hw_pgsize & shca->hca_cap_mr_pgsize)) { 815 ehca_err(pd->device, "unsupported fmr_attr->page_shift=%x", 816 fmr_attr->page_shift); 817 ib_fmr = ERR_PTR(-EINVAL); ··· 826 827 /* register MR on HCA */ 828 memset(&pginfo, 0, sizeof(pginfo)); 829 + pginfo.hwpage_size = hw_pgsize; 830 /* 831 * pginfo.num_hwpages==0, ie register_rpages() will not be called 832 * but deferred to map_phys_fmr()
+3 -1
drivers/infiniband/hw/ehca/ehca_qp.c
··· 451 has_srq = 1; 452 parms.ext_type = EQPT_SRQBASE; 453 parms.srq_qpn = my_srq->real_qp_num; 454 - parms.srq_token = my_srq->token; 455 } 456 457 if (is_llqp && has_srq) { ··· 581 ehca_err(pd->device, "Invalid number of qp"); 582 goto create_qp_exit1; 583 } 584 585 parms.servicetype = ibqptype2servicetype(qp_type); 586 if (parms.servicetype < 0) {
··· 451 has_srq = 1; 452 parms.ext_type = EQPT_SRQBASE; 453 parms.srq_qpn = my_srq->real_qp_num; 454 } 455 456 if (is_llqp && has_srq) { ··· 582 ehca_err(pd->device, "Invalid number of qp"); 583 goto create_qp_exit1; 584 } 585 + 586 + if (has_srq) 587 + parms.srq_token = my_qp->token; 588 589 parms.servicetype = ibqptype2servicetype(qp_type); 590 if (parms.servicetype < 0) {
+14 -2
drivers/infiniband/hw/mlx4/qp.c
··· 63 u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; 64 }; 65 66 static const __be32 mlx4_ib_opcode[] = { 67 [IB_WR_SEND] = __constant_cpu_to_be32(MLX4_OPCODE_SEND), 68 [IB_WR_SEND_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM), ··· 289 return 0; 290 } 291 292 - static int set_user_sq_size(struct mlx4_ib_qp *qp, 293 struct mlx4_ib_create_qp *ucmd) 294 { 295 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 296 qp->sq.wqe_shift = ucmd->log_sq_stride; 297 ··· 342 343 qp->sq_no_prefetch = ucmd.sq_no_prefetch; 344 345 - err = set_user_sq_size(qp, &ucmd); 346 if (err) 347 goto err; 348
··· 63 u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; 64 }; 65 66 + enum { 67 + MLX4_IB_MIN_SQ_STRIDE = 6 68 + }; 69 + 70 static const __be32 mlx4_ib_opcode[] = { 71 [IB_WR_SEND] = __constant_cpu_to_be32(MLX4_OPCODE_SEND), 72 [IB_WR_SEND_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM), ··· 285 return 0; 286 } 287 288 + static int set_user_sq_size(struct mlx4_ib_dev *dev, 289 + struct mlx4_ib_qp *qp, 290 struct mlx4_ib_create_qp *ucmd) 291 { 292 + /* Sanity check SQ size before proceeding */ 293 + if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || 294 + ucmd->log_sq_stride > 295 + ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 296 + ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 297 + return -EINVAL; 298 + 299 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 300 qp->sq.wqe_shift = ucmd->log_sq_stride; 301 ··· 330 331 qp->sq_no_prefetch = ucmd.sq_no_prefetch; 332 333 + err = set_user_sq_size(dev, qp, &ucmd); 334 if (err) 335 goto err; 336
+19 -34
drivers/infiniband/hw/mthca/mthca_cq.c
··· 204 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq, 205 int incr) 206 { 207 - __be32 doorbell[2]; 208 - 209 if (mthca_is_memfree(dev)) { 210 *cq->set_ci_db = cpu_to_be32(cq->cons_index); 211 wmb(); 212 } else { 213 - doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn); 214 - doorbell[1] = cpu_to_be32(incr - 1); 215 - 216 - mthca_write64(doorbell, 217 dev->kar + MTHCA_CQ_DOORBELL, 218 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 219 /* ··· 726 727 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags) 728 { 729 - __be32 doorbell[2]; 730 731 - doorbell[0] = cpu_to_be32(((flags & IB_CQ_SOLICITED_MASK) == 732 - IB_CQ_SOLICITED ? 733 - MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL : 734 - MTHCA_TAVOR_CQ_DB_REQ_NOT) | 735 - to_mcq(cq)->cqn); 736 - doorbell[1] = (__force __be32) 0xffffffff; 737 - 738 - mthca_write64(doorbell, 739 - to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL, 740 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock)); 741 742 return 0; ··· 740 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 741 { 742 struct mthca_cq *cq = to_mcq(ibcq); 743 - __be32 doorbell[2]; 744 - u32 sn; 745 - __be32 ci; 746 747 - sn = cq->arm_sn & 3; 748 - ci = cpu_to_be32(cq->cons_index); 749 750 - doorbell[0] = ci; 751 - doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) | 752 - ((flags & IB_CQ_SOLICITED_MASK) == 753 - IB_CQ_SOLICITED ? 1 : 2)); 754 - 755 - mthca_write_db_rec(doorbell, cq->arm_db); 756 757 /* 758 * Make sure that the doorbell record in host memory is ··· 757 */ 758 wmb(); 759 760 - doorbell[0] = cpu_to_be32((sn << 28) | 761 - ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 762 - MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL : 763 - MTHCA_ARBEL_CQ_DB_REQ_NOT) | 764 - cq->cqn); 765 - doorbell[1] = ci; 766 767 - mthca_write64(doorbell, 768 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL, 769 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock)); 770
··· 204 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq, 205 int incr) 206 { 207 if (mthca_is_memfree(dev)) { 208 *cq->set_ci_db = cpu_to_be32(cq->cons_index); 209 wmb(); 210 } else { 211 + mthca_write64(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn, incr - 1, 212 dev->kar + MTHCA_CQ_DOORBELL, 213 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 214 /* ··· 731 732 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags) 733 { 734 + u32 dbhi = ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 735 + MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL : 736 + MTHCA_TAVOR_CQ_DB_REQ_NOT) | 737 + to_mcq(cq)->cqn; 738 739 + mthca_write64(dbhi, 0xffffffff, to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL, 740 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock)); 741 742 return 0; ··· 750 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 751 { 752 struct mthca_cq *cq = to_mcq(ibcq); 753 + __be32 db_rec[2]; 754 + u32 dbhi; 755 + u32 sn = cq->arm_sn & 3; 756 757 + db_rec[0] = cpu_to_be32(cq->cons_index); 758 + db_rec[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) | 759 + ((flags & IB_CQ_SOLICITED_MASK) == 760 + IB_CQ_SOLICITED ? 1 : 2)); 761 762 + mthca_write_db_rec(db_rec, cq->arm_db); 763 764 /* 765 * Make sure that the doorbell record in host memory is ··· 770 */ 771 wmb(); 772 773 + dbhi = (sn << 28) | 774 + ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 775 + MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL : 776 + MTHCA_ARBEL_CQ_DB_REQ_NOT) | cq->cqn; 777 778 + mthca_write64(dbhi, cq->cons_index, 779 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL, 780 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock)); 781
+8 -5
drivers/infiniband/hw/mthca/mthca_doorbell.h
··· 58 __raw_writeq((__force u64) val, dest); 59 } 60 61 - static inline void mthca_write64(__be32 val[2], void __iomem *dest, 62 spinlock_t *doorbell_lock) 63 { 64 - __raw_writeq(*(u64 *) val, dest); 65 } 66 67 static inline void mthca_write_db_rec(__be32 val[2], __be32 *db) ··· 87 __raw_writel(((__force u32 *) &val)[1], dest + 4); 88 } 89 90 - static inline void mthca_write64(__be32 val[2], void __iomem *dest, 91 spinlock_t *doorbell_lock) 92 { 93 unsigned long flags; 94 95 spin_lock_irqsave(doorbell_lock, flags); 96 - __raw_writel((__force u32) val[0], dest); 97 - __raw_writel((__force u32) val[1], dest + 4); 98 spin_unlock_irqrestore(doorbell_lock, flags); 99 } 100
··· 58 __raw_writeq((__force u64) val, dest); 59 } 60 61 + static inline void mthca_write64(u32 hi, u32 lo, void __iomem *dest, 62 spinlock_t *doorbell_lock) 63 { 64 + __raw_writeq((__force u64) cpu_to_be64((u64) hi << 32 | lo), dest); 65 } 66 67 static inline void mthca_write_db_rec(__be32 val[2], __be32 *db) ··· 87 __raw_writel(((__force u32 *) &val)[1], dest + 4); 88 } 89 90 + static inline void mthca_write64(u32 hi, u32 lo, void __iomem *dest, 91 spinlock_t *doorbell_lock) 92 { 93 unsigned long flags; 94 95 + hi = (__force u32) cpu_to_be32(hi); 96 + lo = (__force u32) cpu_to_be32(lo); 97 + 98 spin_lock_irqsave(doorbell_lock, flags); 99 + __raw_writel(hi, dest); 100 + __raw_writel(lo, dest + 4); 101 spin_unlock_irqrestore(doorbell_lock, flags); 102 } 103
+3 -18
drivers/infiniband/hw/mthca/mthca_eq.c
··· 173 174 static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) 175 { 176 - __be32 doorbell[2]; 177 - 178 - doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_SET_CI | eq->eqn); 179 - doorbell[1] = cpu_to_be32(ci & (eq->nent - 1)); 180 - 181 /* 182 * This barrier makes sure that all updates to ownership bits 183 * done by set_eqe_hw() hit memory before the consumer index ··· 182 * having set_eqe_hw() overwrite the owner field. 183 */ 184 wmb(); 185 - mthca_write64(doorbell, 186 dev->kar + MTHCA_EQ_DOORBELL, 187 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 188 } ··· 207 208 static inline void tavor_eq_req_not(struct mthca_dev *dev, int eqn) 209 { 210 - __be32 doorbell[2]; 211 - 212 - doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_REQ_NOT | eqn); 213 - doorbell[1] = 0; 214 - 215 - mthca_write64(doorbell, 216 dev->kar + MTHCA_EQ_DOORBELL, 217 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 218 } ··· 220 static inline void disarm_cq(struct mthca_dev *dev, int eqn, int cqn) 221 { 222 if (!mthca_is_memfree(dev)) { 223 - __be32 doorbell[2]; 224 - 225 - doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_DISARM_CQ | eqn); 226 - doorbell[1] = cpu_to_be32(cqn); 227 - 228 - mthca_write64(doorbell, 229 dev->kar + MTHCA_EQ_DOORBELL, 230 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 231 }
··· 173 174 static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) 175 { 176 /* 177 * This barrier makes sure that all updates to ownership bits 178 * done by set_eqe_hw() hit memory before the consumer index ··· 187 * having set_eqe_hw() overwrite the owner field. 188 */ 189 wmb(); 190 + mthca_write64(MTHCA_EQ_DB_SET_CI | eq->eqn, ci & (eq->nent - 1), 191 dev->kar + MTHCA_EQ_DOORBELL, 192 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 193 } ··· 212 213 static inline void tavor_eq_req_not(struct mthca_dev *dev, int eqn) 214 { 215 + mthca_write64(MTHCA_EQ_DB_REQ_NOT | eqn, 0, 216 dev->kar + MTHCA_EQ_DOORBELL, 217 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 218 } ··· 230 static inline void disarm_cq(struct mthca_dev *dev, int eqn, int cqn) 231 { 232 if (!mthca_is_memfree(dev)) { 233 + mthca_write64(MTHCA_EQ_DB_DISARM_CQ | eqn, cqn, 234 dev->kar + MTHCA_EQ_DOORBELL, 235 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 236 }
+15 -30
drivers/infiniband/hw/mthca/mthca_qp.c
··· 1799 1800 out: 1801 if (likely(nreq)) { 1802 - __be32 doorbell[2]; 1803 - 1804 - doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) + 1805 - qp->send_wqe_offset) | f0 | op0); 1806 - doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0); 1807 - 1808 wmb(); 1809 1810 - mthca_write64(doorbell, 1811 dev->kar + MTHCA_SEND_DOORBELL, 1812 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 1813 /* ··· 1825 { 1826 struct mthca_dev *dev = to_mdev(ibqp->device); 1827 struct mthca_qp *qp = to_mqp(ibqp); 1828 - __be32 doorbell[2]; 1829 unsigned long flags; 1830 int err = 0; 1831 int nreq; ··· 1902 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) { 1903 nreq = 0; 1904 1905 - doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0); 1906 - doorbell[1] = cpu_to_be32(qp->qpn << 8); 1907 - 1908 wmb(); 1909 1910 - mthca_write64(doorbell, 1911 - dev->kar + MTHCA_RECEIVE_DOORBELL, 1912 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 1913 1914 qp->rq.next_ind = ind; ··· 1915 1916 out: 1917 if (likely(nreq)) { 1918 - doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0); 1919 - doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq); 1920 - 1921 wmb(); 1922 1923 - mthca_write64(doorbell, 1924 - dev->kar + MTHCA_RECEIVE_DOORBELL, 1925 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 1926 } 1927 ··· 1940 { 1941 struct mthca_dev *dev = to_mdev(ibqp->device); 1942 struct mthca_qp *qp = to_mqp(ibqp); 1943 - __be32 doorbell[2]; 1944 void *wqe; 1945 void *prev_wqe; 1946 unsigned long flags; ··· 1970 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) { 1971 nreq = 0; 1972 1973 - doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) | 1974 - ((qp->sq.head & 0xffff) << 8) | 1975 - f0 | op0); 1976 - doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0); 1977 1978 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB; 1979 ··· 1987 * write MMIO send doorbell. 1988 */ 1989 wmb(); 1990 - mthca_write64(doorbell, 1991 dev->kar + MTHCA_SEND_DOORBELL, 1992 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 1993 } ··· 2142 2143 out: 2144 if (likely(nreq)) { 2145 - doorbell[0] = cpu_to_be32((nreq << 24) | 2146 - ((qp->sq.head & 0xffff) << 8) | 2147 - f0 | op0); 2148 - doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0); 2149 2150 qp->sq.head += nreq; 2151 ··· 2158 * write MMIO send doorbell. 2159 */ 2160 wmb(); 2161 - mthca_write64(doorbell, 2162 - dev->kar + MTHCA_SEND_DOORBELL, 2163 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 2164 } 2165
··· 1799 1800 out: 1801 if (likely(nreq)) { 1802 wmb(); 1803 1804 + mthca_write64(((qp->sq.next_ind << qp->sq.wqe_shift) + 1805 + qp->send_wqe_offset) | f0 | op0, 1806 + (qp->qpn << 8) | size0, 1807 dev->kar + MTHCA_SEND_DOORBELL, 1808 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 1809 /* ··· 1829 { 1830 struct mthca_dev *dev = to_mdev(ibqp->device); 1831 struct mthca_qp *qp = to_mqp(ibqp); 1832 unsigned long flags; 1833 int err = 0; 1834 int nreq; ··· 1907 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) { 1908 nreq = 0; 1909 1910 wmb(); 1911 1912 + mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0, 1913 + qp->qpn << 8, dev->kar + MTHCA_RECEIVE_DOORBELL, 1914 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 1915 1916 qp->rq.next_ind = ind; ··· 1923 1924 out: 1925 if (likely(nreq)) { 1926 wmb(); 1927 1928 + mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0, 1929 + qp->qpn << 8 | nreq, dev->kar + MTHCA_RECEIVE_DOORBELL, 1930 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 1931 } 1932 ··· 1951 { 1952 struct mthca_dev *dev = to_mdev(ibqp->device); 1953 struct mthca_qp *qp = to_mqp(ibqp); 1954 + u32 dbhi; 1955 void *wqe; 1956 void *prev_wqe; 1957 unsigned long flags; ··· 1981 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) { 1982 nreq = 0; 1983 1984 + dbhi = (MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) | 1985 + ((qp->sq.head & 0xffff) << 8) | f0 | op0; 1986 1987 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB; 1988 ··· 2000 * write MMIO send doorbell. 2001 */ 2002 wmb(); 2003 + 2004 + mthca_write64(dbhi, (qp->qpn << 8) | size0, 2005 dev->kar + MTHCA_SEND_DOORBELL, 2006 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 2007 } ··· 2154 2155 out: 2156 if (likely(nreq)) { 2157 + dbhi = (nreq << 24) | ((qp->sq.head & 0xffff) << 8) | f0 | op0; 2158 2159 qp->sq.head += nreq; 2160 ··· 2173 * write MMIO send doorbell. 2174 */ 2175 wmb(); 2176 + 2177 + mthca_write64(dbhi, (qp->qpn << 8) | size0, dev->kar + MTHCA_SEND_DOORBELL, 2178 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 2179 } 2180
+2 -9
drivers/infiniband/hw/mthca/mthca_srq.c
··· 491 { 492 struct mthca_dev *dev = to_mdev(ibsrq->device); 493 struct mthca_srq *srq = to_msrq(ibsrq); 494 - __be32 doorbell[2]; 495 unsigned long flags; 496 int err = 0; 497 int first_ind; ··· 562 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) { 563 nreq = 0; 564 565 - doorbell[0] = cpu_to_be32(first_ind << srq->wqe_shift); 566 - doorbell[1] = cpu_to_be32(srq->srqn << 8); 567 - 568 /* 569 * Make sure that descriptors are written 570 * before doorbell is rung. 571 */ 572 wmb(); 573 574 - mthca_write64(doorbell, 575 dev->kar + MTHCA_RECEIVE_DOORBELL, 576 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 577 ··· 577 } 578 579 if (likely(nreq)) { 580 - doorbell[0] = cpu_to_be32(first_ind << srq->wqe_shift); 581 - doorbell[1] = cpu_to_be32((srq->srqn << 8) | nreq); 582 - 583 /* 584 * Make sure that descriptors are written before 585 * doorbell is rung. 586 */ 587 wmb(); 588 589 - mthca_write64(doorbell, 590 dev->kar + MTHCA_RECEIVE_DOORBELL, 591 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 592 }
··· 491 { 492 struct mthca_dev *dev = to_mdev(ibsrq->device); 493 struct mthca_srq *srq = to_msrq(ibsrq); 494 unsigned long flags; 495 int err = 0; 496 int first_ind; ··· 563 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) { 564 nreq = 0; 565 566 /* 567 * Make sure that descriptors are written 568 * before doorbell is rung. 569 */ 570 wmb(); 571 572 + mthca_write64(first_ind << srq->wqe_shift, srq->srqn << 8, 573 dev->kar + MTHCA_RECEIVE_DOORBELL, 574 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 575 ··· 581 } 582 583 if (likely(nreq)) { 584 /* 585 * Make sure that descriptors are written before 586 * doorbell is rung. 587 */ 588 wmb(); 589 590 + mthca_write64(first_ind << srq->wqe_shift, (srq->srqn << 8) | nreq, 591 dev->kar + MTHCA_RECEIVE_DOORBELL, 592 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 593 }
+9 -6
drivers/infiniband/ulp/ipoib/ipoib.h
··· 84 IPOIB_MCAST_RUN = 6, 85 IPOIB_STOP_REAPER = 7, 86 IPOIB_MCAST_STARTED = 8, 87 - IPOIB_FLAG_NETIF_STOPPED = 9, 88 - IPOIB_FLAG_ADMIN_CM = 10, 89 - IPOIB_FLAG_UMCAST = 11, 90 91 IPOIB_MAX_BACKOFF_SECONDS = 16, 92 ··· 97 98 #define IPOIB_OP_RECV (1ul << 31) 99 #ifdef CONFIG_INFINIBAND_IPOIB_CM 100 - #define IPOIB_CM_OP_SRQ (1ul << 30) 101 #else 102 - #define IPOIB_CM_OP_SRQ (0) 103 #endif 104 105 /* structs */ ··· 196 197 struct ipoib_cm_tx { 198 struct ib_cm_id *id; 199 - struct ib_cq *cq; 200 struct ib_qp *qp; 201 struct list_head list; 202 struct net_device *dev; ··· 292 unsigned tx_tail; 293 struct ib_sge tx_sge; 294 struct ib_send_wr tx_wr; 295 296 struct ib_wc ibwc[IPOIB_NUM_WC]; 297 ··· 503 void ipoib_cm_skb_too_long(struct net_device* dev, struct sk_buff *skb, 504 unsigned int mtu); 505 void ipoib_cm_handle_rx_wc(struct net_device *dev, struct ib_wc *wc); 506 #else 507 508 struct ipoib_cm_tx; ··· 592 { 593 } 594 595 #endif 596 597 #ifdef CONFIG_INFINIBAND_IPOIB_DEBUG
··· 84 IPOIB_MCAST_RUN = 6, 85 IPOIB_STOP_REAPER = 7, 86 IPOIB_MCAST_STARTED = 8, 87 + IPOIB_FLAG_ADMIN_CM = 9, 88 + IPOIB_FLAG_UMCAST = 10, 89 90 IPOIB_MAX_BACKOFF_SECONDS = 16, 91 ··· 98 99 #define IPOIB_OP_RECV (1ul << 31) 100 #ifdef CONFIG_INFINIBAND_IPOIB_CM 101 + #define IPOIB_OP_CM (1ul << 30) 102 #else 103 + #define IPOIB_OP_CM (0) 104 #endif 105 106 /* structs */ ··· 197 198 struct ipoib_cm_tx { 199 struct ib_cm_id *id; 200 struct ib_qp *qp; 201 struct list_head list; 202 struct net_device *dev; ··· 294 unsigned tx_tail; 295 struct ib_sge tx_sge; 296 struct ib_send_wr tx_wr; 297 + unsigned tx_outstanding; 298 299 struct ib_wc ibwc[IPOIB_NUM_WC]; 300 ··· 504 void ipoib_cm_skb_too_long(struct net_device* dev, struct sk_buff *skb, 505 unsigned int mtu); 506 void ipoib_cm_handle_rx_wc(struct net_device *dev, struct ib_wc *wc); 507 + void ipoib_cm_handle_tx_wc(struct net_device *dev, struct ib_wc *wc); 508 #else 509 510 struct ipoib_cm_tx; ··· 592 { 593 } 594 595 + static inline void ipoib_cm_handle_tx_wc(struct net_device *dev, struct ib_wc *wc) 596 + { 597 + } 598 #endif 599 600 #ifdef CONFIG_INFINIBAND_IPOIB_DEBUG
+49 -71
drivers/infiniband/ulp/ipoib/ipoib_cm.c
··· 87 struct ib_recv_wr *bad_wr; 88 int i, ret; 89 90 - priv->cm.rx_wr.wr_id = id | IPOIB_CM_OP_SRQ; 91 92 for (i = 0; i < IPOIB_CM_RX_SG; ++i) 93 priv->cm.rx_sge[i].addr = priv->cm.srq_ring[id].mapping[i]; ··· 401 void ipoib_cm_handle_rx_wc(struct net_device *dev, struct ib_wc *wc) 402 { 403 struct ipoib_dev_priv *priv = netdev_priv(dev); 404 - unsigned int wr_id = wc->wr_id & ~IPOIB_CM_OP_SRQ; 405 struct sk_buff *skb, *newskb; 406 struct ipoib_cm_rx *p; 407 unsigned long flags; ··· 412 wr_id, wc->status); 413 414 if (unlikely(wr_id >= ipoib_recvq_size)) { 415 - if (wr_id == (IPOIB_CM_RX_DRAIN_WRID & ~IPOIB_CM_OP_SRQ)) { 416 spin_lock_irqsave(&priv->lock, flags); 417 list_splice_init(&priv->cm.rx_drain_list, &priv->cm.rx_reap_list); 418 ipoib_cm_start_rx_drain(priv); ··· 434 goto repost; 435 } 436 437 - if (!likely(wr_id & IPOIB_CM_RX_UPDATE_MASK)) { 438 p = wc->qp->qp_context; 439 if (p && time_after_eq(jiffies, p->jiffies + IPOIB_CM_RX_UPDATE_TIME)) { 440 spin_lock_irqsave(&priv->lock, flags); ··· 498 priv->tx_sge.addr = addr; 499 priv->tx_sge.length = len; 500 501 - priv->tx_wr.wr_id = wr_id; 502 503 return ib_post_send(tx->qp, &priv->tx_wr, &bad_wr); 504 } ··· 549 dev->trans_start = jiffies; 550 ++tx->tx_head; 551 552 - if (tx->tx_head - tx->tx_tail == ipoib_sendq_size) { 553 ipoib_dbg(priv, "TX ring 0x%x full, stopping kernel net queue\n", 554 tx->qp->qp_num); 555 netif_stop_queue(dev); 556 - set_bit(IPOIB_FLAG_NETIF_STOPPED, &tx->flags); 557 } 558 } 559 } 560 561 - static void ipoib_cm_handle_tx_wc(struct net_device *dev, struct ipoib_cm_tx *tx, 562 - struct ib_wc *wc) 563 { 564 struct ipoib_dev_priv *priv = netdev_priv(dev); 565 - unsigned int wr_id = wc->wr_id; 566 struct ipoib_tx_buf *tx_req; 567 unsigned long flags; 568 ··· 586 587 spin_lock_irqsave(&priv->tx_lock, flags); 588 ++tx->tx_tail; 589 - if (unlikely(test_bit(IPOIB_FLAG_NETIF_STOPPED, &tx->flags)) && 590 - tx->tx_head - tx->tx_tail <= ipoib_sendq_size >> 1) { 591 - clear_bit(IPOIB_FLAG_NETIF_STOPPED, &tx->flags); 592 netif_wake_queue(dev); 593 - } 594 595 if (wc->status != IB_WC_SUCCESS && 596 wc->status != IB_WC_WR_FLUSH_ERR) { ··· 612 tx->neigh = NULL; 613 } 614 615 - /* queue would be re-started anyway when TX is destroyed, 616 - * but it makes sense to do it ASAP here. */ 617 - if (test_and_clear_bit(IPOIB_FLAG_NETIF_STOPPED, &tx->flags)) 618 - netif_wake_queue(dev); 619 - 620 if (test_and_clear_bit(IPOIB_FLAG_INITIALIZED, &tx->flags)) { 621 list_move(&tx->list, &priv->cm.reap_list); 622 queue_work(ipoib_workqueue, &priv->cm.reap_task); ··· 623 } 624 625 spin_unlock_irqrestore(&priv->tx_lock, flags); 626 - } 627 - 628 - static void ipoib_cm_tx_completion(struct ib_cq *cq, void *tx_ptr) 629 - { 630 - struct ipoib_cm_tx *tx = tx_ptr; 631 - int n, i; 632 - 633 - ib_req_notify_cq(cq, IB_CQ_NEXT_COMP); 634 - do { 635 - n = ib_poll_cq(cq, IPOIB_NUM_WC, tx->ibwc); 636 - for (i = 0; i < n; ++i) 637 - ipoib_cm_handle_tx_wc(tx->dev, tx, tx->ibwc + i); 638 - } while (n == IPOIB_NUM_WC); 639 } 640 641 int ipoib_cm_dev_open(struct net_device *dev) ··· 787 return 0; 788 } 789 790 - static struct ib_qp *ipoib_cm_create_tx_qp(struct net_device *dev, struct ib_cq *cq) 791 { 792 struct ipoib_dev_priv *priv = netdev_priv(dev); 793 struct ib_qp_init_attr attr = { 794 - .send_cq = cq, 795 .recv_cq = priv->cq, 796 .srq = priv->cm.srq, 797 .cap.max_send_wr = ipoib_sendq_size, 798 .cap.max_send_sge = 1, 799 .sq_sig_type = IB_SIGNAL_ALL_WR, 800 .qp_type = IB_QPT_RC, 801 }; 802 803 return ib_create_qp(priv->pd, &attr); ··· 880 goto err_tx; 881 } 882 883 - p->cq = ib_create_cq(priv->ca, ipoib_cm_tx_completion, NULL, p, 884 - ipoib_sendq_size + 1, 0); 885 - if (IS_ERR(p->cq)) { 886 - ret = PTR_ERR(p->cq); 887 - ipoib_warn(priv, "failed to allocate tx cq: %d\n", ret); 888 - goto err_cq; 889 - } 890 - 891 - ret = ib_req_notify_cq(p->cq, IB_CQ_NEXT_COMP); 892 - if (ret) { 893 - ipoib_warn(priv, "failed to request completion notification: %d\n", ret); 894 - goto err_req_notify; 895 - } 896 - 897 - p->qp = ipoib_cm_create_tx_qp(p->dev, p->cq); 898 if (IS_ERR(p->qp)) { 899 ret = PTR_ERR(p->qp); 900 ipoib_warn(priv, "failed to allocate tx qp: %d\n", ret); ··· 917 err_id: 918 p->id = NULL; 919 ib_destroy_qp(p->qp); 920 - err_req_notify: 921 err_qp: 922 p->qp = NULL; 923 - ib_destroy_cq(p->cq); 924 - err_cq: 925 - p->cq = NULL; 926 err_tx: 927 return ret; 928 } ··· 927 { 928 struct ipoib_dev_priv *priv = netdev_priv(p->dev); 929 struct ipoib_tx_buf *tx_req; 930 931 ipoib_dbg(priv, "Destroy active connection 0x%x head 0x%x tail 0x%x\n", 932 p->qp ? p->qp->qp_num : 0, p->tx_head, p->tx_tail); ··· 936 if (p->id) 937 ib_destroy_cm_id(p->id); 938 939 if (p->qp) 940 ib_destroy_qp(p->qp); 941 942 - if (p->cq) 943 - ib_destroy_cq(p->cq); 944 - 945 - if (test_bit(IPOIB_FLAG_NETIF_STOPPED, &p->flags)) 946 - netif_wake_queue(p->dev); 947 - 948 - if (p->tx_ring) { 949 - while ((int) p->tx_tail - (int) p->tx_head < 0) { 950 - tx_req = &p->tx_ring[p->tx_tail & (ipoib_sendq_size - 1)]; 951 - ib_dma_unmap_single(priv->ca, tx_req->mapping, tx_req->skb->len, 952 - DMA_TO_DEVICE); 953 - dev_kfree_skb_any(tx_req->skb); 954 - ++p->tx_tail; 955 - } 956 - 957 - kfree(p->tx_ring); 958 - } 959 - 960 kfree(p); 961 } 962
··· 87 struct ib_recv_wr *bad_wr; 88 int i, ret; 89 90 + priv->cm.rx_wr.wr_id = id | IPOIB_OP_CM | IPOIB_OP_RECV; 91 92 for (i = 0; i < IPOIB_CM_RX_SG; ++i) 93 priv->cm.rx_sge[i].addr = priv->cm.srq_ring[id].mapping[i]; ··· 401 void ipoib_cm_handle_rx_wc(struct net_device *dev, struct ib_wc *wc) 402 { 403 struct ipoib_dev_priv *priv = netdev_priv(dev); 404 + unsigned int wr_id = wc->wr_id & ~(IPOIB_OP_CM | IPOIB_OP_RECV); 405 struct sk_buff *skb, *newskb; 406 struct ipoib_cm_rx *p; 407 unsigned long flags; ··· 412 wr_id, wc->status); 413 414 if (unlikely(wr_id >= ipoib_recvq_size)) { 415 + if (wr_id == (IPOIB_CM_RX_DRAIN_WRID & ~(IPOIB_OP_CM | IPOIB_OP_RECV))) { 416 spin_lock_irqsave(&priv->lock, flags); 417 list_splice_init(&priv->cm.rx_drain_list, &priv->cm.rx_reap_list); 418 ipoib_cm_start_rx_drain(priv); ··· 434 goto repost; 435 } 436 437 + if (unlikely(!(wr_id & IPOIB_CM_RX_UPDATE_MASK))) { 438 p = wc->qp->qp_context; 439 if (p && time_after_eq(jiffies, p->jiffies + IPOIB_CM_RX_UPDATE_TIME)) { 440 spin_lock_irqsave(&priv->lock, flags); ··· 498 priv->tx_sge.addr = addr; 499 priv->tx_sge.length = len; 500 501 + priv->tx_wr.wr_id = wr_id | IPOIB_OP_CM; 502 503 return ib_post_send(tx->qp, &priv->tx_wr, &bad_wr); 504 } ··· 549 dev->trans_start = jiffies; 550 ++tx->tx_head; 551 552 + if (++priv->tx_outstanding == ipoib_sendq_size) { 553 ipoib_dbg(priv, "TX ring 0x%x full, stopping kernel net queue\n", 554 tx->qp->qp_num); 555 netif_stop_queue(dev); 556 } 557 } 558 } 559 560 + void ipoib_cm_handle_tx_wc(struct net_device *dev, struct ib_wc *wc) 561 { 562 struct ipoib_dev_priv *priv = netdev_priv(dev); 563 + struct ipoib_cm_tx *tx = wc->qp->qp_context; 564 + unsigned int wr_id = wc->wr_id & ~IPOIB_OP_CM; 565 struct ipoib_tx_buf *tx_req; 566 unsigned long flags; 567 ··· 587 588 spin_lock_irqsave(&priv->tx_lock, flags); 589 ++tx->tx_tail; 590 + if (unlikely(--priv->tx_outstanding == ipoib_sendq_size >> 1) && 591 + netif_queue_stopped(dev) && 592 + test_bit(IPOIB_FLAG_ADMIN_UP, &priv->flags)) 593 netif_wake_queue(dev); 594 595 if (wc->status != IB_WC_SUCCESS && 596 wc->status != IB_WC_WR_FLUSH_ERR) { ··· 614 tx->neigh = NULL; 615 } 616 617 if (test_and_clear_bit(IPOIB_FLAG_INITIALIZED, &tx->flags)) { 618 list_move(&tx->list, &priv->cm.reap_list); 619 queue_work(ipoib_workqueue, &priv->cm.reap_task); ··· 630 } 631 632 spin_unlock_irqrestore(&priv->tx_lock, flags); 633 } 634 635 int ipoib_cm_dev_open(struct net_device *dev) ··· 807 return 0; 808 } 809 810 + static struct ib_qp *ipoib_cm_create_tx_qp(struct net_device *dev, struct ipoib_cm_tx *tx) 811 { 812 struct ipoib_dev_priv *priv = netdev_priv(dev); 813 struct ib_qp_init_attr attr = { 814 + .send_cq = priv->cq, 815 .recv_cq = priv->cq, 816 .srq = priv->cm.srq, 817 .cap.max_send_wr = ipoib_sendq_size, 818 .cap.max_send_sge = 1, 819 .sq_sig_type = IB_SIGNAL_ALL_WR, 820 .qp_type = IB_QPT_RC, 821 + .qp_context = tx 822 }; 823 824 return ib_create_qp(priv->pd, &attr); ··· 899 goto err_tx; 900 } 901 902 + p->qp = ipoib_cm_create_tx_qp(p->dev, p); 903 if (IS_ERR(p->qp)) { 904 ret = PTR_ERR(p->qp); 905 ipoib_warn(priv, "failed to allocate tx qp: %d\n", ret); ··· 950 err_id: 951 p->id = NULL; 952 ib_destroy_qp(p->qp); 953 err_qp: 954 p->qp = NULL; 955 err_tx: 956 return ret; 957 } ··· 964 { 965 struct ipoib_dev_priv *priv = netdev_priv(p->dev); 966 struct ipoib_tx_buf *tx_req; 967 + unsigned long flags; 968 + unsigned long begin; 969 970 ipoib_dbg(priv, "Destroy active connection 0x%x head 0x%x tail 0x%x\n", 971 p->qp ? p->qp->qp_num : 0, p->tx_head, p->tx_tail); ··· 971 if (p->id) 972 ib_destroy_cm_id(p->id); 973 974 + if (p->tx_ring) { 975 + /* Wait for all sends to complete */ 976 + begin = jiffies; 977 + while ((int) p->tx_tail - (int) p->tx_head < 0) { 978 + if (time_after(jiffies, begin + 5 * HZ)) { 979 + ipoib_warn(priv, "timing out; %d sends not completed\n", 980 + p->tx_head - p->tx_tail); 981 + goto timeout; 982 + } 983 + 984 + msleep(1); 985 + } 986 + } 987 + 988 + timeout: 989 + 990 + while ((int) p->tx_tail - (int) p->tx_head < 0) { 991 + tx_req = &p->tx_ring[p->tx_tail & (ipoib_sendq_size - 1)]; 992 + ib_dma_unmap_single(priv->ca, tx_req->mapping, tx_req->skb->len, 993 + DMA_TO_DEVICE); 994 + dev_kfree_skb_any(tx_req->skb); 995 + ++p->tx_tail; 996 + spin_lock_irqsave(&priv->tx_lock, flags); 997 + if (unlikely(--priv->tx_outstanding == ipoib_sendq_size >> 1) && 998 + netif_queue_stopped(p->dev) && 999 + test_bit(IPOIB_FLAG_ADMIN_UP, &priv->flags)) 1000 + netif_wake_queue(p->dev); 1001 + spin_unlock_irqrestore(&priv->tx_lock, flags); 1002 + } 1003 + 1004 if (p->qp) 1005 ib_destroy_qp(p->qp); 1006 1007 + kfree(p->tx_ring); 1008 kfree(p); 1009 } 1010
+31 -21
drivers/infiniband/ulp/ipoib/ipoib_ib.c
··· 267 268 spin_lock_irqsave(&priv->tx_lock, flags); 269 ++priv->tx_tail; 270 - if (unlikely(test_bit(IPOIB_FLAG_NETIF_STOPPED, &priv->flags)) && 271 - priv->tx_head - priv->tx_tail <= ipoib_sendq_size >> 1) { 272 - clear_bit(IPOIB_FLAG_NETIF_STOPPED, &priv->flags); 273 netif_wake_queue(dev); 274 - } 275 spin_unlock_irqrestore(&priv->tx_lock, flags); 276 277 if (wc->status != IB_WC_SUCCESS && ··· 300 for (i = 0; i < n; i++) { 301 struct ib_wc *wc = priv->ibwc + i; 302 303 - if (wc->wr_id & IPOIB_CM_OP_SRQ) { 304 ++done; 305 - ipoib_cm_handle_rx_wc(dev, wc); 306 - } else if (wc->wr_id & IPOIB_OP_RECV) { 307 - ++done; 308 - ipoib_ib_handle_rx_wc(dev, wc); 309 - } else 310 - ipoib_ib_handle_tx_wc(dev, wc); 311 } 312 313 if (n != t) ··· 404 address->last_send = priv->tx_head; 405 ++priv->tx_head; 406 407 - if (priv->tx_head - priv->tx_tail == ipoib_sendq_size) { 408 ipoib_dbg(priv, "TX ring full, stopping kernel net queue\n"); 409 netif_stop_queue(dev); 410 - set_bit(IPOIB_FLAG_NETIF_STOPPED, &priv->flags); 411 } 412 } 413 } ··· 438 __ipoib_reap_ah(dev); 439 440 if (!test_bit(IPOIB_STOP_REAPER, &priv->flags)) 441 - queue_delayed_work(ipoib_workqueue, &priv->ah_reap_task, HZ); 442 } 443 444 int ipoib_ib_dev_open(struct net_device *dev) ··· 475 } 476 477 clear_bit(IPOIB_STOP_REAPER, &priv->flags); 478 - queue_delayed_work(ipoib_workqueue, &priv->ah_reap_task, HZ); 479 480 set_bit(IPOIB_FLAG_INITIALIZED, &priv->flags); 481 ··· 565 if (priv->ibwc[i].status == IB_WC_SUCCESS) 566 priv->ibwc[i].status = IB_WC_WR_FLUSH_ERR; 567 568 - if (priv->ibwc[i].wr_id & IPOIB_CM_OP_SRQ) 569 - ipoib_cm_handle_rx_wc(dev, priv->ibwc + i); 570 - else if (priv->ibwc[i].wr_id & IPOIB_OP_RECV) 571 - ipoib_ib_handle_rx_wc(dev, priv->ibwc + i); 572 - else 573 - ipoib_ib_handle_tx_wc(dev, priv->ibwc + i); 574 } 575 } while (n == IPOIB_NUM_WC); 576 } ··· 621 DMA_TO_DEVICE); 622 dev_kfree_skb_any(tx_req->skb); 623 ++priv->tx_tail; 624 } 625 626 for (i = 0; i < ipoib_recvq_size; ++i) {
··· 267 268 spin_lock_irqsave(&priv->tx_lock, flags); 269 ++priv->tx_tail; 270 + if (unlikely(--priv->tx_outstanding == ipoib_sendq_size >> 1) && 271 + netif_queue_stopped(dev) && 272 + test_bit(IPOIB_FLAG_ADMIN_UP, &priv->flags)) 273 netif_wake_queue(dev); 274 spin_unlock_irqrestore(&priv->tx_lock, flags); 275 276 if (wc->status != IB_WC_SUCCESS && ··· 301 for (i = 0; i < n; i++) { 302 struct ib_wc *wc = priv->ibwc + i; 303 304 + if (wc->wr_id & IPOIB_OP_RECV) { 305 ++done; 306 + if (wc->wr_id & IPOIB_OP_CM) 307 + ipoib_cm_handle_rx_wc(dev, wc); 308 + else 309 + ipoib_ib_handle_rx_wc(dev, wc); 310 + } else { 311 + if (wc->wr_id & IPOIB_OP_CM) 312 + ipoib_cm_handle_tx_wc(dev, wc); 313 + else 314 + ipoib_ib_handle_tx_wc(dev, wc); 315 + } 316 } 317 318 if (n != t) ··· 401 address->last_send = priv->tx_head; 402 ++priv->tx_head; 403 404 + if (++priv->tx_outstanding == ipoib_sendq_size) { 405 ipoib_dbg(priv, "TX ring full, stopping kernel net queue\n"); 406 netif_stop_queue(dev); 407 } 408 } 409 } ··· 436 __ipoib_reap_ah(dev); 437 438 if (!test_bit(IPOIB_STOP_REAPER, &priv->flags)) 439 + queue_delayed_work(ipoib_workqueue, &priv->ah_reap_task, 440 + round_jiffies_relative(HZ)); 441 } 442 443 int ipoib_ib_dev_open(struct net_device *dev) ··· 472 } 473 474 clear_bit(IPOIB_STOP_REAPER, &priv->flags); 475 + queue_delayed_work(ipoib_workqueue, &priv->ah_reap_task, 476 + round_jiffies_relative(HZ)); 477 478 set_bit(IPOIB_FLAG_INITIALIZED, &priv->flags); 479 ··· 561 if (priv->ibwc[i].status == IB_WC_SUCCESS) 562 priv->ibwc[i].status = IB_WC_WR_FLUSH_ERR; 563 564 + if (priv->ibwc[i].wr_id & IPOIB_OP_RECV) { 565 + if (priv->ibwc[i].wr_id & IPOIB_OP_CM) 566 + ipoib_cm_handle_rx_wc(dev, priv->ibwc + i); 567 + else 568 + ipoib_ib_handle_rx_wc(dev, priv->ibwc + i); 569 + } else { 570 + if (priv->ibwc[i].wr_id & IPOIB_OP_CM) 571 + ipoib_cm_handle_tx_wc(dev, priv->ibwc + i); 572 + else 573 + ipoib_ib_handle_tx_wc(dev, priv->ibwc + i); 574 + } 575 } 576 } while (n == IPOIB_NUM_WC); 577 } ··· 612 DMA_TO_DEVICE); 613 dev_kfree_skb_any(tx_req->skb); 614 ++priv->tx_tail; 615 + --priv->tx_outstanding; 616 } 617 618 for (i = 0; i < ipoib_recvq_size; ++i) {
+1 -3
drivers/infiniband/ulp/ipoib/ipoib_main.c
··· 148 149 netif_stop_queue(dev); 150 151 - clear_bit(IPOIB_FLAG_NETIF_STOPPED, &priv->flags); 152 - 153 /* 154 * Now flush workqueue to make sure a scheduled task doesn't 155 * bring our internal state back up. ··· 900 goto out_rx_ring_cleanup; 901 } 902 903 - /* priv->tx_head & tx_tail are already 0 */ 904 905 if (ipoib_ib_dev_init(dev, ca, port)) 906 goto out_tx_ring_cleanup;
··· 148 149 netif_stop_queue(dev); 150 151 /* 152 * Now flush workqueue to make sure a scheduled task doesn't 153 * bring our internal state back up. ··· 902 goto out_rx_ring_cleanup; 903 } 904 905 + /* priv->tx_head, tx_tail & tx_outstanding are already 0 */ 906 907 if (ipoib_ib_dev_init(dev, ca, port)) 908 goto out_tx_ring_cleanup;
+1 -1
drivers/net/mlx4/fw.c
··· 736 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET); 737 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 738 739 - err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 1000); 740 741 if (err) 742 mlx4_err(dev, "INIT_HCA returns %d\n", err);
··· 736 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET); 737 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 738 739 + err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000); 740 741 if (err) 742 mlx4_err(dev, "INIT_HCA returns %d\n", err);
-11
include/linux/mlx4/doorbell.h
··· 52 #define MLX4_INIT_DOORBELL_LOCK(ptr) do { } while (0) 53 #define MLX4_GET_DOORBELL_LOCK(ptr) (NULL) 54 55 - static inline void mlx4_write64_raw(__be64 val, void __iomem *dest) 56 - { 57 - __raw_writeq((__force u64) val, dest); 58 - } 59 - 60 static inline void mlx4_write64(__be32 val[2], void __iomem *dest, 61 spinlock_t *doorbell_lock) 62 { ··· 69 #define MLX4_DECLARE_DOORBELL_LOCK(name) spinlock_t name; 70 #define MLX4_INIT_DOORBELL_LOCK(ptr) spin_lock_init(ptr) 71 #define MLX4_GET_DOORBELL_LOCK(ptr) (ptr) 72 - 73 - static inline void mlx4_write64_raw(__be64 val, void __iomem *dest) 74 - { 75 - __raw_writel(((__force u32 *) &val)[0], dest); 76 - __raw_writel(((__force u32 *) &val)[1], dest + 4); 77 - } 78 79 static inline void mlx4_write64(__be32 val[2], void __iomem *dest, 80 spinlock_t *doorbell_lock)
··· 52 #define MLX4_INIT_DOORBELL_LOCK(ptr) do { } while (0) 53 #define MLX4_GET_DOORBELL_LOCK(ptr) (NULL) 54 55 static inline void mlx4_write64(__be32 val[2], void __iomem *dest, 56 spinlock_t *doorbell_lock) 57 { ··· 74 #define MLX4_DECLARE_DOORBELL_LOCK(name) spinlock_t name; 75 #define MLX4_INIT_DOORBELL_LOCK(ptr) spin_lock_init(ptr) 76 #define MLX4_GET_DOORBELL_LOCK(ptr) (ptr) 77 78 static inline void mlx4_write64(__be32 val[2], void __iomem *dest, 79 spinlock_t *doorbell_lock)