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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: usb: Convert Allwinner USB PHY controller to a schema
The Allwinner SoCs have a USB PHY controller that is supported in Linux,
with a matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Rob Herring <robh@kernel.org>
authored by
Maxime Ripard
and committed by
Rob Herring
0b2f7ad1
0b7c446f
+1094
-68
+105
Documentation/devicetree/bindings/phy/allwinner,sun4i-a10-usb-phy.yaml
+105
Documentation/devicetree/bindings/phy/allwinner,sun4i-a10-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner A10 USB PHY Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <mripard@kernel.org>
12
+
13
+
properties:
14
+
"#phy-cells":
15
+
const: 1
16
+
17
+
compatible:
18
+
enum:
19
+
- allwinner,sun4i-a10-usb-phy
20
+
- allwinner,sun7i-a20-usb-phy
21
+
22
+
reg:
23
+
items:
24
+
- description: PHY Control registers
25
+
- description: PHY PMU1 registers
26
+
- description: PHY PMU2 registers
27
+
28
+
reg-names:
29
+
items:
30
+
- const: phy_ctrl
31
+
- const: pmu1
32
+
- const: pmu2
33
+
34
+
clocks:
35
+
maxItems: 1
36
+
description: USB PHY bus clock
37
+
38
+
clock-names:
39
+
const: usb_phy
40
+
41
+
resets:
42
+
items:
43
+
- description: USB OTG reset
44
+
- description: USB Host 1 Controller reset
45
+
- description: USB Host 2 Controller reset
46
+
47
+
reset-names:
48
+
items:
49
+
- const: usb0_reset
50
+
- const: usb1_reset
51
+
- const: usb2_reset
52
+
53
+
usb0_id_det-gpios:
54
+
description: GPIO to the USB OTG ID pin
55
+
56
+
usb0_vbus_det-gpios:
57
+
description: GPIO to the USB OTG VBUS detect pin
58
+
59
+
usb0_vbus_power-supply:
60
+
description: Power supply to detect the USB OTG VBUS
61
+
62
+
usb0_vbus-supply:
63
+
description: Regulator controlling USB OTG VBUS
64
+
65
+
usb1_vbus-supply:
66
+
description: Regulator controlling USB1 Host controller
67
+
68
+
usb2_vbus-supply:
69
+
description: Regulator controlling USB2 Host controller
70
+
71
+
required:
72
+
- "#phy-cells"
73
+
- compatible
74
+
- clocks
75
+
- clock-names
76
+
- reg
77
+
- reg-names
78
+
- resets
79
+
- reset-names
80
+
81
+
additionalProperties: false
82
+
83
+
examples:
84
+
- |
85
+
#include <dt-bindings/gpio/gpio.h>
86
+
#include <dt-bindings/clock/sun4i-a10-ccu.h>
87
+
#include <dt-bindings/reset/sun4i-a10-ccu.h>
88
+
89
+
usbphy: phy@01c13400 {
90
+
#phy-cells = <1>;
91
+
compatible = "allwinner,sun4i-a10-usb-phy";
92
+
reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
93
+
reg-names = "phy_ctrl", "pmu1", "pmu2";
94
+
clocks = <&ccu CLK_USB_PHY>;
95
+
clock-names = "usb_phy";
96
+
resets = <&ccu RST_USB_PHY0>,
97
+
<&ccu RST_USB_PHY1>,
98
+
<&ccu RST_USB_PHY2>;
99
+
reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
100
+
usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>;
101
+
usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>;
102
+
usb0_vbus-supply = <®_usb0_vbus>;
103
+
usb1_vbus-supply = <®_usb1_vbus>;
104
+
usb2_vbus-supply = <®_usb2_vbus>;
105
+
};
+106
Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
+106
Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner A64 USB PHY Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <mripard@kernel.org>
12
+
13
+
properties:
14
+
"#phy-cells":
15
+
const: 1
16
+
17
+
compatible:
18
+
const: allwinner,sun50i-a64-usb-phy
19
+
20
+
reg:
21
+
items:
22
+
- description: PHY Control registers
23
+
- description: PHY PMU0 registers
24
+
- description: PHY PMU1 registers
25
+
26
+
reg-names:
27
+
items:
28
+
- const: phy_ctrl
29
+
- const: pmu0
30
+
- const: pmu1
31
+
32
+
clocks:
33
+
items:
34
+
- description: USB OTG PHY bus clock
35
+
- description: USB Host 0 PHY bus clock
36
+
37
+
clock-names:
38
+
items:
39
+
- const: usb0_phy
40
+
- const: usb1_phy
41
+
42
+
resets:
43
+
items:
44
+
- description: USB OTG reset
45
+
- description: USB Host 1 Controller reset
46
+
47
+
reset-names:
48
+
items:
49
+
- const: usb0_reset
50
+
- const: usb1_reset
51
+
52
+
usb0_id_det-gpios:
53
+
description: GPIO to the USB OTG ID pin
54
+
55
+
usb0_vbus_det-gpios:
56
+
description: GPIO to the USB OTG VBUS detect pin
57
+
58
+
usb0_vbus_power-supply:
59
+
description: Power supply to detect the USB OTG VBUS
60
+
61
+
usb0_vbus-supply:
62
+
description: Regulator controlling USB OTG VBUS
63
+
64
+
usb1_vbus-supply:
65
+
description: Regulator controlling USB1 Host controller
66
+
67
+
required:
68
+
- "#phy-cells"
69
+
- compatible
70
+
- clocks
71
+
- clock-names
72
+
- reg
73
+
- reg-names
74
+
- resets
75
+
- reset-names
76
+
77
+
additionalProperties: false
78
+
79
+
examples:
80
+
- |
81
+
#include <dt-bindings/gpio/gpio.h>
82
+
#include <dt-bindings/clock/sun50i-a64-ccu.h>
83
+
#include <dt-bindings/reset/sun50i-a64-ccu.h>
84
+
85
+
phy@1c19400 {
86
+
#phy-cells = <1>;
87
+
compatible = "allwinner,sun50i-a64-usb-phy";
88
+
reg = <0x01c19400 0x14>,
89
+
<0x01c1a800 0x4>,
90
+
<0x01c1b800 0x4>;
91
+
reg-names = "phy_ctrl",
92
+
"pmu0",
93
+
"pmu1";
94
+
clocks = <&ccu CLK_USB_PHY0>,
95
+
<&ccu CLK_USB_PHY1>;
96
+
clock-names = "usb0_phy",
97
+
"usb1_phy";
98
+
resets = <&ccu RST_USB_PHY0>,
99
+
<&ccu RST_USB_PHY1>;
100
+
reset-names = "usb0_reset",
101
+
"usb1_reset";
102
+
usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
103
+
usb0_vbus_power-supply = <&usb_power_supply>;
104
+
usb0_vbus-supply = <®_drivevbus>;
105
+
usb1_vbus-supply = <®_usb1_vbus>;
106
+
};
+105
Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb-phy.yaml
+105
Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner H6 USB PHY Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <mripard@kernel.org>
12
+
13
+
properties:
14
+
"#phy-cells":
15
+
const: 1
16
+
17
+
compatible:
18
+
const: allwinner,sun50i-h6-usb-phy
19
+
20
+
reg:
21
+
items:
22
+
- description: PHY Control registers
23
+
- description: PHY PMU0 registers
24
+
- description: PHY PMU3 registers
25
+
26
+
reg-names:
27
+
items:
28
+
- const: phy_ctrl
29
+
- const: pmu0
30
+
- const: pmu3
31
+
32
+
clocks:
33
+
items:
34
+
- description: USB OTG PHY bus clock
35
+
- description: USB Host PHY bus clock
36
+
37
+
clock-names:
38
+
items:
39
+
- const: usb0_phy
40
+
- const: usb3_phy
41
+
42
+
resets:
43
+
items:
44
+
- description: USB OTG reset
45
+
- description: USB Host Controller reset
46
+
47
+
reset-names:
48
+
items:
49
+
- const: usb0_reset
50
+
- const: usb3_reset
51
+
52
+
usb0_id_det-gpios:
53
+
description: GPIO to the USB OTG ID pin
54
+
55
+
usb0_vbus_det-gpios:
56
+
description: GPIO to the USB OTG VBUS detect pin
57
+
58
+
usb0_vbus_power-supply:
59
+
description: Power supply to detect the USB OTG VBUS
60
+
61
+
usb0_vbus-supply:
62
+
description: Regulator controlling USB OTG VBUS
63
+
64
+
usb3_vbus-supply:
65
+
description: Regulator controlling USB3 Host controller
66
+
67
+
required:
68
+
- "#phy-cells"
69
+
- compatible
70
+
- clocks
71
+
- clock-names
72
+
- reg
73
+
- reg-names
74
+
- resets
75
+
- reset-names
76
+
77
+
additionalProperties: false
78
+
79
+
examples:
80
+
- |
81
+
#include <dt-bindings/gpio/gpio.h>
82
+
#include <dt-bindings/clock/sun50i-h6-ccu.h>
83
+
#include <dt-bindings/reset/sun50i-h6-ccu.h>
84
+
85
+
phy@5100400 {
86
+
#phy-cells = <1>;
87
+
compatible = "allwinner,sun50i-h6-usb-phy";
88
+
reg = <0x05100400 0x24>,
89
+
<0x05101800 0x4>,
90
+
<0x05311800 0x4>;
91
+
reg-names = "phy_ctrl",
92
+
"pmu0",
93
+
"pmu3";
94
+
clocks = <&ccu CLK_USB_PHY0>,
95
+
<&ccu CLK_USB_PHY3>;
96
+
clock-names = "usb0_phy",
97
+
"usb3_phy";
98
+
resets = <&ccu RST_USB_PHY0>,
99
+
<&ccu RST_USB_PHY3>;
100
+
reset-names = "usb0_reset",
101
+
"usb3_reset";
102
+
usb0_id_det-gpios = <&pio 2 6 GPIO_ACTIVE_HIGH>; /* PC6 */
103
+
usb0_vbus-supply = <®_vcc5v>;
104
+
usb3_vbus-supply = <®_vcc5v>;
105
+
};
+93
Documentation/devicetree/bindings/phy/allwinner,sun5i-a13-usb-phy.yaml
+93
Documentation/devicetree/bindings/phy/allwinner,sun5i-a13-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/allwinner,sun5i-a13-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner A13 USB PHY Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <mripard@kernel.org>
12
+
13
+
properties:
14
+
"#phy-cells":
15
+
const: 1
16
+
17
+
compatible:
18
+
const: allwinner,sun5i-a13-usb-phy
19
+
20
+
reg:
21
+
items:
22
+
- description: PHY Control registers
23
+
- description: PHY PMU1 registers
24
+
25
+
reg-names:
26
+
items:
27
+
- const: phy_ctrl
28
+
- const: pmu1
29
+
30
+
clocks:
31
+
maxItems: 1
32
+
description: USB OTG PHY bus clock
33
+
34
+
clock-names:
35
+
const: usb_phy
36
+
37
+
resets:
38
+
items:
39
+
- description: USB OTG reset
40
+
- description: USB Host 1 Controller reset
41
+
42
+
reset-names:
43
+
items:
44
+
- const: usb0_reset
45
+
- const: usb1_reset
46
+
47
+
usb0_id_det-gpios:
48
+
description: GPIO to the USB OTG ID pin
49
+
50
+
usb0_vbus_det-gpios:
51
+
description: GPIO to the USB OTG VBUS detect pin
52
+
53
+
usb0_vbus_power-supply:
54
+
description: Power supply to detect the USB OTG VBUS
55
+
56
+
usb0_vbus-supply:
57
+
description: Regulator controlling USB OTG VBUS
58
+
59
+
usb1_vbus-supply:
60
+
description: Regulator controlling USB1 Host controller
61
+
62
+
required:
63
+
- "#phy-cells"
64
+
- compatible
65
+
- clocks
66
+
- clock-names
67
+
- reg
68
+
- reg-names
69
+
- resets
70
+
- reset-names
71
+
72
+
additionalProperties: false
73
+
74
+
examples:
75
+
- |
76
+
#include <dt-bindings/gpio/gpio.h>
77
+
#include <dt-bindings/clock/sun5i-ccu.h>
78
+
#include <dt-bindings/reset/sun5i-ccu.h>
79
+
80
+
phy@1c13400 {
81
+
#phy-cells = <1>;
82
+
compatible = "allwinner,sun5i-a13-usb-phy";
83
+
reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
84
+
reg-names = "phy_ctrl", "pmu1";
85
+
clocks = <&ccu CLK_USB_PHY0>;
86
+
clock-names = "usb_phy";
87
+
resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
88
+
reset-names = "usb0_reset", "usb1_reset";
89
+
usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
90
+
usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
91
+
usb0_vbus-supply = <®_usb0_vbus>;
92
+
usb1_vbus-supply = <®_usb1_vbus>;
93
+
};
+119
Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-usb-phy.yaml
+119
Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner A31 USB PHY Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <mripard@kernel.org>
12
+
13
+
properties:
14
+
"#phy-cells":
15
+
const: 1
16
+
17
+
compatible:
18
+
const: allwinner,sun6i-a31-usb-phy
19
+
20
+
reg:
21
+
items:
22
+
- description: PHY Control registers
23
+
- description: PHY PMU1 registers
24
+
- description: PHY PMU2 registers
25
+
26
+
reg-names:
27
+
items:
28
+
- const: phy_ctrl
29
+
- const: pmu1
30
+
- const: pmu2
31
+
32
+
clocks:
33
+
items:
34
+
- description: USB OTG PHY bus clock
35
+
- description: USB Host 0 PHY bus clock
36
+
- description: USB Host 1 PHY bus clock
37
+
38
+
clock-names:
39
+
items:
40
+
- const: usb0_phy
41
+
- const: usb1_phy
42
+
- const: usb2_phy
43
+
44
+
resets:
45
+
items:
46
+
- description: USB OTG reset
47
+
- description: USB Host 1 Controller reset
48
+
- description: USB Host 2 Controller reset
49
+
50
+
reset-names:
51
+
items:
52
+
- const: usb0_reset
53
+
- const: usb1_reset
54
+
- const: usb2_reset
55
+
56
+
usb0_id_det-gpios:
57
+
description: GPIO to the USB OTG ID pin
58
+
59
+
usb0_vbus_det-gpios:
60
+
description: GPIO to the USB OTG VBUS detect pin
61
+
62
+
usb0_vbus_power-supply:
63
+
description: Power supply to detect the USB OTG VBUS
64
+
65
+
usb0_vbus-supply:
66
+
description: Regulator controlling USB OTG VBUS
67
+
68
+
usb1_vbus-supply:
69
+
description: Regulator controlling USB1 Host controller
70
+
71
+
usb2_vbus-supply:
72
+
description: Regulator controlling USB2 Host controller
73
+
74
+
required:
75
+
- "#phy-cells"
76
+
- compatible
77
+
- clocks
78
+
- clock-names
79
+
- reg
80
+
- reg-names
81
+
- resets
82
+
- reset-names
83
+
84
+
additionalProperties: false
85
+
86
+
examples:
87
+
- |
88
+
#include <dt-bindings/gpio/gpio.h>
89
+
#include <dt-bindings/clock/sun6i-a31-ccu.h>
90
+
#include <dt-bindings/reset/sun6i-a31-ccu.h>
91
+
92
+
phy@1c19400 {
93
+
#phy-cells = <1>;
94
+
compatible = "allwinner,sun6i-a31-usb-phy";
95
+
reg = <0x01c19400 0x10>,
96
+
<0x01c1a800 0x4>,
97
+
<0x01c1b800 0x4>;
98
+
reg-names = "phy_ctrl",
99
+
"pmu1",
100
+
"pmu2";
101
+
clocks = <&ccu CLK_USB_PHY0>,
102
+
<&ccu CLK_USB_PHY1>,
103
+
<&ccu CLK_USB_PHY2>;
104
+
clock-names = "usb0_phy",
105
+
"usb1_phy",
106
+
"usb2_phy";
107
+
resets = <&ccu RST_USB_PHY0>,
108
+
<&ccu RST_USB_PHY1>,
109
+
<&ccu RST_USB_PHY2>;
110
+
reset-names = "usb0_reset",
111
+
"usb1_reset",
112
+
"usb2_reset";
113
+
usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
114
+
usb0_vbus_det-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
115
+
usb0_vbus_power-supply = <&usb_power_supply>;
116
+
usb0_vbus-supply = <®_drivevbus>;
117
+
usb1_vbus-supply = <®_usb1_vbus>;
118
+
usb2_vbus-supply = <®_usb2_vbus>;
119
+
};
+102
Documentation/devicetree/bindings/phy/allwinner,sun8i-a23-usb-phy.yaml
+102
Documentation/devicetree/bindings/phy/allwinner,sun8i-a23-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/allwinner,sun8i-a23-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner A23 USB PHY Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <mripard@kernel.org>
12
+
13
+
properties:
14
+
"#phy-cells":
15
+
const: 1
16
+
17
+
compatible:
18
+
enum:
19
+
- allwinner,sun8i-a23-usb-phy
20
+
- allwinner,sun8i-a33-usb-phy
21
+
22
+
reg:
23
+
items:
24
+
- description: PHY Control registers
25
+
- description: PHY PMU1 registers
26
+
27
+
reg-names:
28
+
items:
29
+
- const: phy_ctrl
30
+
- const: pmu1
31
+
32
+
clocks:
33
+
items:
34
+
- description: USB OTG PHY bus clock
35
+
- description: USB Host 0 PHY bus clock
36
+
37
+
clock-names:
38
+
items:
39
+
- const: usb0_phy
40
+
- const: usb1_phy
41
+
42
+
resets:
43
+
items:
44
+
- description: USB OTG reset
45
+
- description: USB Host 1 Controller reset
46
+
47
+
reset-names:
48
+
items:
49
+
- const: usb0_reset
50
+
- const: usb1_reset
51
+
52
+
usb0_id_det-gpios:
53
+
description: GPIO to the USB OTG ID pin
54
+
55
+
usb0_vbus_det-gpios:
56
+
description: GPIO to the USB OTG VBUS detect pin
57
+
58
+
usb0_vbus_power-supply:
59
+
description: Power supply to detect the USB OTG VBUS
60
+
61
+
usb0_vbus-supply:
62
+
description: Regulator controlling USB OTG VBUS
63
+
64
+
usb1_vbus-supply:
65
+
description: Regulator controlling USB1 Host controller
66
+
67
+
required:
68
+
- "#phy-cells"
69
+
- compatible
70
+
- clocks
71
+
- clock-names
72
+
- reg
73
+
- reg-names
74
+
- resets
75
+
- reset-names
76
+
77
+
additionalProperties: false
78
+
79
+
examples:
80
+
- |
81
+
#include <dt-bindings/gpio/gpio.h>
82
+
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
83
+
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
84
+
85
+
phy@1c19400 {
86
+
#phy-cells = <1>;
87
+
compatible = "allwinner,sun8i-a23-usb-phy";
88
+
reg = <0x01c19400 0x10>, <0x01c1a800 0x4>;
89
+
reg-names = "phy_ctrl", "pmu1";
90
+
clocks = <&ccu CLK_USB_PHY0>,
91
+
<&ccu CLK_USB_PHY1>;
92
+
clock-names = "usb0_phy",
93
+
"usb1_phy";
94
+
resets = <&ccu RST_USB_PHY0>,
95
+
<&ccu RST_USB_PHY1>;
96
+
reset-names = "usb0_reset",
97
+
"usb1_reset";
98
+
usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
99
+
usb0_vbus_power-supply = <&usb_power_supply>;
100
+
usb0_vbus-supply = <®_drivevbus>;
101
+
usb1_vbus-supply = <®_usb1_vbus>;
102
+
};
+122
Documentation/devicetree/bindings/phy/allwinner,sun8i-a83t-usb-phy.yaml
+122
Documentation/devicetree/bindings/phy/allwinner,sun8i-a83t-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner A83t USB PHY Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <mripard@kernel.org>
12
+
13
+
properties:
14
+
"#phy-cells":
15
+
const: 1
16
+
17
+
compatible:
18
+
const: allwinner,sun8i-a83t-usb-phy
19
+
20
+
reg:
21
+
items:
22
+
- description: PHY Control registers
23
+
- description: PHY PMU1 registers
24
+
- description: PHY PMU2 registers
25
+
26
+
reg-names:
27
+
items:
28
+
- const: phy_ctrl
29
+
- const: pmu1
30
+
- const: pmu2
31
+
32
+
clocks:
33
+
items:
34
+
- description: USB OTG PHY bus clock
35
+
- description: USB Host 0 PHY bus clock
36
+
- description: USB Host 1 PHY bus clock
37
+
- description: USB HSIC 12MHz clock
38
+
39
+
clock-names:
40
+
items:
41
+
- const: usb0_phy
42
+
- const: usb1_phy
43
+
- const: usb2_phy
44
+
- const: usb2_hsic_12M
45
+
46
+
resets:
47
+
items:
48
+
- description: USB OTG reset
49
+
- description: USB Host 1 Controller reset
50
+
- description: USB Host 2 Controller reset
51
+
52
+
reset-names:
53
+
items:
54
+
- const: usb0_reset
55
+
- const: usb1_reset
56
+
- const: usb2_reset
57
+
58
+
usb0_id_det-gpios:
59
+
description: GPIO to the USB OTG ID pin
60
+
61
+
usb0_vbus_det-gpios:
62
+
description: GPIO to the USB OTG VBUS detect pin
63
+
64
+
usb0_vbus_power-supply:
65
+
description: Power supply to detect the USB OTG VBUS
66
+
67
+
usb0_vbus-supply:
68
+
description: Regulator controlling USB OTG VBUS
69
+
70
+
usb1_vbus-supply:
71
+
description: Regulator controlling USB1 Host controller
72
+
73
+
usb2_vbus-supply:
74
+
description: Regulator controlling USB2 Host controller
75
+
76
+
required:
77
+
- "#phy-cells"
78
+
- compatible
79
+
- clocks
80
+
- clock-names
81
+
- reg
82
+
- reg-names
83
+
- resets
84
+
- reset-names
85
+
86
+
additionalProperties: false
87
+
88
+
examples:
89
+
- |
90
+
#include <dt-bindings/gpio/gpio.h>
91
+
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
92
+
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
93
+
94
+
phy@1c19400 {
95
+
#phy-cells = <1>;
96
+
compatible = "allwinner,sun8i-a83t-usb-phy";
97
+
reg = <0x01c19400 0x10>,
98
+
<0x01c1a800 0x14>,
99
+
<0x01c1b800 0x14>;
100
+
reg-names = "phy_ctrl",
101
+
"pmu1",
102
+
"pmu2";
103
+
clocks = <&ccu CLK_USB_PHY0>,
104
+
<&ccu CLK_USB_PHY1>,
105
+
<&ccu CLK_USB_HSIC>,
106
+
<&ccu CLK_USB_HSIC_12M>;
107
+
clock-names = "usb0_phy",
108
+
"usb1_phy",
109
+
"usb2_phy",
110
+
"usb2_hsic_12M";
111
+
resets = <&ccu RST_USB_PHY0>,
112
+
<&ccu RST_USB_PHY1>,
113
+
<&ccu RST_USB_HSIC>;
114
+
reset-names = "usb0_reset",
115
+
"usb1_reset",
116
+
"usb2_reset";
117
+
usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
118
+
usb0_vbus_power-supply = <&usb_power_supply>;
119
+
usb0_vbus-supply = <®_drivevbus>;
120
+
usb1_vbus-supply = <®_usb1_vbus>;
121
+
usb2_vbus-supply = <®_usb2_vbus>;
122
+
};
+137
Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
+137
Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner H3 USB PHY Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <mripard@kernel.org>
12
+
13
+
properties:
14
+
"#phy-cells":
15
+
const: 1
16
+
17
+
compatible:
18
+
const: allwinner,sun8i-h3-usb-phy
19
+
20
+
reg:
21
+
items:
22
+
- description: PHY Control registers
23
+
- description: PHY PMU0 registers
24
+
- description: PHY PMU1 registers
25
+
- description: PHY PMU2 registers
26
+
- description: PHY PMU3 registers
27
+
28
+
reg-names:
29
+
items:
30
+
- const: phy_ctrl
31
+
- const: pmu0
32
+
- const: pmu1
33
+
- const: pmu2
34
+
- const: pmu3
35
+
36
+
clocks:
37
+
items:
38
+
- description: USB OTG PHY bus clock
39
+
- description: USB Host 0 PHY bus clock
40
+
- description: USB Host 1 PHY bus clock
41
+
- description: USB Host 2 PHY bus clock
42
+
43
+
clock-names:
44
+
items:
45
+
- const: usb0_phy
46
+
- const: usb1_phy
47
+
- const: usb2_phy
48
+
- const: usb3_phy
49
+
50
+
resets:
51
+
items:
52
+
- description: USB OTG reset
53
+
- description: USB Host 1 Controller reset
54
+
- description: USB Host 2 Controller reset
55
+
- description: USB Host 3 Controller reset
56
+
57
+
reset-names:
58
+
items:
59
+
- const: usb0_reset
60
+
- const: usb1_reset
61
+
- const: usb2_reset
62
+
- const: usb3_reset
63
+
64
+
usb0_id_det-gpios:
65
+
description: GPIO to the USB OTG ID pin
66
+
67
+
usb0_vbus_det-gpios:
68
+
description: GPIO to the USB OTG VBUS detect pin
69
+
70
+
usb0_vbus_power-supply:
71
+
description: Power supply to detect the USB OTG VBUS
72
+
73
+
usb0_vbus-supply:
74
+
description: Regulator controlling USB OTG VBUS
75
+
76
+
usb1_vbus-supply:
77
+
description: Regulator controlling USB1 Host controller
78
+
79
+
usb2_vbus-supply:
80
+
description: Regulator controlling USB2 Host controller
81
+
82
+
usb3_vbus-supply:
83
+
description: Regulator controlling USB3 Host controller
84
+
85
+
required:
86
+
- "#phy-cells"
87
+
- compatible
88
+
- clocks
89
+
- clock-names
90
+
- reg
91
+
- reg-names
92
+
- resets
93
+
- reset-names
94
+
95
+
additionalProperties: false
96
+
97
+
examples:
98
+
- |
99
+
#include <dt-bindings/gpio/gpio.h>
100
+
#include <dt-bindings/clock/sun8i-h3-ccu.h>
101
+
#include <dt-bindings/reset/sun8i-h3-ccu.h>
102
+
103
+
phy@1c19400 {
104
+
#phy-cells = <1>;
105
+
compatible = "allwinner,sun8i-h3-usb-phy";
106
+
reg = <0x01c19400 0x2c>,
107
+
<0x01c1a800 0x4>,
108
+
<0x01c1b800 0x4>,
109
+
<0x01c1c800 0x4>,
110
+
<0x01c1d800 0x4>;
111
+
reg-names = "phy_ctrl",
112
+
"pmu0",
113
+
"pmu1",
114
+
"pmu2",
115
+
"pmu3";
116
+
clocks = <&ccu CLK_USB_PHY0>,
117
+
<&ccu CLK_USB_PHY1>,
118
+
<&ccu CLK_USB_PHY2>,
119
+
<&ccu CLK_USB_PHY3>;
120
+
clock-names = "usb0_phy",
121
+
"usb1_phy",
122
+
"usb2_phy",
123
+
"usb3_phy";
124
+
resets = <&ccu RST_USB_PHY0>,
125
+
<&ccu RST_USB_PHY1>,
126
+
<&ccu RST_USB_PHY2>,
127
+
<&ccu RST_USB_PHY3>;
128
+
reset-names = "usb0_reset",
129
+
"usb1_reset",
130
+
"usb2_reset",
131
+
"usb3_reset";
132
+
usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
133
+
usb0_vbus-supply = <®_usb0_vbus>;
134
+
usb1_vbus-supply = <®_usb1_vbus>;
135
+
usb2_vbus-supply = <®_usb2_vbus>;
136
+
usb3_vbus-supply = <®_usb3_vbus>;
137
+
};
+119
Documentation/devicetree/bindings/phy/allwinner,sun8i-r40-usb-phy.yaml
+119
Documentation/devicetree/bindings/phy/allwinner,sun8i-r40-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/allwinner,sun8i-r40-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner R40 USB PHY Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <mripard@kernel.org>
12
+
13
+
properties:
14
+
"#phy-cells":
15
+
const: 1
16
+
17
+
compatible:
18
+
const: allwinner,sun8i-r40-usb-phy
19
+
20
+
reg:
21
+
items:
22
+
- description: PHY Control registers
23
+
- description: PHY PMU0 registers
24
+
- description: PHY PMU1 registers
25
+
- description: PHY PMU2 registers
26
+
27
+
reg-names:
28
+
items:
29
+
- const: phy_ctrl
30
+
- const: pmu0
31
+
- const: pmu1
32
+
- const: pmu2
33
+
34
+
clocks:
35
+
items:
36
+
- description: USB OTG PHY bus clock
37
+
- description: USB Host 0 PHY bus clock
38
+
- description: USB Host 1 PHY bus clock
39
+
40
+
clock-names:
41
+
items:
42
+
- const: usb0_phy
43
+
- const: usb1_phy
44
+
- const: usb2_phy
45
+
46
+
resets:
47
+
items:
48
+
- description: USB OTG reset
49
+
- description: USB Host 1 Controller reset
50
+
- description: USB Host 2 Controller reset
51
+
52
+
reset-names:
53
+
items:
54
+
- const: usb0_reset
55
+
- const: usb1_reset
56
+
- const: usb2_reset
57
+
58
+
usb0_id_det-gpios:
59
+
description: GPIO to the USB OTG ID pin
60
+
61
+
usb0_vbus_det-gpios:
62
+
description: GPIO to the USB OTG VBUS detect pin
63
+
64
+
usb0_vbus_power-supply:
65
+
description: Power supply to detect the USB OTG VBUS
66
+
67
+
usb0_vbus-supply:
68
+
description: Regulator controlling USB OTG VBUS
69
+
70
+
usb1_vbus-supply:
71
+
description: Regulator controlling USB1 Host controller
72
+
73
+
usb2_vbus-supply:
74
+
description: Regulator controlling USB2 Host controller
75
+
76
+
required:
77
+
- "#phy-cells"
78
+
- compatible
79
+
- clocks
80
+
- clock-names
81
+
- reg
82
+
- reg-names
83
+
- resets
84
+
- reset-names
85
+
86
+
additionalProperties: false
87
+
88
+
examples:
89
+
- |
90
+
#include <dt-bindings/gpio/gpio.h>
91
+
#include <dt-bindings/clock/sun8i-r40-ccu.h>
92
+
#include <dt-bindings/reset/sun8i-r40-ccu.h>
93
+
94
+
phy@1c13400 {
95
+
#phy-cells = <1>;
96
+
compatible = "allwinner,sun8i-r40-usb-phy";
97
+
reg = <0x01c13400 0x14>,
98
+
<0x01c14800 0x4>,
99
+
<0x01c19800 0x4>,
100
+
<0x01c1c800 0x4>;
101
+
reg-names = "phy_ctrl",
102
+
"pmu0",
103
+
"pmu1",
104
+
"pmu2";
105
+
clocks = <&ccu CLK_USB_PHY0>,
106
+
<&ccu CLK_USB_PHY1>,
107
+
<&ccu CLK_USB_PHY2>;
108
+
clock-names = "usb0_phy",
109
+
"usb1_phy",
110
+
"usb2_phy";
111
+
resets = <&ccu RST_USB_PHY0>,
112
+
<&ccu RST_USB_PHY1>,
113
+
<&ccu RST_USB_PHY2>;
114
+
reset-names = "usb0_reset",
115
+
"usb1_reset",
116
+
"usb2_reset";
117
+
usb1_vbus-supply = <®_vcc5v0>;
118
+
usb2_vbus-supply = <®_vcc5v0>;
119
+
};
+86
Documentation/devicetree/bindings/phy/allwinner,sun8i-v3s-usb-phy.yaml
+86
Documentation/devicetree/bindings/phy/allwinner,sun8i-v3s-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/allwinner,sun8i-v3s-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Allwinner V3s USB PHY Device Tree Bindings
8
+
9
+
maintainers:
10
+
- Chen-Yu Tsai <wens@csie.org>
11
+
- Maxime Ripard <mripard@kernel.org>
12
+
13
+
properties:
14
+
"#phy-cells":
15
+
const: 1
16
+
17
+
compatible:
18
+
const: allwinner,sun8i-v3s-usb-phy
19
+
20
+
reg:
21
+
items:
22
+
- description: PHY Control registers
23
+
- description: PHY PMU0 registers
24
+
25
+
reg-names:
26
+
items:
27
+
- const: phy_ctrl
28
+
- const: pmu0
29
+
30
+
clocks:
31
+
maxItems: 1
32
+
description: USB OTG PHY bus clock
33
+
34
+
clock-names:
35
+
const: usb0_phy
36
+
37
+
resets:
38
+
maxItems: 1
39
+
description: USB OTG reset
40
+
41
+
reset-names:
42
+
const: usb0_reset
43
+
44
+
usb0_id_det-gpios:
45
+
description: GPIO to the USB OTG ID pin
46
+
47
+
usb0_vbus_det-gpios:
48
+
description: GPIO to the USB OTG VBUS detect pin
49
+
50
+
usb0_vbus_power-supply:
51
+
description: Power supply to detect the USB OTG VBUS
52
+
53
+
usb0_vbus-supply:
54
+
description: Regulator controlling USB OTG VBUS
55
+
56
+
required:
57
+
- "#phy-cells"
58
+
- compatible
59
+
- clocks
60
+
- clock-names
61
+
- reg
62
+
- reg-names
63
+
- resets
64
+
- reset-names
65
+
66
+
additionalProperties: false
67
+
68
+
examples:
69
+
- |
70
+
#include <dt-bindings/gpio/gpio.h>
71
+
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
72
+
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
73
+
74
+
phy@1c19400 {
75
+
#phy-cells = <1>;
76
+
compatible = "allwinner,sun8i-v3s-usb-phy";
77
+
reg = <0x01c19400 0x2c>,
78
+
<0x01c1a800 0x4>;
79
+
reg-names = "phy_ctrl",
80
+
"pmu0";
81
+
clocks = <&ccu CLK_USB_PHY0>;
82
+
clock-names = "usb0_phy";
83
+
resets = <&ccu RST_USB_PHY0>;
84
+
reset-names = "usb0_reset";
85
+
usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
86
+
};
-68
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
-68
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
···
1
-
Allwinner sun4i USB PHY
2
-
-----------------------
3
-
4
-
Required properties:
5
-
- compatible : should be one of
6
-
* allwinner,sun4i-a10-usb-phy
7
-
* allwinner,sun5i-a13-usb-phy
8
-
* allwinner,sun6i-a31-usb-phy
9
-
* allwinner,sun7i-a20-usb-phy
10
-
* allwinner,sun8i-a23-usb-phy
11
-
* allwinner,sun8i-a33-usb-phy
12
-
* allwinner,sun8i-a83t-usb-phy
13
-
* allwinner,sun8i-h3-usb-phy
14
-
* allwinner,sun8i-r40-usb-phy
15
-
* allwinner,sun8i-v3s-usb-phy
16
-
* allwinner,sun50i-a64-usb-phy
17
-
* allwinner,sun50i-h6-usb-phy
18
-
- reg : a list of offset + length pairs
19
-
- reg-names :
20
-
* "phy_ctrl"
21
-
* "pmu0" for H3, V3s, A64 or H6
22
-
* "pmu1"
23
-
* "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
24
-
* "pmu3" for sun8i-h3 or sun50i-h6
25
-
- #phy-cells : from the generic phy bindings, must be 1
26
-
- clocks : phandle + clock specifier for the phy clocks
27
-
- clock-names :
28
-
* "usb_phy" for sun4i, sun5i or sun7i
29
-
* "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
30
-
* "usb0_phy", "usb1_phy" for sun8i
31
-
* "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t
32
-
* "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
33
-
* "usb0_phy" and "usb3_phy" for sun50i-h6
34
-
- resets : a list of phandle + reset specifier pairs
35
-
- reset-names :
36
-
* "usb0_reset"
37
-
* "usb1_reset"
38
-
* "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
39
-
* "usb3_reset" for sun8i-h3 and sun50i-h6
40
-
41
-
Optional properties:
42
-
- usb0_id_det-gpios : gpio phandle for reading the otg id pin value
43
-
- usb0_vbus_det-gpios : gpio phandle for detecting the presence of usb0 vbus
44
-
- usb0_vbus_power-supply: power-supply phandle for usb0 vbus presence detect
45
-
- usb0_vbus-supply : regulator phandle for controller usb0 vbus
46
-
- usb1_vbus-supply : regulator phandle for controller usb1 vbus
47
-
- usb2_vbus-supply : regulator phandle for controller usb2 vbus
48
-
- usb3_vbus-supply : regulator phandle for controller usb3 vbus
49
-
50
-
Example:
51
-
usbphy: phy@01c13400 {
52
-
#phy-cells = <1>;
53
-
compatible = "allwinner,sun4i-a10-usb-phy";
54
-
/* phy base regs, phy1 pmu reg, phy2 pmu reg */
55
-
reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
56
-
reg-names = "phy_ctrl", "pmu1", "pmu2";
57
-
clocks = <&usb_clk 8>;
58
-
clock-names = "usb_phy";
59
-
resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
60
-
reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
61
-
pinctrl-names = "default";
62
-
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
63
-
usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */
64
-
usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
65
-
usb0_vbus-supply = <®_usb0_vbus>;
66
-
usb1_vbus-supply = <®_usb1_vbus>;
67
-
usb2_vbus-supply = <®_usb2_vbus>;
68
-
};