···229229 "setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",230230 hz, spi_st->baud, sscbrg);231231232232- /* Set SSC_CTL and enable SSC */233233- var = readl_relaxed(spi_st->base + SSC_CTL);234234- var |= SSC_CTL_MS;232232+ /* Set SSC_CTL and enable SSC */233233+ var = readl_relaxed(spi_st->base + SSC_CTL);234234+ var |= SSC_CTL_MS;235235236236- if (spi->mode & SPI_CPOL)236236+ if (spi->mode & SPI_CPOL)237237 var |= SSC_CTL_PO;238238- else238238+ else239239 var &= ~SSC_CTL_PO;240240241241- if (spi->mode & SPI_CPHA)241241+ if (spi->mode & SPI_CPHA)242242 var |= SSC_CTL_PH;243243- else243243+ else244244 var &= ~SSC_CTL_PH;245245246246- if ((spi->mode & SPI_LSB_FIRST) == 0)246246+ if ((spi->mode & SPI_LSB_FIRST) == 0)247247 var |= SSC_CTL_HB;248248- else248248+ else249249 var &= ~SSC_CTL_HB;250250251251- if (spi->mode & SPI_LOOP)251251+ if (spi->mode & SPI_LOOP)252252 var |= SSC_CTL_LPB;253253- else253253+ else254254 var &= ~SSC_CTL_LPB;255255256256- var &= ~SSC_CTL_DATA_WIDTH_MSK;257257- var |= (spi->bits_per_word - 1);256256+ var &= ~SSC_CTL_DATA_WIDTH_MSK;257257+ var |= (spi->bits_per_word - 1);258258259259- var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;260260- var |= SSC_CTL_EN;259259+ var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;260260+ var |= SSC_CTL_EN;261261262262- writel_relaxed(var, spi_st->base + SSC_CTL);262262+ writel_relaxed(var, spi_st->base + SSC_CTL);263263264264- /* Clear the status register */265265- readl_relaxed(spi_st->base + SSC_RBUF);264264+ /* Clear the status register */265265+ readl_relaxed(spi_st->base + SSC_RBUF);266266267267- return 0;267267+ return 0;268268269269out_free_gpio:270270 gpio_free(cs);