dt-bindings: clock: Add Google gs101 clock management unit bindings

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Provide dt-schema documentation for Google gs101 SoC clock controller.
Currently this adds support for cmu_top, cmu_misc and cmu_apm.

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231209233106.147416-3-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

authored by

Peter Griffin and committed by

Krzysztof Kozlowski 2 years ago 0a910f16 fdd78ff0

+498

2 changed files

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Documentation

devicetree

bindings

clock

google,gs101-clock.yaml

include

dt-bindings

clock

google,gs101.h

+106

Documentation/devicetree/bindings/clock/google,gs101-clock.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Google GS101 SoC clock controller 8 + 9 + maintainers: 10 + - Peter Griffin <peter.griffin@linaro.org> 11 + 12 + description: | 13 + Google GS101 clock controller is comprised of several CMU units, generating 14 + clocks for different domains. Those CMU units are modeled as separate device 15 + tree nodes, and might depend on each other. The root clock in that clock tree 16 + is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate 17 + clock in dts. 18 + 19 + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and 20 + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. 21 + 22 + Each clock is assigned an identifier and client nodes can use this identifier 23 + to specify the clock which they consume. All clocks available for usage 24 + in clock consumer nodes are defined as preprocessor macros in 25 + 'dt-bindings/clock/gs101.h' header. 26 + 27 + properties: 28 + compatible: 29 + enum: 30 + - google,gs101-cmu-top 31 + - google,gs101-cmu-apm 32 + - google,gs101-cmu-misc 33 + 34 + clocks: 35 + minItems: 1 36 + maxItems: 2 37 + 38 + clock-names: 39 + minItems: 1 40 + maxItems: 2 41 + 42 + "#clock-cells": 43 + const: 1 44 + 45 + reg: 46 + maxItems: 1 47 + 48 + required: 49 + - compatible 50 + - "#clock-cells" 51 + - clocks 52 + - clock-names 53 + - reg 54 + 55 + allOf: 56 + - if: 57 + properties: 58 + compatible: 59 + contains: 60 + enum: 61 + - google,gs101-cmu-top 62 + - google,gs101-cmu-apm 63 + then: 64 + properties: 65 + clocks: 66 + items: 67 + - description: External reference clock (24.576 MHz) 68 + 69 + clock-names: 70 + items: 71 + - const: oscclk 72 + 73 + - if: 74 + properties: 75 + compatible: 76 + contains: 77 + const: google,gs101-cmu-misc 78 + 79 + then: 80 + properties: 81 + clocks: 82 + items: 83 + - description: Misc bus clock (from CMU_TOP) 84 + - description: Misc sss clock (from CMU_TOP) 85 + 86 + clock-names: 87 + items: 88 + - const: dout_cmu_misc_bus 89 + - const: dout_cmu_misc_sss 90 + 91 + additionalProperties: false 92 + 93 + examples: 94 + # Clock controller node for CMU_TOP 95 + - | 96 + #include <dt-bindings/clock/google,gs101.h> 97 + 98 + cmu_top: clock-controller@1e080000 { 99 + compatible = "google,gs101-cmu-top"; 100 + reg = <0x1e080000 0x8000>; 101 + #clock-cells = <1>; 102 + clocks = <&ext_24_5m>; 103 + clock-names = "oscclk"; 104 + }; 105 + 106 + ...

+392

include/dt-bindings/clock/google,gs101.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (C) 2023 Linaro Ltd. 4 + * Author: Peter Griffin <peter.griffin@linaro.org> 5 + * 6 + * Device Tree binding constants for Google gs101 clock controller. 7 + */ 8 + 9 + #ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H 10 + #define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H 11 + 12 + /* CMU_TOP PLL */ 13 + #define CLK_FOUT_SHARED0_PLL 1 14 + #define CLK_FOUT_SHARED1_PLL 2 15 + #define CLK_FOUT_SHARED2_PLL 3 16 + #define CLK_FOUT_SHARED3_PLL 4 17 + #define CLK_FOUT_SPARE_PLL 5 18 + 19 + /* CMU_TOP MUX */ 20 + #define CLK_MOUT_PLL_SHARED0 6 21 + #define CLK_MOUT_PLL_SHARED1 7 22 + #define CLK_MOUT_PLL_SHARED2 8 23 + #define CLK_MOUT_PLL_SHARED3 9 24 + #define CLK_MOUT_PLL_SPARE 10 25 + #define CLK_MOUT_CMU_BO_BUS 11 26 + #define CLK_MOUT_CMU_BUS0_BUS 12 27 + #define CLK_MOUT_CMU_BUS1_BUS 13 28 + #define CLK_MOUT_CMU_BUS2_BUS 14 29 + #define CLK_MOUT_CMU_CIS_CLK0 15 30 + #define CLK_MOUT_CMU_CIS_CLK1 16 31 + #define CLK_MOUT_CMU_CIS_CLK2 17 32 + #define CLK_MOUT_CMU_CIS_CLK3 18 33 + #define CLK_MOUT_CMU_CIS_CLK4 19 34 + #define CLK_MOUT_CMU_CIS_CLK5 20 35 + #define CLK_MOUT_CMU_CIS_CLK6 21 36 + #define CLK_MOUT_CMU_CIS_CLK7 22 37 + #define CLK_MOUT_CMU_CMU_BOOST 23 38 + #define CLK_MOUT_CMU_BOOST_OPTION1 24 39 + #define CLK_MOUT_CMU_CORE_BUS 25 40 + #define CLK_MOUT_CMU_CPUCL0_DBG 26 41 + #define CLK_MOUT_CMU_CPUCL0_SWITCH 27 42 + #define CLK_MOUT_CMU_CPUCL1_SWITCH 28 43 + #define CLK_MOUT_CMU_CPUCL2_SWITCH 29 44 + #define CLK_MOUT_CMU_CSIS_BUS 30 45 + #define CLK_MOUT_CMU_DISP_BUS 31 46 + #define CLK_MOUT_CMU_DNS_BUS 32 47 + #define CLK_MOUT_CMU_DPU_BUS 33 48 + #define CLK_MOUT_CMU_EH_BUS 34 49 + #define CLK_MOUT_CMU_G2D_G2D 35 50 + #define CLK_MOUT_CMU_G2D_MSCL 36 51 + #define CLK_MOUT_CMU_G3AA_G3AA 37 52 + #define CLK_MOUT_CMU_G3D_BUSD 38 53 + #define CLK_MOUT_CMU_G3D_GLB 39 54 + #define CLK_MOUT_CMU_G3D_SWITCH 40 55 + #define CLK_MOUT_CMU_GDC_GDC0 41 56 + #define CLK_MOUT_CMU_GDC_GDC1 42 57 + #define CLK_MOUT_CMU_GDC_SCSC 43 58 + #define CLK_MOUT_CMU_HPM 44 59 + #define CLK_MOUT_CMU_HSI0_BUS 45 60 + #define CLK_MOUT_CMU_HSI0_DPGTC 46 61 + #define CLK_MOUT_CMU_HSI0_USB31DRD 47 62 + #define CLK_MOUT_CMU_HSI0_USBDPDGB 48 63 + #define CLK_MOUT_CMU_HSI1_BUS 49 64 + #define CLK_MOUT_CMU_HSI1_PCIE 50 65 + #define CLK_MOUT_CMU_HSI2_BUS 51 66 + #define CLK_MOUT_CMU_HSI2_MMC_CARD 52 67 + #define CLK_MOUT_CMU_HSI2_PCIE 53 68 + #define CLK_MOUT_CMU_HSI2_UFS_EMBD 54 69 + #define CLK_MOUT_CMU_IPP_BUS 55 70 + #define CLK_MOUT_CMU_ITP_BUS 56 71 + #define CLK_MOUT_CMU_MCSC_ITSC 57 72 + #define CLK_MOUT_CMU_MCSC_MCSC 58 73 + #define CLK_MOUT_CMU_MFC_MFC 59 74 + #define CLK_MOUT_CMU_MIF_BUSP 60 75 + #define CLK_MOUT_CMU_MIF_SWITCH 61 76 + #define CLK_MOUT_CMU_MISC_BUS 62 77 + #define CLK_MOUT_CMU_MISC_SSS 63 78 + #define CLK_MOUT_CMU_PDP_BUS 64 79 + #define CLK_MOUT_CMU_PDP_VRA 65 80 + #define CLK_MOUT_CMU_PERIC0_BUS 66 81 + #define CLK_MOUT_CMU_PERIC0_IP 67 82 + #define CLK_MOUT_CMU_PERIC1_BUS 68 83 + #define CLK_MOUT_CMU_PERIC1_IP 69 84 + #define CLK_MOUT_CMU_TNR_BUS 70 85 + #define CLK_MOUT_CMU_TOP_BOOST_OPTION1 71 86 + #define CLK_MOUT_CMU_TOP_CMUREF 72 87 + #define CLK_MOUT_CMU_TPU_BUS 73 88 + #define CLK_MOUT_CMU_TPU_TPU 74 89 + #define CLK_MOUT_CMU_TPU_TPUCTL 75 90 + #define CLK_MOUT_CMU_TPU_UART 76 91 + #define CLK_MOUT_CMU_CMUREF 77 92 + 93 + /* CMU_TOP Dividers */ 94 + #define CLK_DOUT_CMU_BO_BUS 78 95 + #define CLK_DOUT_CMU_BUS0_BUS 79 96 + #define CLK_DOUT_CMU_BUS1_BUS 80 97 + #define CLK_DOUT_CMU_BUS2_BUS 81 98 + #define CLK_DOUT_CMU_CIS_CLK0 82 99 + #define CLK_DOUT_CMU_CIS_CLK1 83 100 + #define CLK_DOUT_CMU_CIS_CLK2 84 101 + #define CLK_DOUT_CMU_CIS_CLK3 85 102 + #define CLK_DOUT_CMU_CIS_CLK4 86 103 + #define CLK_DOUT_CMU_CIS_CLK5 87 104 + #define CLK_DOUT_CMU_CIS_CLK6 88 105 + #define CLK_DOUT_CMU_CIS_CLK7 89 106 + #define CLK_DOUT_CMU_CORE_BUS 90 107 + #define CLK_DOUT_CMU_CPUCL0_DBG 91 108 + #define CLK_DOUT_CMU_CPUCL0_SWITCH 92 109 + #define CLK_DOUT_CMU_CPUCL1_SWITCH 93 110 + #define CLK_DOUT_CMU_CPUCL2_SWITCH 94 111 + #define CLK_DOUT_CMU_CSIS_BUS 95 112 + #define CLK_DOUT_CMU_DISP_BUS 96 113 + #define CLK_DOUT_CMU_DNS_BUS 97 114 + #define CLK_DOUT_CMU_DPU_BUS 98 115 + #define CLK_DOUT_CMU_EH_BUS 99 116 + #define CLK_DOUT_CMU_G2D_G2D 100 117 + #define CLK_DOUT_CMU_G2D_MSCL 101 118 + #define CLK_DOUT_CMU_G3AA_G3AA 102 119 + #define CLK_DOUT_CMU_G3D_BUSD 103 120 + #define CLK_DOUT_CMU_G3D_GLB 104 121 + #define CLK_DOUT_CMU_G3D_SWITCH 105 122 + #define CLK_DOUT_CMU_GDC_GDC0 106 123 + #define CLK_DOUT_CMU_GDC_GDC1 107 124 + #define CLK_DOUT_CMU_GDC_SCSC 108 125 + #define CLK_DOUT_CMU_CMU_HPM 109 126 + #define CLK_DOUT_CMU_HSI0_BUS 110 127 + #define CLK_DOUT_CMU_HSI0_DPGTC 111 128 + #define CLK_DOUT_CMU_HSI0_USB31DRD 112 129 + #define CLK_DOUT_CMU_HSI0_USBDPDBG 113 130 + #define CLK_DOUT_CMU_HSI1_BUS 114 131 + #define CLK_DOUT_CMU_HSI1_PCIE 115 132 + #define CLK_DOUT_CMU_HSI2_BUS 116 133 + #define CLK_DOUT_CMU_HSI2_MMC_CARD 117 134 + #define CLK_DOUT_CMU_HSI2_PCIE 118 135 + #define CLK_DOUT_CMU_HSI2_UFS_EMBD 119 136 + #define CLK_DOUT_CMU_IPP_BUS 120 137 + #define CLK_DOUT_CMU_ITP_BUS 121 138 + #define CLK_DOUT_CMU_MCSC_ITSC 122 139 + #define CLK_DOUT_CMU_MCSC_MCSC 123 140 + #define CLK_DOUT_CMU_MFC_MFC 124 141 + #define CLK_DOUT_CMU_MIF_BUSP 125 142 + #define CLK_DOUT_CMU_MISC_BUS 126 143 + #define CLK_DOUT_CMU_MISC_SSS 127 144 + #define CLK_DOUT_CMU_OTP 128 145 + #define CLK_DOUT_CMU_PDP_BUS 129 146 + #define CLK_DOUT_CMU_PDP_VRA 130 147 + #define CLK_DOUT_CMU_PERIC0_BUS 131 148 + #define CLK_DOUT_CMU_PERIC0_IP 132 149 + #define CLK_DOUT_CMU_PERIC1_BUS 133 150 + #define CLK_DOUT_CMU_PERIC1_IP 134 151 + #define CLK_DOUT_CMU_TNR_BUS 135 152 + #define CLK_DOUT_CMU_TPU_BUS 136 153 + #define CLK_DOUT_CMU_TPU_TPU 137 154 + #define CLK_DOUT_CMU_TPU_TPUCTL 138 155 + #define CLK_DOUT_CMU_TPU_UART 139 156 + #define CLK_DOUT_CMU_CMU_BOOST 140 157 + #define CLK_DOUT_CMU_CMU_CMUREF 141 158 + #define CLK_DOUT_CMU_SHARED0_DIV2 142 159 + #define CLK_DOUT_CMU_SHARED0_DIV3 143 160 + #define CLK_DOUT_CMU_SHARED0_DIV4 144 161 + #define CLK_DOUT_CMU_SHARED0_DIV5 145 162 + #define CLK_DOUT_CMU_SHARED1_DIV2 146 163 + #define CLK_DOUT_CMU_SHARED1_DIV3 147 164 + #define CLK_DOUT_CMU_SHARED1_DIV4 148 165 + #define CLK_DOUT_CMU_SHARED2_DIV2 149 166 + #define CLK_DOUT_CMU_SHARED3_DIV2 150 167 + 168 + /* CMU_TOP Gates */ 169 + #define CLK_GOUT_BUS0_BOOST 151 170 + #define CLK_GOUT_BUS1_BOOST 152 171 + #define CLK_GOUT_BUS2_BOOST 153 172 + #define CLK_GOUT_CORE_BOOST 154 173 + #define CLK_GOUT_CPUCL0_BOOST 155 174 + #define CLK_GOUT_CPUCL1_BOOST 156 175 + #define CLK_GOUT_CPUCL2_BOOST 157 176 + #define CLK_GOUT_MIF_BOOST 158 177 + #define CLK_GOUT_MIF_SWITCH 159 178 + #define CLK_GOUT_BO_BUS 160 179 + #define CLK_GOUT_BUS0_BUS 161 180 + #define CLK_GOUT_BUS1_BUS 162 181 + #define CLK_GOUT_BUS2_BUS 163 182 + #define CLK_GOUT_CIS_CLK0 164 183 + #define CLK_GOUT_CIS_CLK1 165 184 + #define CLK_GOUT_CIS_CLK2 167 185 + #define CLK_GOUT_CIS_CLK3 168 186 + #define CLK_GOUT_CIS_CLK4 169 187 + #define CLK_GOUT_CIS_CLK5 170 188 + #define CLK_GOUT_CIS_CLK6 171 189 + #define CLK_GOUT_CIS_CLK7 172 190 + #define CLK_GOUT_CMU_BOOST 173 191 + #define CLK_GOUT_CORE_BUS 174 192 + #define CLK_GOUT_CPUCL0_DBG 175 193 + #define CLK_GOUT_CPUCL0_SWITCH 176 194 + #define CLK_GOUT_CPUCL1_SWITCH 177 195 + #define CLK_GOUT_CPUCL2_SWITCH 178 196 + #define CLK_GOUT_CSIS_BUS 179 197 + #define CLK_GOUT_DISP_BUS 180 198 + #define CLK_GOUT_DNS_BUS 181 199 + #define CLK_GOUT_DPU_BUS 182 200 + #define CLK_GOUT_EH_BUS 183 201 + #define CLK_GOUT_G2D_G2D 184 202 + #define CLK_GOUT_G2D_MSCL 185 203 + #define CLK_GOUT_G3AA_G3AA 186 204 + #define CLK_GOUT_G3D_BUSD 187 205 + #define CLK_GOUT_G3D_GLB 188 206 + #define CLK_GOUT_G3D_SWITCH 189 207 + #define CLK_GOUT_GDC_GDC0 190 208 + #define CLK_GOUT_GDC_GDC1 191 209 + #define CLK_GOUT_GDC_SCSC 192 210 + #define CLK_GOUT_CMU_HPM 193 211 + #define CLK_GOUT_HSI0_BUS 194 212 + #define CLK_GOUT_HSI0_DPGTC 195 213 + #define CLK_GOUT_HSI0_USB31DRD 196 214 + #define CLK_GOUT_HSI0_USBDPDGB 197 215 + #define CLK_GOUT_HSI1_BUS 198 216 + #define CLK_GOUT_HSI1_PCIE 199 217 + #define CLK_GOUT_HSI2_BUS 200 218 + #define CLK_GOUT_HSI2_MMC_CARD 201 219 + #define CLK_GOUT_HSI2_PCIE 202 220 + #define CLK_GOUT_HSI2_UFS_EMBD 203 221 + #define CLK_GOUT_IPP_BUS 204 222 + #define CLK_GOUT_ITP_BUS 205 223 + #define CLK_GOUT_MCSC_ITSC 206 224 + #define CLK_GOUT_MCSC_MCSC 207 225 + #define CLK_GOUT_MFC_MFC 208 226 + #define CLK_GOUT_MIF_BUSP 209 227 + #define CLK_GOUT_MISC_BUS 210 228 + #define CLK_GOUT_MISC_SSS 211 229 + #define CLK_GOUT_PDP_BUS 212 230 + #define CLK_GOUT_PDP_VRA 213 231 + #define CLK_GOUT_G3AA 214 232 + #define CLK_GOUT_PERIC0_BUS 215 233 + #define CLK_GOUT_PERIC0_IP 216 234 + #define CLK_GOUT_PERIC1_BUS 217 235 + #define CLK_GOUT_PERIC1_IP 218 236 + #define CLK_GOUT_TNR_BUS 219 237 + #define CLK_GOUT_TOP_CMUREF 220 238 + #define CLK_GOUT_TPU_BUS 221 239 + #define CLK_GOUT_TPU_TPU 222 240 + #define CLK_GOUT_TPU_TPUCTL 223 241 + #define CLK_GOUT_TPU_UART 224 242 + 243 + /* CMU_APM */ 244 + #define CLK_MOUT_APM_FUNC 1 245 + #define CLK_MOUT_APM_FUNCSRC 2 246 + #define CLK_DOUT_APM_BOOST 3 247 + #define CLK_DOUT_APM_USI0_UART 4 248 + #define CLK_DOUT_APM_USI0_USI 5 249 + #define CLK_DOUT_APM_USI1_UART 6 250 + #define CLK_GOUT_APM_APM_CMU_APM_PCLK 7 251 + #define CLK_GOUT_BUS0_BOOST_OPTION1 8 252 + #define CLK_GOUT_CMU_BOOST_OPTION1 9 253 + #define CLK_GOUT_CORE_BOOST_OPTION1 10 254 + #define CLK_GOUT_APM_FUNC 11 255 + #define CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 12 256 + #define CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK 13 257 + #define CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK 14 258 + #define CLK_GOUT_APM_APBIF_RTC_PCLK 15 259 + #define CLK_GOUT_APM_APBIF_TRTC_PCLK 16 260 + #define CLK_GOUT_APM_APM_USI0_UART_IPCLK 17 261 + #define CLK_GOUT_APM_APM_USI0_UART_PCLK 18 262 + #define CLK_GOUT_APM_APM_USI0_USI_IPCLK 19 263 + #define CLK_GOUT_APM_APM_USI0_USI_PCLK 20 264 + #define CLK_GOUT_APM_APM_USI1_UART_IPCLK 21 265 + #define CLK_GOUT_APM_APM_USI1_UART_PCLK 22 266 + #define CLK_GOUT_APM_D_TZPC_APM_PCLK 23 267 + #define CLK_GOUT_APM_GPC_APM_PCLK 24 268 + #define CLK_GOUT_APM_GREBEINTEGRATION_HCLK 25 269 + #define CLK_GOUT_APM_INTMEM_ACLK 26 270 + #define CLK_GOUT_APM_INTMEM_PCLK 27 271 + #define CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK 28 272 + #define CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK 29 273 + #define CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK 30 274 + #define CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK 31 275 + #define CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK 32 276 + #define CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK 33 277 + #define CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK 34 278 + #define CLK_GOUT_APM_MAILBOX_APM_AP_PCLK 35 279 + #define CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK 36 280 + #define CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK 37 281 + #define CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK 38 282 + #define CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK 39 283 + #define CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK 40 284 + #define CLK_GOUT_APM_PMU_INTR_GEN_PCLK 41 285 + #define CLK_GOUT_APM_ROM_CRC32_HOST_ACLK 42 286 + #define CLK_GOUT_APM_ROM_CRC32_HOST_PCLK 43 287 + #define CLK_GOUT_APM_CLK_APM_BUS_CLK 44 288 + #define CLK_GOUT_APM_CLK_APM_USI0_UART_CLK 45 289 + #define CLK_GOUT_APM_CLK_APM_USI0_USI_CLK 46 290 + #define CLK_GOUT_APM_CLK_APM_USI1_UART_CLK 47 291 + #define CLK_GOUT_APM_SPEEDY_APM_PCLK 48 292 + #define CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK 49 293 + #define CLK_GOUT_APM_SSMT_D_APM_ACLK 50 294 + #define CLK_GOUT_APM_SSMT_D_APM_PCLK 51 295 + #define CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK 52 296 + #define CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK 53 297 + #define CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK 54 298 + #define CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2 55 299 + #define CLK_GOUT_APM_SYSREG_APM_PCLK 56 300 + #define CLK_GOUT_APM_UASC_APM_ACLK 57 301 + #define CLK_GOUT_APM_UASC_APM_PCLK 58 302 + #define CLK_GOUT_APM_UASC_DBGCORE_ACLK 59 303 + #define CLK_GOUT_APM_UASC_DBGCORE_PCLK 60 304 + #define CLK_GOUT_APM_UASC_G_SWD_ACLK 61 305 + #define CLK_GOUT_APM_UASC_G_SWD_PCLK 62 306 + #define CLK_GOUT_APM_UASC_P_AOCAPM_ACLK 63 307 + #define CLK_GOUT_APM_UASC_P_AOCAPM_PCLK 64 308 + #define CLK_GOUT_APM_UASC_P_APM_ACLK 65 309 + #define CLK_GOUT_APM_UASC_P_APM_PCLK 66 310 + #define CLK_GOUT_APM_WDT_APM_PCLK 67 311 + #define CLK_GOUT_APM_XIU_DP_APM_ACLK 68 312 + #define CLK_APM_PLL_DIV2_APM 69 313 + #define CLK_APM_PLL_DIV4_APM 70 314 + #define CLK_APM_PLL_DIV16_APM 71 315 + 316 + /* CMU_MISC */ 317 + #define CLK_MOUT_MISC_BUS_USER 1 318 + #define CLK_MOUT_MISC_SSS_USER 2 319 + #define CLK_MOUT_MISC_GIC 3 320 + #define CLK_DOUT_MISC_BUSP 4 321 + #define CLK_DOUT_MISC_GIC 5 322 + #define CLK_GOUT_MISC_MISC_CMU_MISC_PCLK 6 323 + #define CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK 7 324 + #define CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK 8 325 + #define CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK 9 326 + #define CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK 10 327 + #define CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM 11 328 + #define CLK_GOUT_MISC_AD_APB_DIT_PCLKM 12 329 + #define CLK_GOUT_MISC_AD_APB_PUF_PCLKM 13 330 + #define CLK_GOUT_MISC_DIT_ICLKL2A 14 331 + #define CLK_GOUT_MISC_D_TZPC_MISC_PCLK 15 332 + #define CLK_GOUT_MISC_GIC_GICCLK 16 333 + #define CLK_GOUT_MISC_GPC_MISC_PCLK 17 334 + #define CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK 18 335 + #define CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK 19 336 + #define CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK 20 337 + #define CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK 21 338 + #define CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK 22 339 + #define CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK 23 340 + #define CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK 24 341 + #define CLK_GOUT_MISC_MCT_PCLK 25 342 + #define CLK_GOUT_MISC_OTP_CON_BIRA_PCLK 26 343 + #define CLK_GOUT_MISC_OTP_CON_BISR_PCLK 27 344 + #define CLK_GOUT_MISC_OTP_CON_TOP_PCLK 28 345 + #define CLK_GOUT_MISC_PDMA_ACLK 29 346 + #define CLK_GOUT_MISC_PPMU_DMA_ACLK 30 347 + #define CLK_GOUT_MISC_PPMU_MISC_ACLK 31 348 + #define CLK_GOUT_MISC_PPMU_MISC_PCLK 32 349 + #define CLK_GOUT_MISC_PUF_I_CLK 33 350 + #define CLK_GOUT_MISC_QE_DIT_ACLK 34 351 + #define CLK_GOUT_MISC_QE_DIT_PCLK 35 352 + #define CLK_GOUT_MISC_QE_PDMA_ACLK 36 353 + #define CLK_GOUT_MISC_QE_PDMA_PCLK 37 354 + #define CLK_GOUT_MISC_QE_PPMU_DMA_ACLK 38 355 + #define CLK_GOUT_MISC_QE_PPMU_DMA_PCLK 39 356 + #define CLK_GOUT_MISC_QE_RTIC_ACLK 40 357 + #define CLK_GOUT_MISC_QE_RTIC_PCLK 41 358 + #define CLK_GOUT_MISC_QE_SPDMA_ACLK 42 359 + #define CLK_GOUT_MISC_QE_SPDMA_PCLK 43 360 + #define CLK_GOUT_MISC_QE_SSS_ACLK 44 361 + #define CLK_GOUT_MISC_QE_SSS_PCLK 45 362 + #define CLK_GOUT_MISC_CLK_MISC_BUSD_CLK 46 363 + #define CLK_GOUT_MISC_CLK_MISC_BUSP_CLK 47 364 + #define CLK_GOUT_MISC_CLK_MISC_GIC_CLK 48 365 + #define CLK_GOUT_MISC_CLK_MISC_SSS_CLK 49 366 + #define CLK_GOUT_MISC_RTIC_I_ACLK 50 367 + #define CLK_GOUT_MISC_RTIC_I_PCLK 51 368 + #define CLK_GOUT_MISC_SPDMA_ACLK 52 369 + #define CLK_GOUT_MISC_SSMT_DIT_ACLK 53 370 + #define CLK_GOUT_MISC_SSMT_DIT_PCLK 54 371 + #define CLK_GOUT_MISC_SSMT_PDMA_ACLK 55 372 + #define CLK_GOUT_MISC_SSMT_PDMA_PCLK 56 373 + #define CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK 57 374 + #define CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK 58 375 + #define CLK_GOUT_MISC_SSMT_RTIC_ACLK 59 376 + #define CLK_GOUT_MISC_SSMT_RTIC_PCLK 60 377 + #define CLK_GOUT_MISC_SSMT_SPDMA_ACLK 61 378 + #define CLK_GOUT_MISC_SSMT_SPDMA_PCLK 62 379 + #define CLK_GOUT_MISC_SSMT_SSS_ACLK 63 380 + #define CLK_GOUT_MISC_SSMT_SSS_PCLK 64 381 + #define CLK_GOUT_MISC_SSS_I_ACLK 65 382 + #define CLK_GOUT_MISC_SSS_I_PCLK 66 383 + #define CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2 67 384 + #define CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1 68 385 + #define CLK_GOUT_MISC_SYSREG_MISC_PCLK 69 386 + #define CLK_GOUT_MISC_TMU_SUB_PCLK 70 387 + #define CLK_GOUT_MISC_TMU_TOP_PCLK 71 388 + #define CLK_GOUT_MISC_WDT_CLUSTER0_PCLK 72 389 + #define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73 390 + #define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74 391 + 392 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */