drm/rockchip: vop: add rk3399 vop support

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

There are two VOP in rk3399 chip, respectively VOP_BIG and VOP_LIT.
most registers layout of this two vop is same, their framework are both
VOP_FULL, the Major differences of this two is that:

VOP_BIG max output resolution is 4096x2160.
VOP_LIT max output resolution is 2560x1600

VOP_BIG support four windows.
VOP_LIT only support two windows.

RK3399 vop register layout is similar with rk3288, so some feature
can reuse with rk3288.

Reviewed-by: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>

authored by

Mark Yao and committed by

Sean Paul 9 years ago 0a63bfd0 d49463ec

+298 -5

4 changed files

expand all

drivers

gpu

drm

rockchip

rockchip_drm_vop.c

rockchip_drm_vop.h

rockchip_vop_reg.c

rockchip_vop_reg.h

+10 -5

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

··· 912 912 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 913 913 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 914 914 u16 vact_end = vact_st + vdisplay; 915 - uint32_t val; 915 + uint32_t pin_pol, val; 916 916 917 917 WARN_ON(vop->event); 918 918 ··· 953 953 vop_dsp_hold_valid_irq_disable(vop); 954 954 } 955 955 956 - val = 0x8; 957 - val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 958 - val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 959 - VOP_CTRL_SET(vop, pin_pol, val); 956 + pin_pol = 0x8; 957 + pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 958 + pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 959 + VOP_CTRL_SET(vop, pin_pol, pin_pol); 960 + 960 961 switch (s->output_type) { 961 962 case DRM_MODE_CONNECTOR_LVDS: 962 963 VOP_CTRL_SET(vop, rgb_en, 1); 964 + VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol); 963 965 break; 964 966 case DRM_MODE_CONNECTOR_eDP: 967 + VOP_CTRL_SET(vop, edp_pin_pol, pin_pol); 965 968 VOP_CTRL_SET(vop, edp_en, 1); 966 969 break; 967 970 case DRM_MODE_CONNECTOR_HDMIA: 971 + VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol); 968 972 VOP_CTRL_SET(vop, hdmi_en, 1); 969 973 break; 970 974 case DRM_MODE_CONNECTOR_DSI: 975 + VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol); 971 976 VOP_CTRL_SET(vop, mipi_en, 1); 972 977 break; 973 978 default:

drivers/gpu/drm/rockchip/rockchip_drm_vop.h

··· 49 49 struct vop_reg dither_down; 50 50 struct vop_reg dither_up; 51 51 struct vop_reg pin_pol; 52 + struct vop_reg rgb_pin_pol; 53 + struct vop_reg hdmi_pin_pol; 54 + struct vop_reg edp_pin_pol; 55 + struct vop_reg mipi_pin_pol; 52 56 53 57 struct vop_reg htotal_pw; 54 58 struct vop_reg hact_st_end;

+91

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

··· 279 279 .win_size = ARRAY_SIZE(rk3288_vop_win_data), 280 280 }; 281 281 282 + static const struct vop_ctrl rk3399_ctrl_data = { 283 + .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22), 284 + .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), 285 + .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12), 286 + .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13), 287 + .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14), 288 + .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15), 289 + .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1), 290 + .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6), 291 + .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19), 292 + .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), 293 + .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), 294 + .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20), 295 + .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24), 296 + .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28), 297 + .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 298 + .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0), 299 + .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 300 + .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0), 301 + .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 302 + .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 303 + .cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0), 304 + }; 305 + 306 + static const int rk3399_vop_intrs[] = { 307 + FS_INTR, 308 + 0, 0, 309 + LINE_FLAG_INTR, 310 + 0, 311 + BUS_ERROR_INTR, 312 + 0, 0, 0, 0, 0, 0, 0, 313 + DSP_HOLD_VALID_INTR, 314 + }; 315 + 316 + static const struct vop_intr rk3399_vop_intr = { 317 + .intrs = rk3399_vop_intrs, 318 + .nintrs = ARRAY_SIZE(rk3399_vop_intrs), 319 + .status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0), 320 + .enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0), 321 + .clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0), 322 + }; 323 + 324 + static const struct vop_reg_data rk3399_init_reg_table[] = { 325 + {RK3399_SYS_CTRL, 0x2000f800}, 326 + {RK3399_DSP_CTRL0, 0x00000000}, 327 + {RK3399_WIN0_CTRL0, 0x00000080}, 328 + {RK3399_WIN1_CTRL0, 0x00000080}, 329 + /* TODO: Win2/3 support multiple area function, but we haven't found 330 + * a suitable way to use it yet, so let's just use them as other windows 331 + * with only area 0 enabled. 332 + */ 333 + {RK3399_WIN2_CTRL0, 0x00000010}, 334 + {RK3399_WIN3_CTRL0, 0x00000010}, 335 + }; 336 + 337 + static const struct vop_data rk3399_vop_big = { 338 + .init_table = rk3399_init_reg_table, 339 + .table_size = ARRAY_SIZE(rk3399_init_reg_table), 340 + .intr = &rk3399_vop_intr, 341 + .ctrl = &rk3399_ctrl_data, 342 + /* 343 + * rk3399 vop big windows register layout is same as rk3288. 344 + */ 345 + .win = rk3288_vop_win_data, 346 + .win_size = ARRAY_SIZE(rk3288_vop_win_data), 347 + }; 348 + 349 + static const struct vop_win_data rk3399_vop_lit_win_data[] = { 350 + { .base = 0x00, .phy = &rk3288_win01_data, 351 + .type = DRM_PLANE_TYPE_PRIMARY }, 352 + { .base = 0x00, .phy = &rk3288_win23_data, 353 + .type = DRM_PLANE_TYPE_CURSOR}, 354 + }; 355 + 356 + static const struct vop_data rk3399_vop_lit = { 357 + .init_table = rk3399_init_reg_table, 358 + .table_size = ARRAY_SIZE(rk3399_init_reg_table), 359 + .intr = &rk3399_vop_intr, 360 + .ctrl = &rk3399_ctrl_data, 361 + /* 362 + * rk3399 vop lit windows register layout is same as rk3288, 363 + * but cut off the win1 and win3 windows. 364 + */ 365 + .win = rk3399_vop_lit_win_data, 366 + .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), 367 + }; 368 + 282 369 static const struct of_device_id vop_driver_dt_match[] = { 283 370 { .compatible = "rockchip,rk3036-vop", 284 371 .data = &rk3036_vop }, 285 372 { .compatible = "rockchip,rk3288-vop", 286 373 .data = &rk3288_vop }, 374 + { .compatible = "rockchip,rk3399-vop-big", 375 + .data = &rk3399_vop_big }, 376 + { .compatible = "rockchip,rk3399-vop-lit", 377 + .data = &rk3399_vop_lit }, 287 378 {}, 288 379 }; 289 380 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);

+193

drivers/gpu/drm/rockchip/rockchip_vop_reg.h

··· 166 166 #define RK3036_HWC_LUT_ADDR 0x800 167 167 /* rk3036 register definition end */ 168 168 169 + /* rk3399 register definition */ 170 + #define RK3399_REG_CFG_DONE 0x00000 171 + #define RK3399_VERSION_INFO 0x00004 172 + #define RK3399_SYS_CTRL 0x00008 173 + #define RK3399_SYS_CTRL1 0x0000c 174 + #define RK3399_DSP_CTRL0 0x00010 175 + #define RK3399_DSP_CTRL1 0x00014 176 + #define RK3399_DSP_BG 0x00018 177 + #define RK3399_MCU_CTRL 0x0001c 178 + #define RK3399_WB_CTRL0 0x00020 179 + #define RK3399_WB_CTRL1 0x00024 180 + #define RK3399_WB_YRGB_MST 0x00028 181 + #define RK3399_WB_CBR_MST 0x0002c 182 + #define RK3399_WIN0_CTRL0 0x00030 183 + #define RK3399_WIN0_CTRL1 0x00034 184 + #define RK3399_WIN0_COLOR_KEY 0x00038 185 + #define RK3399_WIN0_VIR 0x0003c 186 + #define RK3399_WIN0_YRGB_MST 0x00040 187 + #define RK3399_WIN0_CBR_MST 0x00044 188 + #define RK3399_WIN0_ACT_INFO 0x00048 189 + #define RK3399_WIN0_DSP_INFO 0x0004c 190 + #define RK3399_WIN0_DSP_ST 0x00050 191 + #define RK3399_WIN0_SCL_FACTOR_YRGB 0x00054 192 + #define RK3399_WIN0_SCL_FACTOR_CBR 0x00058 193 + #define RK3399_WIN0_SCL_OFFSET 0x0005c 194 + #define RK3399_WIN0_SRC_ALPHA_CTRL 0x00060 195 + #define RK3399_WIN0_DST_ALPHA_CTRL 0x00064 196 + #define RK3399_WIN0_FADING_CTRL 0x00068 197 + #define RK3399_WIN0_CTRL2 0x0006c 198 + #define RK3399_WIN1_CTRL0 0x00070 199 + #define RK3399_WIN1_CTRL1 0x00074 200 + #define RK3399_WIN1_COLOR_KEY 0x00078 201 + #define RK3399_WIN1_VIR 0x0007c 202 + #define RK3399_WIN1_YRGB_MST 0x00080 203 + #define RK3399_WIN1_CBR_MST 0x00084 204 + #define RK3399_WIN1_ACT_INFO 0x00088 205 + #define RK3399_WIN1_DSP_INFO 0x0008c 206 + #define RK3399_WIN1_DSP_ST 0x00090 207 + #define RK3399_WIN1_SCL_FACTOR_YRGB 0x00094 208 + #define RK3399_WIN1_SCL_FACTOR_CBR 0x00098 209 + #define RK3399_WIN1_SCL_OFFSET 0x0009c 210 + #define RK3399_WIN1_SRC_ALPHA_CTRL 0x000a0 211 + #define RK3399_WIN1_DST_ALPHA_CTRL 0x000a4 212 + #define RK3399_WIN1_FADING_CTRL 0x000a8 213 + #define RK3399_WIN1_CTRL2 0x000ac 214 + #define RK3399_WIN2_CTRL0 0x000b0 215 + #define RK3399_WIN2_CTRL1 0x000b4 216 + #define RK3399_WIN2_VIR0_1 0x000b8 217 + #define RK3399_WIN2_VIR2_3 0x000bc 218 + #define RK3399_WIN2_MST0 0x000c0 219 + #define RK3399_WIN2_DSP_INFO0 0x000c4 220 + #define RK3399_WIN2_DSP_ST0 0x000c8 221 + #define RK3399_WIN2_COLOR_KEY 0x000cc 222 + #define RK3399_WIN2_MST1 0x000d0 223 + #define RK3399_WIN2_DSP_INFO1 0x000d4 224 + #define RK3399_WIN2_DSP_ST1 0x000d8 225 + #define RK3399_WIN2_SRC_ALPHA_CTRL 0x000dc 226 + #define RK3399_WIN2_MST2 0x000e0 227 + #define RK3399_WIN2_DSP_INFO2 0x000e4 228 + #define RK3399_WIN2_DSP_ST2 0x000e8 229 + #define RK3399_WIN2_DST_ALPHA_CTRL 0x000ec 230 + #define RK3399_WIN2_MST3 0x000f0 231 + #define RK3399_WIN2_DSP_INFO3 0x000f4 232 + #define RK3399_WIN2_DSP_ST3 0x000f8 233 + #define RK3399_WIN2_FADING_CTRL 0x000fc 234 + #define RK3399_WIN3_CTRL0 0x00100 235 + #define RK3399_WIN3_CTRL1 0x00104 236 + #define RK3399_WIN3_VIR0_1 0x00108 237 + #define RK3399_WIN3_VIR2_3 0x0010c 238 + #define RK3399_WIN3_MST0 0x00110 239 + #define RK3399_WIN3_DSP_INFO0 0x00114 240 + #define RK3399_WIN3_DSP_ST0 0x00118 241 + #define RK3399_WIN3_COLOR_KEY 0x0011c 242 + #define RK3399_WIN3_MST1 0x00120 243 + #define RK3399_WIN3_DSP_INFO1 0x00124 244 + #define RK3399_WIN3_DSP_ST1 0x00128 245 + #define RK3399_WIN3_SRC_ALPHA_CTRL 0x0012c 246 + #define RK3399_WIN3_MST2 0x00130 247 + #define RK3399_WIN3_DSP_INFO2 0x00134 248 + #define RK3399_WIN3_DSP_ST2 0x00138 249 + #define RK3399_WIN3_DST_ALPHA_CTRL 0x0013c 250 + #define RK3399_WIN3_MST3 0x00140 251 + #define RK3399_WIN3_DSP_INFO3 0x00144 252 + #define RK3399_WIN3_DSP_ST3 0x00148 253 + #define RK3399_WIN3_FADING_CTRL 0x0014c 254 + #define RK3399_HWC_CTRL0 0x00150 255 + #define RK3399_HWC_CTRL1 0x00154 256 + #define RK3399_HWC_MST 0x00158 257 + #define RK3399_HWC_DSP_ST 0x0015c 258 + #define RK3399_HWC_SRC_ALPHA_CTRL 0x00160 259 + #define RK3399_HWC_DST_ALPHA_CTRL 0x00164 260 + #define RK3399_HWC_FADING_CTRL 0x00168 261 + #define RK3399_HWC_RESERVED1 0x0016c 262 + #define RK3399_POST_DSP_HACT_INFO 0x00170 263 + #define RK3399_POST_DSP_VACT_INFO 0x00174 264 + #define RK3399_POST_SCL_FACTOR_YRGB 0x00178 265 + #define RK3399_POST_RESERVED 0x0017c 266 + #define RK3399_POST_SCL_CTRL 0x00180 267 + #define RK3399_POST_DSP_VACT_INFO_F1 0x00184 268 + #define RK3399_DSP_HTOTAL_HS_END 0x00188 269 + #define RK3399_DSP_HACT_ST_END 0x0018c 270 + #define RK3399_DSP_VTOTAL_VS_END 0x00190 271 + #define RK3399_DSP_VACT_ST_END 0x00194 272 + #define RK3399_DSP_VS_ST_END_F1 0x00198 273 + #define RK3399_DSP_VACT_ST_END_F1 0x0019c 274 + #define RK3399_PWM_CTRL 0x001a0 275 + #define RK3399_PWM_PERIOD_HPR 0x001a4 276 + #define RK3399_PWM_DUTY_LPR 0x001a8 277 + #define RK3399_PWM_CNT 0x001ac 278 + #define RK3399_BCSH_COLOR_BAR 0x001b0 279 + #define RK3399_BCSH_BCS 0x001b4 280 + #define RK3399_BCSH_H 0x001b8 281 + #define RK3399_BCSH_CTRL 0x001bc 282 + #define RK3399_CABC_CTRL0 0x001c0 283 + #define RK3399_CABC_CTRL1 0x001c4 284 + #define RK3399_CABC_CTRL2 0x001c8 285 + #define RK3399_CABC_CTRL3 0x001cc 286 + #define RK3399_CABC_GAUSS_LINE0_0 0x001d0 287 + #define RK3399_CABC_GAUSS_LINE0_1 0x001d4 288 + #define RK3399_CABC_GAUSS_LINE1_0 0x001d8 289 + #define RK3399_CABC_GAUSS_LINE1_1 0x001dc 290 + #define RK3399_CABC_GAUSS_LINE2_0 0x001e0 291 + #define RK3399_CABC_GAUSS_LINE2_1 0x001e4 292 + #define RK3399_FRC_LOWER01_0 0x001e8 293 + #define RK3399_FRC_LOWER01_1 0x001ec 294 + #define RK3399_FRC_LOWER10_0 0x001f0 295 + #define RK3399_FRC_LOWER10_1 0x001f4 296 + #define RK3399_FRC_LOWER11_0 0x001f8 297 + #define RK3399_FRC_LOWER11_1 0x001fc 298 + #define RK3399_AFBCD0_CTRL 0x00200 299 + #define RK3399_AFBCD0_HDR_PTR 0x00204 300 + #define RK3399_AFBCD0_PIC_SIZE 0x00208 301 + #define RK3399_AFBCD0_STATUS 0x0020c 302 + #define RK3399_AFBCD1_CTRL 0x00220 303 + #define RK3399_AFBCD1_HDR_PTR 0x00224 304 + #define RK3399_AFBCD1_PIC_SIZE 0x00228 305 + #define RK3399_AFBCD1_STATUS 0x0022c 306 + #define RK3399_AFBCD2_CTRL 0x00240 307 + #define RK3399_AFBCD2_HDR_PTR 0x00244 308 + #define RK3399_AFBCD2_PIC_SIZE 0x00248 309 + #define RK3399_AFBCD2_STATUS 0x0024c 310 + #define RK3399_AFBCD3_CTRL 0x00260 311 + #define RK3399_AFBCD3_HDR_PTR 0x00264 312 + #define RK3399_AFBCD3_PIC_SIZE 0x00268 313 + #define RK3399_AFBCD3_STATUS 0x0026c 314 + #define RK3399_INTR_EN0 0x00280 315 + #define RK3399_INTR_CLEAR0 0x00284 316 + #define RK3399_INTR_STATUS0 0x00288 317 + #define RK3399_INTR_RAW_STATUS0 0x0028c 318 + #define RK3399_INTR_EN1 0x00290 319 + #define RK3399_INTR_CLEAR1 0x00294 320 + #define RK3399_INTR_STATUS1 0x00298 321 + #define RK3399_INTR_RAW_STATUS1 0x0029c 322 + #define RK3399_LINE_FLAG 0x002a0 323 + #define RK3399_VOP_STATUS 0x002a4 324 + #define RK3399_BLANKING_VALUE 0x002a8 325 + #define RK3399_MCU_BYPASS_PORT 0x002ac 326 + #define RK3399_WIN0_DSP_BG 0x002b0 327 + #define RK3399_WIN1_DSP_BG 0x002b4 328 + #define RK3399_WIN2_DSP_BG 0x002b8 329 + #define RK3399_WIN3_DSP_BG 0x002bc 330 + #define RK3399_YUV2YUV_WIN 0x002c0 331 + #define RK3399_YUV2YUV_POST 0x002c4 332 + #define RK3399_AUTO_GATING_EN 0x002cc 333 + #define RK3399_WIN0_CSC_COE 0x003a0 334 + #define RK3399_WIN1_CSC_COE 0x003c0 335 + #define RK3399_WIN2_CSC_COE 0x003e0 336 + #define RK3399_WIN3_CSC_COE 0x00400 337 + #define RK3399_HWC_CSC_COE 0x00420 338 + #define RK3399_BCSH_R2Y_CSC_COE 0x00440 339 + #define RK3399_BCSH_Y2R_CSC_COE 0x00460 340 + #define RK3399_POST_YUV2YUV_Y2R_COE 0x00480 341 + #define RK3399_POST_YUV2YUV_3X3_COE 0x004a0 342 + #define RK3399_POST_YUV2YUV_R2Y_COE 0x004c0 343 + #define RK3399_WIN0_YUV2YUV_Y2R 0x004e0 344 + #define RK3399_WIN0_YUV2YUV_3X3 0x00500 345 + #define RK3399_WIN0_YUV2YUV_R2Y 0x00520 346 + #define RK3399_WIN1_YUV2YUV_Y2R 0x00540 347 + #define RK3399_WIN1_YUV2YUV_3X3 0x00560 348 + #define RK3399_WIN1_YUV2YUV_R2Y 0x00580 349 + #define RK3399_WIN2_YUV2YUV_Y2R 0x005a0 350 + #define RK3399_WIN2_YUV2YUV_3X3 0x005c0 351 + #define RK3399_WIN2_YUV2YUV_R2Y 0x005e0 352 + #define RK3399_WIN3_YUV2YUV_Y2R 0x00600 353 + #define RK3399_WIN3_YUV2YUV_3X3 0x00620 354 + #define RK3399_WIN3_YUV2YUV_R2Y 0x00640 355 + #define RK3399_WIN2_LUT_ADDR 0x01000 356 + #define RK3399_WIN3_LUT_ADDR 0x01400 357 + #define RK3399_HWC_LUT_ADDR 0x01800 358 + #define RK3399_CABC_GAMMA_LUT_ADDR 0x01c00 359 + #define RK3399_GAMMA_LUT_ADDR 0x02000 360 + /* rk3399 register definition end */ 361 + 169 362 #endif /* _ROCKCHIP_VOP_REG_H */