ntb: fix SKX NTB config space size register offsets

The offsets for the SZ registers are wrong. Updated.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Reported-by: Sandeep Mann <sandeep@purestorage.com>
Tested-by: Zachary Ross <zacharyx.ross@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>

authored by Dave Jiang and committed by Jon Mason 09e71a6f 5c43c52d

+4 -4
+4 -4
drivers/ntb/hw/intel/ntb_hw_intel.h
··· 152 #define XEON_SPAD_COUNT 16 153 154 /* Intel Skylake Xeon hardware */ 155 - #define SKX_IMBAR1SZ_OFFSET 0x00d1 156 - #define SKX_IMBAR2SZ_OFFSET 0x00d5 157 - #define SKX_EMBAR1SZ_OFFSET 0x00d3 158 - #define SKX_EMBAR2SZ_OFFSET 0x00d6 159 #define SKX_DEVCTRL_OFFSET 0x0098 160 #define SKX_DEVSTS_OFFSET 0x009a 161 #define SKX_UNCERRSTS_OFFSET 0x014c
··· 152 #define XEON_SPAD_COUNT 16 153 154 /* Intel Skylake Xeon hardware */ 155 + #define SKX_IMBAR1SZ_OFFSET 0x00d0 156 + #define SKX_IMBAR2SZ_OFFSET 0x00d1 157 + #define SKX_EMBAR1SZ_OFFSET 0x00d2 158 + #define SKX_EMBAR2SZ_OFFSET 0x00d3 159 #define SKX_DEVCTRL_OFFSET 0x0098 160 #define SKX_DEVSTS_OFFSET 0x009a 161 #define SKX_UNCERRSTS_OFFSET 0x014c