tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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Merge tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull Rockchip clk driver updates from Heiko Stuebner:

PLL initialization for PLLs having both an integral and fractional mode
(rk3036, rk3399) does now take into account the mode that the PLL is
actually running at.

As always also some additional and optimized PLL rates for rk3066 and
rk3399, some additional clock ids for rk3066 and some additional clocks
on rk3399 are now sucessfully handled inside their respective driver.

* tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused
clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree
clk: rockchip: add 400MHz to rk3066 clock rates table
clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399
clk: rockchip: Use clock ids for cpu and peri clocks on rk3066
clk: rockchip: Add binding ids for cpu and peri clocks on rk3066
clk: rockchip: add 533.25MHz to rk3399 clock rates table

Stephen Boyd 09d5dc58 a4efb090

+32 -22
+4 -2
drivers/clk/rockchip/clk-pll.c
··· 319 319 320 320 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || 321 321 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || 322 - rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) { 322 + rate->dsmpd != cur.dsmpd || 323 + (!cur.dsmpd && (rate->frac != cur.frac))) { 323 324 struct clk *parent = clk_get_parent(hw->clk); 324 325 325 326 if (!parent) { ··· 796 795 797 796 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || 798 797 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || 799 - rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) { 798 + rate->dsmpd != cur.dsmpd || 799 + (!cur.dsmpd && (rate->frac != cur.frac))) { 800 800 struct clk *parent = clk_get_parent(hw->clk); 801 801 802 802 if (!parent) {
+7 -6
drivers/clk/rockchip/clk-rk3188.c
··· 89 89 RK3066_PLL_RATE( 504000000, 1, 84, 4), 90 90 RK3066_PLL_RATE( 456000000, 1, 76, 4), 91 91 RK3066_PLL_RATE( 408000000, 1, 68, 4), 92 + RK3066_PLL_RATE( 400000000, 3, 100, 2), 92 93 RK3066_PLL_RATE( 384000000, 2, 128, 4), 93 94 RK3066_PLL_RATE( 360000000, 1, 60, 4), 94 95 RK3066_PLL_RATE( 312000000, 1, 52, 4), ··· 307 306 RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 308 307 RK2928_CLKGATE_CON(0), 2, GFLAGS), 309 308 310 - GATE(0, "aclk_cpu", "aclk_cpu_pre", 0, 309 + GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, 311 310 RK2928_CLKGATE_CON(0), 3, GFLAGS), 312 311 313 312 GATE(0, "atclk_cpu", "pclk_cpu_pre", 0, 314 313 RK2928_CLKGATE_CON(0), 6, GFLAGS), 315 - GATE(0, "pclk_cpu", "pclk_cpu_pre", 0, 314 + GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", 0, 316 315 RK2928_CLKGATE_CON(0), 5, GFLAGS), 317 - GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED, 316 + GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED, 318 317 RK2928_CLKGATE_CON(0), 4, GFLAGS), 319 318 320 319 COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, ··· 324 323 RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS, 325 324 RK2928_CLKGATE_CON(1), 4, GFLAGS), 326 325 327 - GATE(0, "aclk_peri", "aclk_peri_pre", 0, 326 + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0, 328 327 RK2928_CLKGATE_CON(2), 1, GFLAGS), 329 - COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_pre", 0, 328 + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", 0, 330 329 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 331 330 RK2928_CLKGATE_CON(2), 2, GFLAGS), 332 - COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0, 331 + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", 0, 333 332 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 334 333 RK2928_CLKGATE_CON(2), 3, GFLAGS), 335 334
+14 -13
drivers/clk/rockchip/clk-rk3399.c
··· 77 77 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 78 78 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 79 79 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 80 - RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 80 + RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), 81 81 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 82 82 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 83 83 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), ··· 87 87 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 88 88 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 89 89 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 90 - RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), 90 + RK3036_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0), 91 91 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 92 92 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 93 93 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), 94 94 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 95 95 RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), 96 + RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0), 96 97 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 97 98 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 98 99 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), ··· 411 410 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED, 412 411 RK3399_CLKGATE_CON(6), 6, GFLAGS), 413 412 414 - GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED, 413 + GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0, 415 414 RK3399_CLKGATE_CON(13), 12, GFLAGS), 416 - GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED, 415 + GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0, 417 416 RK3399_CLKGATE_CON(13), 12, GFLAGS), 418 - MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED, 417 + MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0, 419 418 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS), 420 419 421 420 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0, ··· 499 498 RK3399_CLKGATE_CON(14), 10, GFLAGS), 500 499 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED, 501 500 RK3399_CLKGATE_CON(14), 11, GFLAGS), 502 - GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", CLK_IGNORE_UNUSED, 501 + GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 503 502 RK3399_CLKGATE_CON(0), 7, GFLAGS), 504 503 505 504 /* big core */ ··· 540 539 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, 541 540 RK3399_CLKGATE_CON(14), 2, GFLAGS), 542 541 543 - GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", CLK_IGNORE_UNUSED, 542 + GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0, 544 543 RK3399_CLKGATE_CON(1), 7, GFLAGS), 545 544 546 545 /* gmac */ ··· 676 675 677 676 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED, 678 677 RK3399_CLKGATE_CON(18), 10, GFLAGS), 679 - GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED, 678 + GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0, 680 679 RK3399_CLKGATE_CON(18), 12, GFLAGS), 681 680 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED, 682 681 RK3399_CLKGATE_CON(18), 15, GFLAGS), 683 682 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED, 684 683 RK3399_CLKGATE_CON(19), 2, GFLAGS), 685 684 686 - GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", CLK_IGNORE_UNUSED, 685 + GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0, 687 686 RK3399_CLKGATE_CON(4), 11, GFLAGS), 688 - GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED, 687 + GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0, 689 688 RK3399_CLKGATE_CON(3), 5, GFLAGS), 690 - GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED, 689 + GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0, 691 690 RK3399_CLKGATE_CON(3), 6, GFLAGS), 692 691 693 692 /* cci */ ··· 967 966 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS), 968 967 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS), 969 968 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS), 970 - GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS), 969 + GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS), 971 970 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS), 972 971 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS), 973 972 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS), ··· 981 980 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS), 982 981 983 982 /* pclk_perilp0 gates */ 984 - GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS), 983 + GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS), 985 984 986 985 /* crypto */ 987 986 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
+7 -1
include/dt-bindings/clock/rk3188-cru-common.h
··· 72 72 #define ACLK_IPP 200 73 73 #define ACLK_RGA 201 74 74 #define ACLK_CIF0 202 75 + #define ACLK_CPU 203 76 + #define ACLK_PERI 204 75 77 76 78 /* pclk gates */ 77 79 #define PCLK_GRF 320 ··· 106 104 #define PCLK_EFUSE 347 107 105 #define PCLK_TZPC 348 108 106 #define PCLK_TSADC 349 107 + #define PCLK_CPU 350 108 + #define PCLK_PERI 351 109 109 110 110 /* hclk gates */ 111 111 #define HCLK_SDMMC 448 ··· 130 126 #define HCLK_IPP 465 131 127 #define HCLK_RGA 466 132 128 #define HCLK_NANDC0 467 129 + #define HCLK_CPU 468 130 + #define HCLK_PERI 469 133 131 134 - #define CLK_NR_CLKS (HCLK_NANDC0 + 1) 132 + #define CLK_NR_CLKS (HCLK_PERI + 1) 135 133 136 134 /* soft-reset indices */ 137 135 #define SRST_MCORE 2