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kernel os linux

clock, reset: microchip: move all mpfs reset code to the reset subsystem

Stephen and Philipp, while reviewing patches, said that all of the aux
device creation and the register read/write code could be moved to the
reset subsystem, leaving the clock driver with no implementations of
reset_* functions at all. Move them.

Suggested-by: Philipp Zabel <p.zabel@pengutronix.de>
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240424-strangle-sharpener-34755c5e6e3e@spud
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Conor Dooley and committed by
Stephen Boyd
098c290a 4cece764

+93 -104
+2 -90
drivers/clk/microchip/clk-mpfs.c
··· 4 4 * 5 5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. 6 6 */ 7 - #include <linux/auxiliary_bus.h> 8 7 #include <linux/clk-provider.h> 9 8 #include <linux/io.h> 10 9 #include <linux/module.h> 11 10 #include <linux/platform_device.h> 12 - #include <linux/slab.h> 13 11 #include <dt-bindings/clock/microchip,mpfs-clock.h> 14 12 #include <soc/microchip/mpfs.h> 15 13 ··· 359 361 return 0; 360 362 } 361 363 362 - /* 363 - * Peripheral clock resets 364 - */ 365 - 366 - #if IS_ENABLED(CONFIG_RESET_CONTROLLER) 367 - 368 - u32 mpfs_reset_read(struct device *dev) 369 - { 370 - struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 371 - 372 - return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); 373 - } 374 - EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); 375 - 376 - void mpfs_reset_write(struct device *dev, u32 val) 377 - { 378 - struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 379 - 380 - writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); 381 - } 382 - EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); 383 - 384 - static void mpfs_reset_unregister_adev(void *_adev) 385 - { 386 - struct auxiliary_device *adev = _adev; 387 - 388 - auxiliary_device_delete(adev); 389 - auxiliary_device_uninit(adev); 390 - } 391 - 392 - static void mpfs_reset_adev_release(struct device *dev) 393 - { 394 - struct auxiliary_device *adev = to_auxiliary_dev(dev); 395 - 396 - kfree(adev); 397 - } 398 - 399 - static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data) 400 - { 401 - struct auxiliary_device *adev; 402 - int ret; 403 - 404 - adev = kzalloc(sizeof(*adev), GFP_KERNEL); 405 - if (!adev) 406 - return ERR_PTR(-ENOMEM); 407 - 408 - adev->name = "reset-mpfs"; 409 - adev->dev.parent = clk_data->dev; 410 - adev->dev.release = mpfs_reset_adev_release; 411 - adev->id = 666u; 412 - 413 - ret = auxiliary_device_init(adev); 414 - if (ret) { 415 - kfree(adev); 416 - return ERR_PTR(ret); 417 - } 418 - 419 - return adev; 420 - } 421 - 422 - static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 423 - { 424 - struct auxiliary_device *adev; 425 - int ret; 426 - 427 - adev = mpfs_reset_adev_alloc(clk_data); 428 - if (IS_ERR(adev)) 429 - return PTR_ERR(adev); 430 - 431 - ret = auxiliary_device_add(adev); 432 - if (ret) { 433 - auxiliary_device_uninit(adev); 434 - return ret; 435 - } 436 - 437 - return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev); 438 - } 439 - 440 - #else /* !CONFIG_RESET_CONTROLLER */ 441 - 442 - static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 443 - { 444 - return 0; 445 - } 446 - 447 - #endif /* !CONFIG_RESET_CONTROLLER */ 448 - 449 364 static int mpfs_clk_probe(struct platform_device *pdev) 450 365 { 451 366 struct device *dev = &pdev->dev; ··· 410 499 if (ret) 411 500 return ret; 412 501 413 - return mpfs_reset_controller_register(clk_data); 502 + return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RESET_CR); 414 503 } 415 504 416 505 static const struct of_device_id mpfs_clk_of_match_table[] = { ··· 443 532 MODULE_AUTHOR("Padmarao Begari <padmarao.begari@microchip.com>"); 444 533 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>"); 445 534 MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>"); 535 + MODULE_IMPORT_NS(MCHP_CLK_MPFS);
+86 -9
drivers/reset/reset-mpfs.c
··· 8 8 */ 9 9 #include <linux/auxiliary_bus.h> 10 10 #include <linux/delay.h> 11 + #include <linux/io.h> 11 12 #include <linux/module.h> 12 13 #include <linux/of.h> 13 14 #include <linux/platform_device.h> 15 + #include <linux/slab.h> 14 16 #include <linux/reset-controller.h> 15 17 #include <dt-bindings/clock/microchip,mpfs-clock.h> 16 18 #include <soc/microchip/mpfs.h> ··· 30 28 /* block concurrent access to the soft reset register */ 31 29 static DEFINE_SPINLOCK(mpfs_reset_lock); 32 30 31 + struct mpfs_reset { 32 + void __iomem *base; 33 + struct reset_controller_dev rcdev; 34 + }; 35 + 36 + static inline struct mpfs_reset *to_mpfs_reset(struct reset_controller_dev *rcdev) 37 + { 38 + return container_of(rcdev, struct mpfs_reset, rcdev); 39 + } 40 + 33 41 /* 34 42 * Peripheral clock resets 35 43 */ 36 - 37 44 static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id) 38 45 { 46 + struct mpfs_reset *rst = to_mpfs_reset(rcdev); 39 47 unsigned long flags; 40 48 u32 reg; 41 49 42 50 spin_lock_irqsave(&mpfs_reset_lock, flags); 43 51 44 - reg = mpfs_reset_read(rcdev->dev); 52 + reg = readl(rst->base); 45 53 reg |= BIT(id); 46 - mpfs_reset_write(rcdev->dev, reg); 54 + writel(reg, rst->base); 47 55 48 56 spin_unlock_irqrestore(&mpfs_reset_lock, flags); 49 57 ··· 62 50 63 51 static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id) 64 52 { 53 + struct mpfs_reset *rst = to_mpfs_reset(rcdev); 65 54 unsigned long flags; 66 55 u32 reg; 67 56 68 57 spin_lock_irqsave(&mpfs_reset_lock, flags); 69 58 70 - reg = mpfs_reset_read(rcdev->dev); 59 + reg = readl(rst->base); 71 60 reg &= ~BIT(id); 72 - mpfs_reset_write(rcdev->dev, reg); 61 + writel(reg, rst->base); 73 62 74 63 spin_unlock_irqrestore(&mpfs_reset_lock, flags); 75 64 ··· 79 66 80 67 static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id) 81 68 { 82 - u32 reg = mpfs_reset_read(rcdev->dev); 69 + struct mpfs_reset *rst = to_mpfs_reset(rcdev); 70 + u32 reg = readl(rst->base); 83 71 84 72 /* 85 73 * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit ··· 135 121 { 136 122 struct device *dev = &adev->dev; 137 123 struct reset_controller_dev *rcdev; 124 + struct mpfs_reset *rst; 138 125 139 - rcdev = devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL); 140 - if (!rcdev) 126 + rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); 127 + if (!rst) 141 128 return -ENOMEM; 142 129 130 + rst->base = (void __iomem *)adev->dev.platform_data; 131 + 132 + rcdev = &rst->rcdev; 143 133 rcdev->dev = dev; 144 134 rcdev->dev->parent = dev->parent; 145 135 rcdev->ops = &mpfs_reset_ops; ··· 155 137 return devm_reset_controller_register(dev, rcdev); 156 138 } 157 139 140 + static void mpfs_reset_unregister_adev(void *_adev) 141 + { 142 + struct auxiliary_device *adev = _adev; 143 + 144 + auxiliary_device_delete(adev); 145 + auxiliary_device_uninit(adev); 146 + } 147 + 148 + static void mpfs_reset_adev_release(struct device *dev) 149 + { 150 + struct auxiliary_device *adev = to_auxiliary_dev(dev); 151 + 152 + kfree(adev); 153 + } 154 + 155 + static struct auxiliary_device *mpfs_reset_adev_alloc(struct device *clk_dev) 156 + { 157 + struct auxiliary_device *adev; 158 + int ret; 159 + 160 + adev = kzalloc(sizeof(*adev), GFP_KERNEL); 161 + if (!adev) 162 + return ERR_PTR(-ENOMEM); 163 + 164 + adev->name = "reset-mpfs"; 165 + adev->dev.parent = clk_dev; 166 + adev->dev.release = mpfs_reset_adev_release; 167 + adev->id = 666u; 168 + 169 + ret = auxiliary_device_init(adev); 170 + if (ret) { 171 + kfree(adev); 172 + return ERR_PTR(ret); 173 + } 174 + 175 + return adev; 176 + } 177 + 178 + int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base) 179 + { 180 + struct auxiliary_device *adev; 181 + int ret; 182 + 183 + adev = mpfs_reset_adev_alloc(clk_dev); 184 + if (IS_ERR(adev)) 185 + return PTR_ERR(adev); 186 + 187 + ret = auxiliary_device_add(adev); 188 + if (ret) { 189 + auxiliary_device_uninit(adev); 190 + return ret; 191 + } 192 + 193 + adev->dev.platform_data = (__force void *)base; 194 + 195 + return devm_add_action_or_reset(clk_dev, mpfs_reset_unregister_adev, adev); 196 + } 197 + EXPORT_SYMBOL_NS_GPL(mpfs_reset_controller_register, MCHP_CLK_MPFS); 198 + 158 199 static const struct auxiliary_device_id mpfs_reset_ids[] = { 159 200 { 160 - .name = "clk_mpfs.reset-mpfs", 201 + .name = "reset_mpfs.reset-mpfs", 161 202 }, 162 203 { } 163 204 };
+5 -5
include/soc/microchip/mpfs.h
··· 43 43 #endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */ 44 44 45 45 #if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) 46 - 47 - u32 mpfs_reset_read(struct device *dev); 48 - 49 - void mpfs_reset_write(struct device *dev, u32 val); 50 - 46 + #if IS_ENABLED(CONFIG_RESET_CONTROLLER) 47 + int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base); 48 + #else 49 + static inline int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base) { return 0; } 50 + #endif /* if IS_ENABLED(CONFIG_RESET_CONTROLLER) */ 51 51 #endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */ 52 52 53 53 #endif /* __SOC_MPFS_H__ */