drm/amd/display: Read VBIOS Golden Settings Tbl

+2

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

··· 2834 2834 .bios_parser_destroy = bios_parser_destroy, 2835 2835 2836 2836 .get_board_layout_info = bios_get_board_layout_info, 2837 + 2838 + .get_atom_dc_golden_table = NULL 2837 2839 }; 2838 2840 2839 2841 static bool bios_parser_construct(

+81

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

··· 2079 2079 return 0; 2080 2080 } 2081 2081 2082 + static struct atom_dc_golden_table_v1 *bios_get_golden_table( 2083 + struct bios_parser *bp, 2084 + uint32_t rev_major, 2085 + uint32_t rev_minor, 2086 + uint16_t *dc_golden_table_ver) 2087 + { 2088 + struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 2089 + uint32_t dc_golden_offset = 0; 2090 + *dc_golden_table_ver = 0; 2091 + 2092 + if (!DATA_TABLES(dce_info)) 2093 + return NULL; 2094 + 2095 + /* ver.4.4 or higher */ 2096 + switch (rev_major) { 2097 + case 4: 2098 + switch (rev_minor) { 2099 + case 4: 2100 + disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 2101 + DATA_TABLES(dce_info)); 2102 + if (!disp_cntl_tbl_4_4) 2103 + return NULL; 2104 + dc_golden_offset = disp_cntl_tbl_4_4->dc_golden_table_offset; 2105 + *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 2106 + break; 2107 + } 2108 + break; 2109 + } 2110 + 2111 + if (!dc_golden_offset) 2112 + return NULL; 2113 + 2114 + if (*dc_golden_table_ver != 1) 2115 + return NULL; 2116 + 2117 + return GET_IMAGE(struct atom_dc_golden_table_v1, 2118 + dc_golden_offset); 2119 + } 2120 + 2121 + static enum bp_result bios_get_atom_dc_golden_table( 2122 + struct dc_bios *dcb) 2123 + { 2124 + struct bios_parser *bp = BP_FROM_DCB(dcb); 2125 + enum bp_result result = BP_RESULT_OK; 2126 + struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 2127 + struct atom_common_table_header *header; 2128 + struct atom_data_revision tbl_revision; 2129 + uint16_t dc_golden_table_ver = 0; 2130 + 2131 + header = GET_IMAGE(struct atom_common_table_header, 2132 + DATA_TABLES(dce_info)); 2133 + if (!header) 2134 + return BP_RESULT_UNSUPPORTED; 2135 + 2136 + get_atom_data_table_revision(header, &tbl_revision); 2137 + 2138 + atom_dc_golden_table = bios_get_golden_table(bp, 2139 + tbl_revision.major, 2140 + tbl_revision.minor, 2141 + &dc_golden_table_ver); 2142 + 2143 + if (!atom_dc_golden_table) 2144 + return BP_RESULT_UNSUPPORTED; 2145 + 2146 + dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 2147 + dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 2148 + dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 2149 + dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 2150 + dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 2151 + dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 2152 + dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 2153 + dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 2154 + dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 2155 + dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 2156 + 2157 + return result; 2158 + } 2159 + 2160 + 2082 2161 static const struct dc_vbios_funcs vbios_funcs = { 2083 2162 .get_connectors_number = bios_parser_get_connectors_number, 2084 2163 ··· 2207 2128 2208 2129 .get_board_layout_info = bios_get_board_layout_info, 2209 2130 .pack_data_tables = bios_parser_pack_data_tables, 2131 + 2132 + .get_atom_dc_golden_table = bios_get_atom_dc_golden_table 2210 2133 }; 2211 2134 2212 2135 static bool bios_parser2_construct(

+3

drivers/gpu/drm/amd/display/dc/core/dc_link.c

··· 1540 1540 } 1541 1541 } 1542 1542 1543 + if (bios->funcs->get_atom_dc_golden_table) 1544 + bios->funcs->get_atom_dc_golden_table(bios); 1545 + 1543 1546 /* 1544 1547 * TODO check if GPIO programmed correctly 1545 1548 *

+4

drivers/gpu/drm/amd/display/dc/dc_bios_types.h

··· 133 133 uint16_t (*pack_data_tables)( 134 134 struct dc_bios *dcb, 135 135 void *dst); 136 + 137 + enum bp_result (*get_atom_dc_golden_table)( 138 + struct dc_bios *dcb); 136 139 }; 137 140 138 141 struct bios_registers { ··· 157 154 struct dc_firmware_info fw_info; 158 155 bool fw_info_valid; 159 156 struct dc_vram_info vram_info; 157 + struct dc_golden_table golden_table; 160 158 }; 161 159 162 160 #endif /* DC_BIOS_TYPES_H */

+14

drivers/gpu/drm/amd/display/dc/dc_types.h

··· 890 890 uint32_t branch_max_line_width; 891 891 }; 892 892 893 + struct dc_golden_table { 894 + uint16_t dc_golden_table_ver; 895 + uint32_t aux_dphy_rx_control0_val; 896 + uint32_t aux_dphy_tx_control_val; 897 + uint32_t aux_dphy_rx_control1_val; 898 + uint32_t dc_gpio_aux_ctrl_0_val; 899 + uint32_t dc_gpio_aux_ctrl_1_val; 900 + uint32_t dc_gpio_aux_ctrl_2_val; 901 + uint32_t dc_gpio_aux_ctrl_3_val; 902 + uint32_t dc_gpio_aux_ctrl_4_val; 903 + uint32_t dc_gpio_aux_ctrl_5_val; 904 + }; 905 + 906 + 893 907 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 894 908 enum dc_gpu_mem_alloc_type { 895 909 DC_MEM_ALLOC_TYPE_GART,

+3 -1

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h

··· 38 38 39 39 #define AUX_REG_LIST(id)\ 40 40 SRI(AUX_CONTROL, DP_AUX, id), \ 41 - SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id) 41 + SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \ 42 + SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id) 42 43 43 44 #define HPD_REG_LIST(id)\ 44 45 SRI(DC_HPD_CONTROL, HPD, id) ··· 108 107 struct dce110_link_enc_aux_registers { 109 108 uint32_t AUX_CONTROL; 110 109 uint32_t AUX_DPHY_RX_CONTROL0; 110 + uint32_t AUX_DPHY_RX_CONTROL1; 111 111 }; 112 112 113 113 struct dce110_link_enc_hpd_registers {

+7 -3

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

··· 31 31 #define TO_DCN10_LINK_ENC(link_encoder)\ 32 32 container_of(link_encoder, struct dcn10_link_encoder, base) 33 33 34 - 35 34 #define AUX_REG_LIST(id)\ 36 35 SRI(AUX_CONTROL, DP_AUX, id), \ 37 - SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id) 36 + SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \ 37 + SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id) 38 38 39 39 #define HPD_REG_LIST(id)\ 40 40 SRI(DC_HPD_CONTROL, HPD, id) ··· 73 73 uint32_t AUX_CONTROL; 74 74 uint32_t AUX_DPHY_RX_CONTROL0; 75 75 uint32_t AUX_DPHY_TX_CONTROL; 76 + uint32_t AUX_DPHY_RX_CONTROL1; 76 77 }; 77 78 78 79 struct dcn10_link_enc_hpd_registers { ··· 444 443 type AUX_TX_PRECHARGE_LEN; \ 445 444 type AUX_TX_PRECHARGE_SYMBOLS; \ 446 445 type AUX_MODE_DET_CHECK_DELAY;\ 447 - type DPCS_DBG_CBUS_DIS 446 + type DPCS_DBG_CBUS_DIS;\ 447 + type AUX_RX_PRECHARGE_SKIP;\ 448 + type AUX_RX_TIMEOUT_LEN;\ 449 + type AUX_RX_TIMEOUT_LEN_MUL 448 450 449 451 struct dcn10_link_enc_shift { 450 452 DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);

+11 -3

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c

··· 309 309 void enc2_hw_init(struct link_encoder *enc) 310 310 { 311 311 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 312 - 313 312 /* 314 313 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2 315 314 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4 ··· 332 333 AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3 333 334 AUX_RX_DETECTION_THRESHOLD [30:28] = 1 334 335 */ 335 - AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110); 336 + if (enc->ctx->dc_bios->golden_table.dc_golden_table_ver > 0) { 337 + AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, enc->ctx->dc_bios->golden_table.aux_dphy_rx_control0_val); 336 338 337 - AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a); 339 + AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, enc->ctx->dc_bios->golden_table.aux_dphy_tx_control_val); 340 + 341 + AUX_REG_WRITE(AUX_DPHY_RX_CONTROL1, enc->ctx->dc_bios->golden_table.aux_dphy_rx_control1_val); 342 + } else { 343 + AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110); 344 + 345 + AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c4d); 346 + 347 + } 338 348 339 349 //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32; 340 350 // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk

+4 -1

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h

··· 191 191 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \ 192 192 LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\ 193 193 LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\ 194 - LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh) 194 + LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\ 195 + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\ 196 + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\ 197 + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh) 195 198 196 199 #define UNIPHY_DCN2_REG_LIST(id) \ 197 200 SRI(CLOCK_ENABLE, SYMCLK, id), \

+53 -1

drivers/gpu/drm/amd/include/atomfirmware.h

··· 941 941 uint8_t reserved3[8]; 942 942 }; 943 943 944 - 945 944 struct atom_display_controller_info_v4_2 946 945 { 947 946 struct atom_common_table_header table_header; ··· 975 976 uint8_t reserved3[8]; 976 977 }; 977 978 979 + struct atom_display_controller_info_v4_4 { 980 + struct atom_common_table_header table_header; 981 + uint32_t display_caps; 982 + uint32_t bootup_dispclk_10khz; 983 + uint16_t dce_refclk_10khz; 984 + uint16_t i2c_engine_refclk_10khz; 985 + uint16_t dvi_ss_percentage; // in unit of 0.001% 986 + uint16_t dvi_ss_rate_10hz; 987 + uint16_t hdmi_ss_percentage; // in unit of 0.001% 988 + uint16_t hdmi_ss_rate_10hz; 989 + uint16_t dp_ss_percentage; // in unit of 0.001% 990 + uint16_t dp_ss_rate_10hz; 991 + uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 992 + uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 993 + uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 994 + uint8_t ss_reserved; 995 + uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 996 + uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 997 + uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 998 + uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 999 + uint16_t dpphy_refclk_10khz; 1000 + uint16_t hw_chip_id; 1001 + uint8_t dcnip_min_ver; 1002 + uint8_t dcnip_max_ver; 1003 + uint8_t max_disp_pipe_num; 1004 + uint8_t max_vbios_active_disp_pipum; 1005 + uint8_t max_ppll_num; 1006 + uint8_t max_disp_phy_num; 1007 + uint8_t max_aux_pairs; 1008 + uint8_t remotedisplayconfig; 1009 + uint32_t dispclk_pll_vco_freq; 1010 + uint32_t dp_ref_clk_freq; 1011 + uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) 1012 + uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) 1013 + uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) 1014 + uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx 1015 + uint16_t dc_golden_table_ver; 1016 + uint32_t reserved3[3]; 1017 + }; 1018 + 1019 + struct atom_dc_golden_table_v1 1020 + { 1021 + uint32_t aux_dphy_rx_control0_val; 1022 + uint32_t aux_dphy_tx_control_val; 1023 + uint32_t aux_dphy_rx_control1_val; 1024 + uint32_t dc_gpio_aux_ctrl_0_val; 1025 + uint32_t dc_gpio_aux_ctrl_1_val; 1026 + uint32_t dc_gpio_aux_ctrl_2_val; 1027 + uint32_t dc_gpio_aux_ctrl_3_val; 1028 + uint32_t dc_gpio_aux_ctrl_4_val; 1029 + uint32_t dc_gpio_aux_ctrl_5_val; 1030 + uint32_t reserved[23]; 1031 + }; 978 1032 979 1033 enum dce_info_caps_def 980 1034 {