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Staging: winbond: phy_calibration.h coding style cleanup.
I fixed all checkpatch.pl problems, removed versioning comments and
"commented away" code.
Signed-off-by: Lars Lindley <lindley@coyote.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Pekka Enberg <penberg@cs.helsinki.fi>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
authored by
Lars Lindley
and committed by
Greg Kroah-Hartman
0970305a
8eb3e22e
+66
-89
+66
-89
drivers/staging/winbond/phy_calibration.h
+66
-89
drivers/staging/winbond/phy_calibration.h
···
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#include "wbhal_f.h"
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// 20031229 Turbo add
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#define REG_AGC_CTRL1 0x1000
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#define REG_AGC_CTRL2 0x1004
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#define REG_AGC_CTRL3 0x1008
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#define REG_AGC_CTRL4 0x100C
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#define REG_AGC_CTRL5 0x1010
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#define REG_AGC_CTRL6 0x1014
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#define REG_AGC_CTRL7 0x1018
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#define REG_AGC_CTRL8 0x101C
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#define REG_AGC_CTRL9 0x1020
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#define REG_AGC_CTRL10 0x1024
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#define REG_CCA_CTRL 0x1028
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#define REG_A_ACQ_CTRL 0x102C
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#define REG_B_ACQ_CTRL 0x1030
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#define REG_A_TXRX_CTRL 0x1034
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#define REG_B_TXRX_CTRL 0x1038
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#define REG_A_TX_COEF3 0x103C
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#define REG_A_TX_COEF2 0x1040
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#define REG_A_TX_COEF1 0x1044
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#define REG_B_TX_COEF2 0x1048
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#define REG_B_TX_COEF1 0x104C
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#define REG_MODE_CTRL 0x1050
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#define REG_CALIB_DATA 0x1054
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#define REG_IQ_ALPHA 0x1058
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#define REG_DC_CANCEL 0x105C
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#define REG_WTO_READ 0x1060
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#define REG_OFFSET_READ 0x1064
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#define REG_CALIB_READ1 0x1068
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#define REG_CALIB_READ2 0x106C
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#define REG_A_FREQ_EST 0x1070
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#define REG_AGC_CTRL1 0x1000
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#define REG_AGC_CTRL2 0x1004
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#define REG_AGC_CTRL3 0x1008
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#define REG_AGC_CTRL4 0x100C
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#define REG_AGC_CTRL5 0x1010
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#define REG_AGC_CTRL6 0x1014
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#define REG_AGC_CTRL7 0x1018
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#define REG_AGC_CTRL8 0x101C
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#define REG_AGC_CTRL9 0x1020
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#define REG_AGC_CTRL10 0x1024
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#define REG_CCA_CTRL 0x1028
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#define REG_A_ACQ_CTRL 0x102C
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#define REG_B_ACQ_CTRL 0x1030
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#define REG_A_TXRX_CTRL 0x1034
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#define REG_B_TXRX_CTRL 0x1038
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#define REG_A_TX_COEF3 0x103C
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#define REG_A_TX_COEF2 0x1040
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#define REG_A_TX_COEF1 0x1044
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#define REG_B_TX_COEF2 0x1048
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#define REG_B_TX_COEF1 0x104C
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#define REG_MODE_CTRL 0x1050
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#define REG_CALIB_DATA 0x1054
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#define REG_IQ_ALPHA 0x1058
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#define REG_DC_CANCEL 0x105C
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#define REG_WTO_READ 0x1060
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#define REG_OFFSET_READ 0x1064
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#define REG_CALIB_READ1 0x1068
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#define REG_CALIB_READ2 0x106C
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#define REG_A_FREQ_EST 0x1070
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#define MASK_AMER_OFF_REG BIT(31)
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#define MASK_BMER_OFF_REG BIT(31)
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// 20031101 Turbo add
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#define MASK_AMER_OFF_REG BIT(31)
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#define MASK_LNA_FIX_GAIN (BIT(3) | BIT(4))
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#define MASK_AGC_FIX BIT(1)
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#define MASK_BMER_OFF_REG BIT(31)
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#define MASK_AGC_FIX_GAIN 0xFF00
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#define MASK_LNA_FIX_GAIN (BIT(3)|BIT(4))
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#define MASK_AGC_FIX BIT(1)
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#define MASK_ADC_DC_CAL_STR BIT(10)
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#define MASK_CALIB_START BIT(4)
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#define MASK_IQCAL_TONE_SEL (BIT(3) | BIT(2))
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#define MASK_IQCAL_MODE (BIT(1) | BIT(0))
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#define MASK_AGC_FIX_GAIN 0xFF00
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#define MASK_TX_CAL_0 0xF0000000
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#define TX_CAL_0_SHIFT 28
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#define MASK_TX_CAL_1 0x0F000000
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#define TX_CAL_1_SHIFT 24
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#define MASK_TX_CAL_2 0x00F00000
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#define TX_CAL_2_SHIFT 20
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#define MASK_TX_CAL_3 0x000F0000
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#define TX_CAL_3_SHIFT 16
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#define MASK_RX_CAL_0 0x0000F000
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#define RX_CAL_0_SHIFT 12
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#define MASK_RX_CAL_1 0x00000F00
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#define RX_CAL_1_SHIFT 8
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#define MASK_RX_CAL_2 0x000000F0
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#define RX_CAL_2_SHIFT 4
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#define MASK_RX_CAL_3 0x0000000F
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#define RX_CAL_3_SHIFT 0
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#define MASK_ADC_DC_CAL_STR BIT(10)
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#define MASK_CALIB_START BIT(4)
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#define MASK_IQCAL_TONE_SEL (BIT(3)|BIT(2))
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#define MASK_IQCAL_MODE (BIT(1)|BIT(0))
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#define MASK_CANCEL_DC_I 0x3E0
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#define CANCEL_DC_I_SHIFT 5
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#define MASK_CANCEL_DC_Q 0x01F
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#define CANCEL_DC_Q_SHIFT 0
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#define MASK_TX_CAL_0 0xF0000000
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#define TX_CAL_0_SHIFT 28
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#define MASK_TX_CAL_1 0x0F000000
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#define TX_CAL_1_SHIFT 24
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#define MASK_TX_CAL_2 0x00F00000
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#define TX_CAL_2_SHIFT 20
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#define MASK_TX_CAL_3 0x000F0000
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#define TX_CAL_3_SHIFT 16
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#define MASK_RX_CAL_0 0x0000F000
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#define RX_CAL_0_SHIFT 12
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#define MASK_RX_CAL_1 0x00000F00
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#define RX_CAL_1_SHIFT 8
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#define MASK_RX_CAL_2 0x000000F0
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#define RX_CAL_2_SHIFT 4
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#define MASK_RX_CAL_3 0x0000000F
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#define RX_CAL_3_SHIFT 0
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#define MASK_ADC_DC_CAL_I(x) (((x) & 0x0003FE00) >> 9)
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#define MASK_ADC_DC_CAL_Q(x) ((x) & 0x000001FF)
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#define MASK_CANCEL_DC_I 0x3E0
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#define CANCEL_DC_I_SHIFT 5
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#define MASK_CANCEL_DC_Q 0x01F
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#define CANCEL_DC_Q_SHIFT 0
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#define MASK_IQCAL_TONE_I 0x00001FFF
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#define SHIFT_IQCAL_TONE_I(x) ((x) >> 0)
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#define MASK_IQCAL_TONE_Q 0x03FFE000
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#define SHIFT_IQCAL_TONE_Q(x) ((x) >> 13)
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// LA20040210 kevin
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//#define MASK_ADC_DC_CAL_I(x) (((x)&0x1FE00)>>9)
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//#define MASK_ADC_DC_CAL_Q(x) ((x)&0x1FF)
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#define MASK_ADC_DC_CAL_I(x) (((x)&0x0003FE00)>>9)
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#define MASK_ADC_DC_CAL_Q(x) ((x)&0x000001FF)
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// LA20040210 kevin (Turbo has wrong definition)
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//#define MASK_IQCAL_TONE_I 0x7FFC000
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//#define SHIFT_IQCAL_TONE_I(x) ((x)>>13)
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//#define MASK_IQCAL_TONE_Q 0x1FFF
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//#define SHIFT_IQCAL_TONE_Q(x) ((x)>>0)
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#define MASK_IQCAL_TONE_I 0x00001FFF
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#define SHIFT_IQCAL_TONE_I(x) ((x)>>0)
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#define MASK_IQCAL_TONE_Q 0x03FFE000
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#define SHIFT_IQCAL_TONE_Q(x) ((x)>>13)
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// LA20040210 kevin (Turbo has wrong definition)
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//#define MASK_IQCAL_IMAGE_I 0x7FFC000
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//#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>13)
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//#define MASK_IQCAL_IMAGE_Q 0x1FFF
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//#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>0)
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//#define MASK_IQCAL_IMAGE_I 0x00001FFF
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//#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>0)
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//#define MASK_IQCAL_IMAGE_Q 0x03FFE000
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//#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>13)
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void phy_set_rf_data( struct hw_data * pHwData, u32 index, u32 value );
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#define phy_init_rf( _A ) //RFSynthesizer_initial( _A )
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void phy_set_rf_data(struct hw_data *pHwData, u32 index, u32 value);
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#define phy_init_rf(_A) /* RFSynthesizer_initial(_A) */
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#endif