Merge tag 'imx-dt-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

+2

arch/arm/boot/dts/Makefile

··· 586 586 imx7d-colibri-emmc-eval-v3.dtb \ 587 587 imx7d-colibri-eval-v3.dtb \ 588 588 imx7d-mba7.dtb \ 589 + imx7d-meerkat96.dtb \ 589 590 imx7d-nitrogen7.dtb \ 590 591 imx7d-pico-hobbit.dtb \ 591 592 imx7d-pico-pi.dtb \ ··· 603 602 dtb-$(CONFIG_SOC_LS1021A) += \ 604 603 ls1021a-moxa-uc-8410a.dtb \ 605 604 ls1021a-qds.dtb \ 605 + ls1021a-tsn.dtb \ 606 606 ls1021a-twr.dtb 607 607 dtb-$(CONFIG_SOC_VF610) += \ 608 608 vf500-colibri-eval-v3.dtb \

+223 -43

arch/arm/boot/dts/imx53-m53menlo.dts

··· 10 10 model = "MENLO M53 EMBEDDED DEVICE"; 11 11 compatible = "menlo,m53menlo", "fsl,imx53"; 12 12 13 + gpio-keys { 14 + compatible = "gpio-keys"; 15 + pinctrl-0 = <&pinctrl_power_button>; 16 + pinctrl-names = "default"; 17 + 18 + power-button { 19 + label = "Power button"; 20 + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 21 + linux,code = <KEY_POWER>; 22 + }; 23 + }; 24 + 25 + gpio-poweroff { 26 + compatible = "gpio-poweroff"; 27 + pinctrl-0 = <&pinctrl_power_out>; 28 + pinctrl-names = "default"; 29 + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 30 + }; 31 + 13 32 leds { 14 33 compatible = "gpio-leds"; 15 34 pinctrl-names = "default"; ··· 49 30 eth { 50 31 label = "EthLedYe"; 51 32 gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; 52 - linux,default-trigger = "none"; 33 + linux,default-trigger = "netdev"; 53 34 }; 54 35 }; 55 36 ··· 64 45 }; 65 46 }; 66 47 48 + beeper { 49 + compatible = "gpio-beeper"; 50 + pinctrl-0 = <&pinctrl_beeper>; 51 + gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; 52 + }; 53 + 67 54 reg_usbh1_vbus: regulator-usbh1-vbus { 68 55 compatible = "regulator-fixed"; 69 56 regulator-name = "vbus"; 70 57 regulator-min-microvolt = <5000000>; 71 58 regulator-max-microvolt = <5000000>; 72 - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; 59 + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; 60 + enable-active-high; 73 61 }; 74 62 }; 75 63 ··· 100 74 assigned-clock-rates = <133333334>, <33333334>, <33333334>; 101 75 }; 102 76 77 + &ecspi2 { 78 + pinctrl-names = "default"; 79 + pinctrl-0 = <&pinctrl_ecspi2>; 80 + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio2 27 GPIO_ACTIVE_HIGH>; 81 + status = "okay"; 82 + 83 + spidev@0 { 84 + compatible = "menlo,m53cpld"; 85 + spi-max-frequency = <25000000>; 86 + reg = <0>; 87 + }; 88 + 89 + spidev@1 { 90 + compatible = "menlo,m53cpld"; 91 + spi-max-frequency = <25000000>; 92 + reg = <1>; 93 + }; 94 + }; 95 + 103 96 &esdhc1 { 104 97 pinctrl-names = "default"; 105 98 pinctrl-0 = <&pinctrl_esdhc1>; ··· 131 86 pinctrl-names = "default"; 132 87 pinctrl-0 = <&pinctrl_fec>; 133 88 phy-mode = "rmii"; 89 + phy-reset-gpios = <&gpio7 7 GPIO_ACTIVE_LOW>; 134 90 status = "okay"; 91 + }; 92 + 93 + &gpio1 { 94 + gpio-line-names = 95 + "", "", "", "", 96 + "", "", "", "", 97 + "", "", "", "", 98 + "", "", "", "", 99 + "", "", "", "", 100 + "", "", "", "", 101 + "", "", "", "", 102 + "", "", "", ""; 103 + }; 104 + 105 + &gpio2 { 106 + gpio-line-names = 107 + "", "", "", "", 108 + "", "", "", "", 109 + "TestPin_SV2_3", "", "", "", 110 + "", "", "", "", 111 + "", "", "", "", 112 + "", "", "", "", 113 + "", "", "", "", 114 + "", "", "", ""; 115 + }; 116 + 117 + &gpio3 { 118 + gpio-line-names = 119 + "", "", "", "", 120 + "", "", "", "", 121 + "", "", "", "", 122 + "", "", "", "", 123 + "", "", "", "", 124 + "", "", "", "", 125 + "CPLD_JTAG_TDI", "CPLD_JTAG_TMS", "", "", 126 + "", "CPLD_JTAG_TDO", "", ""; 127 + }; 128 + 129 + &gpio5 { 130 + gpio-line-names = 131 + "", "", "", "", 132 + "", "", "", "", 133 + "", "", "", "", 134 + "", "", "", "", 135 + "", "", "CPLD_JTAG_TCK", "KBD_intK", 136 + "CPLD_int", "CPLD_JTAG_internal", "CPLD_D[0]", "CPLD_D[1]", 137 + "CPLD_D[2]", "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", 138 + "CPLD_D[6]", "CPLD_D[7]", "DISP_reset", "KBD_intI"; 139 + }; 140 + 141 + &gpio6 { 142 + gpio-line-names = 143 + "", "", "", "", 144 + "CPLD_reset", "", "", "", 145 + "", "", "", "", 146 + "", "", "", "", 147 + "", "", "", "", 148 + "", "", "", "", 149 + "", "", "", "", 150 + "", "", "", ""; 151 + }; 152 + 153 + &gpio7 { 154 + gpio-line-names = 155 + "", "", "", "", 156 + "", "", "", "", 157 + "", "", "", "", 158 + "", "USB-OTG_OverCurrent", "", "", 159 + "", "", "", "", 160 + "", "", "", "", 161 + "", "", "", "", 162 + "", "", "", ""; 135 163 }; 136 164 137 165 &i2c1 { ··· 254 136 imx53-m53evk { 255 137 hoggrp { 256 138 fsl,pins = < 257 - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 258 - MX53_PAD_EIM_EB3__GPIO2_31 0x1d5 259 - MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5 260 - MX53_PAD_GPIO_19__CCM_CLKO 0x1d5 261 - MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5 262 - MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5 263 - MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5 264 - MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5 265 - MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5 266 - MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5 267 - MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5 268 - MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5 269 - MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5 270 - MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5 139 + MX53_PAD_GPIO_19__CCM_CLKO 0x1e4 140 + MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4 141 + MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4 142 + MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 143 + MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4 144 + MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4 145 + MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4 146 + MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4 147 + MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4 148 + MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4 149 + MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4 150 + MX53_PAD_EIM_D24__GPIO3_24 0x1e4 151 + MX53_PAD_EIM_D25__GPIO3_25 0x1e4 152 + MX53_PAD_EIM_D29__GPIO3_29 0x1e4 153 + MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4 154 + MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4 155 + MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4 156 + MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4 271 157 >; 272 158 }; 273 159 274 160 pinctrl_led: ledgrp { 275 161 fsl,pins = < 276 - MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5 277 - MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5 162 + MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4 163 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4 164 + >; 165 + }; 166 + 167 + pinctrl_beeper: beepergrp { 168 + fsl,pins = < 169 + MX53_PAD_CSI0_DAT17__GPIO6_3 0x1c4 278 170 >; 279 171 }; 280 172 ··· 297 169 298 170 pinctrl_can2: can2grp { 299 171 fsl,pins = < 300 - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4 172 + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4 301 173 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 302 174 >; 303 175 }; 304 176 305 177 pinctrl_display_gpio: display-gpiogrp { 306 178 fsl,pins = < 307 - MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */ 308 - MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */ 179 + MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */ 180 + MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */ 181 + MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */ 182 + 183 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */ 309 184 >; 310 185 }; 311 186 312 187 pinctrl_edt_ft5x06: edt-ft5x06grp { 313 188 fsl,pins = < 314 - MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */ 315 - MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */ 316 - MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */ 189 + MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */ 190 + MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */ 191 + MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */ 192 + >; 193 + }; 194 + 195 + pinctrl_ecspi2: ecspi2grp { 196 + fsl,pins = < 197 + MX53_PAD_EIM_CS0__ECSPI2_SCLK 0xe4 198 + MX53_PAD_EIM_OE__ECSPI2_MISO 0xe4 199 + MX53_PAD_EIM_CS1__ECSPI2_MOSI 0xe4 200 + MX53_PAD_EIM_RW__GPIO2_26 0xe4 201 + MX53_PAD_EIM_LBA__GPIO2_27 0xe4 317 202 >; 318 203 }; 319 204 320 205 pinctrl_esdhc1: esdhc1grp { 321 206 fsl,pins = < 322 - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 323 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 324 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 325 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 326 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 327 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 207 + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4 208 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4 209 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4 210 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4 211 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 212 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4 213 + MX53_PAD_GPIO_1__GPIO1_1 0x1c4 214 + MX53_PAD_GPIO_9__GPIO1_9 0x1e4 328 215 >; 329 216 }; 330 217 331 218 pinctrl_fec: fecgrp { 332 219 fsl,pins = < 333 - MX53_PAD_FEC_MDC__FEC_MDC 0x4 334 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc 335 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 336 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 337 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 338 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 339 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 340 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 341 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 342 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 220 + MX53_PAD_FEC_MDC__FEC_MDC 0x1e4 221 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4 222 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4 223 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4 224 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4 225 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4 226 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4 227 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4 228 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4 229 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4 230 + MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4 231 + MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 343 232 >; 344 233 }; 345 234 ··· 385 240 >; 386 241 }; 387 242 243 + pinctrl_power_button: powerbutgrp { 244 + fsl,pins = < 245 + MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4 246 + >; 247 + }; 248 + 249 + pinctrl_power_out: poweroutgrp { 250 + fsl,pins = < 251 + MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4 252 + >; 253 + }; 254 + 388 255 pinctrl_uart1: uart1grp { 389 256 fsl,pins = < 390 257 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 391 258 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 259 + MX53_PAD_PATA_IORDY__UART1_RTS 0x1e4 260 + MX53_PAD_PATA_RESET_B__UART1_CTS 0x1e4 392 261 >; 393 262 }; 394 263 ··· 410 251 fsl,pins = < 411 252 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 412 253 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 254 + MX53_PAD_PATA_DIOR__UART2_RTS 0x1e4 255 + MX53_PAD_PATA_INTRQ__UART2_CTS 0x1e4 256 + >; 257 + }; 258 + 259 + pinctrl_uart3: uart3grp { 260 + fsl,pins = < 261 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 262 + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 263 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 413 264 >; 414 265 }; 415 266 416 267 pinctrl_usb: usbgrp { 417 268 fsl,pins = < 418 - MX53_PAD_GPIO_2__GPIO1_2 0x1d5 419 - MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5 269 + MX53_PAD_GPIO_2__GPIO1_2 0x1c4 270 + MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1c4 271 + MX53_PAD_GPIO_4__GPIO1_4 0x1c4 272 + MX53_PAD_GPIO_18__GPIO7_13 0x1c4 420 273 >; 421 274 }; 422 275 }; ··· 458 287 &uart1 { 459 288 pinctrl-names = "default"; 460 289 pinctrl-0 = <&pinctrl_uart1>; 290 + uart-has-rtscts; 461 291 status = "okay"; 462 292 }; 463 293 464 294 &uart2 { 465 295 pinctrl-names = "default"; 466 296 pinctrl-0 = <&pinctrl_uart2>; 297 + uart-has-rtscts; 298 + status = "okay"; 299 + }; 300 + 301 + &uart3 { 302 + pinctrl-names = "default"; 303 + pinctrl-0 = <&pinctrl_uart3>; 304 + linux,rs485-enabled-at-boot-time; 467 305 status = "okay"; 468 306 }; 469 307 ··· 481 301 pinctrl-0 = <&pinctrl_usb>; 482 302 vbus-supply = <&reg_usbh1_vbus>; 483 303 phy_type = "utmi"; 484 - dr_mode = "peripheral"; 304 + dr_mode = "host"; 485 305 status = "okay"; 486 306 }; 487 307

+73

arch/arm/boot/dts/imx53-smd.dts

··· 185 185 >; 186 186 }; 187 187 188 + pinctrl_ipu_csi0: ipucsi0grp { 189 + fsl,pins = < 190 + MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1c4 191 + MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1c4 192 + MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1c4 193 + MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1c4 194 + MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1c4 195 + MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1c4 196 + MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1c4 197 + MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1c4 198 + MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1e4 199 + MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1e4 200 + MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1e4 201 + MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1e4 202 + >; 203 + }; 204 + 205 + pinctrl_ov5642: ov5642grp { 206 + fsl,pins = < 207 + MX53_PAD_NANDF_WP_B__GPIO6_9 0x1e4 208 + MX53_PAD_NANDF_RB0__GPIO6_10 0x1e4 209 + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 210 + >; 211 + }; 212 + 188 213 pinctrl_uart1: uart1grp { 189 214 fsl,pins = < 190 215 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 ··· 281 256 camera: ov5642@3c { 282 257 compatible = "ovti,ov5642"; 283 258 reg = <0x3c>; 259 + pinctrl-names = "default"; 260 + pinctrl-0 = <&pinctrl_ov5642>; 261 + assigned-clocks = <&clks IMX5_CLK_SSI_EXT1_SEL>, 262 + <&clks IMX5_CLK_SSI_EXT1_COM_SEL>; 263 + assigned-clock-parents = <&clks IMX5_CLK_PLL2_SW>, 264 + <&clks IMX5_CLK_SSI_EXT1_PODF>; 265 + assigned-clock-rates = <0>, <24000000>; 266 + clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; 267 + clock-names = "xclk"; 268 + DVDD-supply = <&ldo9_reg>; 269 + AVDD-supply = <&ldo7_reg>; 270 + reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; 271 + powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; 272 + 273 + port { 274 + ov5642_to_ipu_csi0: endpoint { 275 + remote-endpoint = <&ipu_csi0_from_parallel_sensor>; 276 + bus-width = <8>; 277 + hsync-active = <1>; 278 + vsync-active = <1>; 279 + }; 280 + }; 284 281 }; 285 282 286 283 pmic: dialog@48 { 287 284 compatible = "dlg,da9053", "dlg,da9052"; 288 285 reg = <0x48>; 286 + interrupt-parent = <&gpio7>; 287 + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 288 + 289 + regulators { 290 + ldo7_reg: ldo7 { 291 + regulator-min-microvolt = <1200000>; 292 + regulator-max-microvolt = <3600000>; 293 + }; 294 + 295 + ldo9_reg: ldo9 { 296 + regulator-min-microvolt = <1250000>; 297 + regulator-max-microvolt = <3650000>; 298 + }; 299 + }; 289 300 }; 290 301 }; 291 302 ··· 331 270 phy-mode = "rmii"; 332 271 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; 333 272 status = "okay"; 273 + }; 274 + 275 + &ipu_csi0_from_parallel_sensor { 276 + remote-endpoint = <&ov5642_to_ipu_csi0>; 277 + data-shift = <12>; /* Lines 19:12 used */ 278 + hsync-active = <1>; 279 + vsync-active = <1>; 280 + }; 281 + 282 + &ipu_csi0 { 283 + pinctrl-names = "default"; 284 + pinctrl-0 = <&pinctrl_ipu_csi0>; 334 285 };

+12

arch/arm/boot/dts/imx53.dtsi

··· 31 31 i2c0 = &i2c1; 32 32 i2c1 = &i2c2; 33 33 i2c2 = &i2c3; 34 + ipu0 = &ipu; 34 35 mmc0 = &esdhc1; 35 36 mmc1 = &esdhc2; 36 37 mmc2 = &esdhc3; ··· 70 69 display-subsystem { 71 70 compatible = "fsl,imx-display-subsystem"; 72 71 ports = <&ipu_di0>, <&ipu_di1>; 72 + }; 73 + 74 + capture_subsystem { 75 + compatible = "fsl,imx-capture-subsystem"; 76 + ports = <&ipu_csi0>, <&ipu_csi1>; 73 77 }; 74 78 75 79 tzic: tz-interrupt-controller@fffc000 { ··· 164 158 165 159 ipu_csi0: port@0 { 166 160 reg = <0>; 161 + 162 + ipu_csi0_from_parallel_sensor: endpoint { 163 + }; 167 164 }; 168 165 169 166 ipu_csi1: port@1 { 170 167 reg = <1>; 168 + 169 + ipu_csi1_from_parallel_sensor: endpoint { 170 + }; 171 171 }; 172 172 173 173 ipu_di0: port@2 {

+12

arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi

··· 1 + // SPDX-License-Identifier: GPL-2.0 OR X11 2 + /* 3 + * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de> 4 + */ 5 + 6 + #include "imx6dl.dtsi" 7 + #include "imx6qdl-kontron-samx6i.dtsi" 8 + 9 + / { 10 + model = "Kontron SMARC sAMX6i Dual-Lite/Solo"; 11 + compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl"; 12 + };

+36

arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi

··· 1 + // SPDX-License-Identifier: GPL-2.0 OR X11 2 + /* 3 + * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de> 4 + */ 5 + 6 + #include "imx6q.dtsi" 7 + #include "imx6qdl-kontron-samx6i.dtsi" 8 + #include <dt-bindings/gpio/gpio.h> 9 + 10 + / { 11 + model = "Kontron SMARC sAMX6i Quad/Dual"; 12 + compatible = "kontron,imx6q-samx6i", "fsl,imx6q"; 13 + }; 14 + 15 + /* Quad/Dual SoMs have 3 chip-select signals */ 16 + &ecspi4 { 17 + fsl,spi-num-chipselects = <3>; 18 + cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>, 19 + <&gpio3 29 GPIO_ACTIVE_HIGH>, 20 + <&gpio3 25 GPIO_ACTIVE_HIGH>; 21 + }; 22 + 23 + &pinctrl_ecspi4 { 24 + fsl,pins = < 25 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 26 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 27 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 28 + 29 + /* SPI4_IMX_CS2# - connected to internal flash */ 30 + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 31 + /* SPI4_IMX_CS0# - connected to SMARC SPI0_CS0# */ 32 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 33 + /* SPI4_CS3# - connected to SMARC SPI0_CS1# */ 34 + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0 35 + >; 36 + };

+815

arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi

··· 1 + // SPDX-License-Identifier: GPL-2.0 OR X11 2 + /* 3 + * Copyright 2017 (C) Priit Laes <plaes@plaes.org> 4 + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de> 5 + * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de> 6 + * 7 + * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru> 8 + */ 9 + 10 + #include <dt-bindings/gpio/gpio.h> 11 + #include <dt-bindings/sound/fsl-imx-audmux.h> 12 + 13 + / { 14 + reg_1p0v_s0: regulator-1p0v-s0 { 15 + compatible = "regulator-fixed"; 16 + regulator-name = "V_1V0_S0"; 17 + regulator-min-microvolt = <1000000>; 18 + regulator-max-microvolt = <1000000>; 19 + regulator-always-on; 20 + regulator-boot-on; 21 + vin-supply = <&reg_smarc_suppy>; 22 + }; 23 + 24 + reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 { 25 + compatible = "regulator-fixed"; 26 + regulator-name = "V_1V35_VCOREDIG_S5"; 27 + regulator-min-microvolt = <1350000>; 28 + regulator-max-microvolt = <1350000>; 29 + regulator-always-on; 30 + regulator-boot-on; 31 + vin-supply = <&reg_3p3v_s5>; 32 + }; 33 + 34 + reg_1p8v_s5: regulator-1p8v-s5 { 35 + compatible = "regulator-fixed"; 36 + regulator-name = "V_1V8_S5"; 37 + regulator-min-microvolt = <1800000>; 38 + regulator-max-microvolt = <1800000>; 39 + regulator-always-on; 40 + regulator-boot-on; 41 + vin-supply = <&reg_3p3v_s5>; 42 + }; 43 + 44 + reg_3p3v_s0: regulator-3p3v-s0 { 45 + compatible = "regulator-fixed"; 46 + regulator-name = "V_3V3_S0"; 47 + regulator-min-microvolt = <3300000>; 48 + regulator-max-microvolt = <3300000>; 49 + regulator-always-on; 50 + regulator-boot-on; 51 + vin-supply = <&reg_3p3v_s5>; 52 + }; 53 + 54 + reg_3p3v_s0: regulator-3p3v-s0 { 55 + compatible = "regulator-fixed"; 56 + regulator-name = "V_3V3_S0"; 57 + regulator-min-microvolt = <3300000>; 58 + regulator-max-microvolt = <3300000>; 59 + regulator-always-on; 60 + regulator-boot-on; 61 + vin-supply = <&reg_3p3v_s5>; 62 + }; 63 + 64 + reg_3p3v_s5: regulator-3p3v-s5 { 65 + compatible = "regulator-fixed"; 66 + regulator-name = "V_3V3_S5"; 67 + regulator-min-microvolt = <3300000>; 68 + regulator-max-microvolt = <3300000>; 69 + regulator-always-on; 70 + regulator-boot-on; 71 + vin-supply = <&reg_smarc_suppy>; 72 + }; 73 + 74 + reg_smarc_lcdbklt: regulator-smarc-lcdbklt { 75 + compatible = "regulator-fixed"; 76 + pinctrl-names = "default"; 77 + pinctrl-0 = <&pinctrl_lcdbklt_en>; 78 + regulator-name = "LCD_BKLT_EN"; 79 + regulator-min-microvolt = <1800000>; 80 + regulator-max-microvolt = <1800000>; 81 + gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; 82 + enable-active-high; 83 + }; 84 + 85 + reg_smarc_lcdvdd: regulator-smarc-lcdvdd { 86 + compatible = "regulator-fixed"; 87 + pinctrl-names = "default"; 88 + pinctrl-0 = <&pinctrl_lcdvdd_en>; 89 + regulator-name = "LCD_VDD_EN"; 90 + regulator-min-microvolt = <1800000>; 91 + regulator-max-microvolt = <1800000>; 92 + gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; 93 + enable-active-high; 94 + }; 95 + 96 + reg_smarc_rtc: regulator-smarc-rtc { 97 + compatible = "regulator-fixed"; 98 + regulator-name = "V_IN_RTC_BATT"; 99 + regulator-min-microvolt = <3300000>; 100 + regulator-max-microvolt = <3300000>; 101 + regulator-always-on; 102 + regulator-boot-on; 103 + }; 104 + 105 + /* Module supply range can be 3.00V ... 5.25V */ 106 + reg_smarc_suppy: regulator-smarc-supply { 107 + compatible = "regulator-fixed"; 108 + regulator-name = "V_IN_WIDE"; 109 + regulator-min-microvolt = <5000000>; 110 + regulator-max-microvolt = <5000000>; 111 + regulator-always-on; 112 + regulator-boot-on; 113 + }; 114 + 115 + lcd: lcd { 116 + #address-cells = <1>; 117 + #size-cells = <0>; 118 + compatible = "fsl,imx-parallel-display"; 119 + pinctrl-names = "default"; 120 + pinctrl-0 = <&pinctrl_lcd>; 121 + status = "disabled"; 122 + 123 + port@0 { 124 + reg = <0>; 125 + 126 + lcd_in: endpoint { 127 + }; 128 + }; 129 + 130 + port@1 { 131 + reg = <1>; 132 + 133 + lcd_out: endpoint { 134 + }; 135 + }; 136 + }; 137 + 138 + lcd_backlight: lcd-backlight { 139 + compatible = "pwm-backlight"; 140 + pwms = <&pwm4 0 5000000>; 141 + pwm-names = "LCD_BKLT_PWM"; 142 + 143 + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; 144 + default-brightness-level = <4>; 145 + 146 + power-supply = <&reg_smarc_lcdbklt>; 147 + status = "disabled"; 148 + }; 149 + 150 + i2c_intern: i2c-gpio-intern { 151 + compatible = "i2c-gpio"; 152 + pinctrl-names = "default"; 153 + pinctrl-0 = <&pinctrl_i2c_gpio_intern>; 154 + sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 155 + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 156 + i2c-gpio,delay-us = <2>; /* ~100 kHz */ 157 + #address-cells = <1>; 158 + #size-cells = <0>; 159 + }; 160 + 161 + i2c_lcd: i2c-gpio-lcd { 162 + compatible = "i2c-gpio"; 163 + pinctrl-names = "default"; 164 + pinctrl-0 = <&pinctrl_i2c_gpio_lcd>; 165 + sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 166 + scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 167 + i2c-gpio,delay-us = <2>; /* ~100 kHz */ 168 + #address-cells = <1>; 169 + #size-cells = <0>; 170 + status = "disabld"; 171 + }; 172 + 173 + i2c_cam: i2c-gpio-cam { 174 + compatible = "i2c-gpio"; 175 + pinctrl-names = "default"; 176 + pinctrl-0 = <&pinctrl_i2c_gpio_cam>; 177 + sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 178 + scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 179 + i2c-gpio,delay-us = <2>; /* ~100 kHz */ 180 + #address-cells = <1>; 181 + #size-cells = <0>; 182 + status = "disabld"; 183 + }; 184 + }; 185 + 186 + /* I2S0, I2S1 */ 187 + &audmux { 188 + pinctrl-names = "default"; 189 + pinctrl-0 = <&pinctrl_audmux>; 190 + 191 + audmux_ssi1 { 192 + fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; 193 + fsl,port-config = < 194 + (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) | 195 + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) | 196 + IMX_AUDMUX_V2_PTCR_SYN | 197 + IMX_AUDMUX_V2_PTCR_TFSDIR | 198 + IMX_AUDMUX_V2_PTCR_TCLKDIR) 199 + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3) 200 + >; 201 + }; 202 + 203 + audmux_adu3 { 204 + fsl,audmux-port = <MX51_AUDMUX_PORT3>; 205 + fsl,port-config = < 206 + IMX_AUDMUX_V2_PTCR_SYN 207 + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) 208 + >; 209 + }; 210 + 211 + audmux_ssi2 { 212 + fsl,audmux-port = <MX51_AUDMUX_PORT2_SSI1>; 213 + fsl,port-config = < 214 + (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | 215 + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | 216 + IMX_AUDMUX_V2_PTCR_SYN | 217 + IMX_AUDMUX_V2_PTCR_TFSDIR | 218 + IMX_AUDMUX_V2_PTCR_TCLKDIR) 219 + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) 220 + >; 221 + }; 222 + 223 + audmux_adu4 { 224 + fsl,audmux-port = <MX51_AUDMUX_PORT4>; 225 + fsl,port-config = < 226 + IMX_AUDMUX_V2_PTCR_SYN 227 + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1) 228 + >; 229 + }; 230 + }; 231 + 232 + /* CAN0 */ 233 + &can1 { 234 + pinctrl-names = "default"; 235 + pinctrl-0 = <&pinctrl_flexcan1>; 236 + }; 237 + 238 + /* CAN1 */ 239 + &can2 { 240 + pinctrl-names = "default"; 241 + pinctrl-0 = <&pinctrl_flexcan2>; 242 + }; 243 + 244 + /* SPI1 */ 245 + &ecspi2 { 246 + pinctrl-names = "default"; 247 + pinctrl-0 = <&pinctrl_ecspi2>; 248 + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, 249 + <&gpio2 27 GPIO_ACTIVE_HIGH>; 250 + }; 251 + 252 + /* SPI0 */ 253 + &ecspi4 { 254 + pinctrl-names = "default"; 255 + pinctrl-0 = <&pinctrl_ecspi4>; 256 + cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>, 257 + <&gpio3 29 GPIO_ACTIVE_HIGH>; 258 + status = "okay"; 259 + 260 + /* default boot source: workaround #1 for errata ERR006282 */ 261 + smarc_flash: spi-flash@0 { 262 + compatible = "winbond,w25q16dw", "jedec,spi-nor"; 263 + reg = <0>; 264 + spi-max-frequency = <20000000>; 265 + }; 266 + }; 267 + 268 + /* GBE */ 269 + &fec { 270 + pinctrl-names = "default"; 271 + pinctrl-0 = <&pinctrl_enet>; 272 + phy-mode = "rgmii"; 273 + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 274 + }; 275 + 276 + &i2c_intern { 277 + pmic@8 { 278 + compatible = "fsl,pfuze100"; 279 + reg = <0x08>; 280 + 281 + regulators { 282 + reg_v_core_s0: sw1ab { 283 + regulator-name = "V_CORE_S0"; 284 + regulator-min-microvolt = <300000>; 285 + regulator-max-microvolt = <1875000>; 286 + regulator-boot-on; 287 + regulator-always-on; 288 + }; 289 + 290 + reg_vddsoc_s0: sw1c { 291 + regulator-name = "V_VDDSOC_S0"; 292 + regulator-min-microvolt = <300000>; 293 + regulator-max-microvolt = <1875000>; 294 + regulator-boot-on; 295 + regulator-always-on; 296 + }; 297 + 298 + reg_3p15v_s0: sw2 { 299 + regulator-name = "V_3V15_S0"; 300 + regulator-min-microvolt = <800000>; 301 + regulator-max-microvolt = <3300000>; 302 + regulator-boot-on; 303 + regulator-always-on; 304 + }; 305 + 306 + /* sw3a/b is used in dual mode, but driver does not 307 + * support it. Although, there's no need to control 308 + * DDR power - so just leaving dummy entries for sw3a 309 + * and sw3b for now. 310 + */ 311 + sw3a { 312 + regulator-min-microvolt = <400000>; 313 + regulator-max-microvolt = <1975000>; 314 + regulator-boot-on; 315 + regulator-always-on; 316 + }; 317 + 318 + sw3b { 319 + regulator-min-microvolt = <400000>; 320 + regulator-max-microvolt = <1975000>; 321 + regulator-boot-on; 322 + regulator-always-on; 323 + }; 324 + 325 + reg_1p8v_s0: sw4 { 326 + regulator-name = "V_1V8_S0"; 327 + regulator-min-microvolt = <800000>; 328 + regulator-max-microvolt = <3300000>; 329 + regulator-boot-on; 330 + regulator-always-on; 331 + }; 332 + 333 + /* Regulator for USB */ 334 + reg_5p0v_s0: swbst { 335 + regulator-name = "V_5V0_S0"; 336 + regulator-min-microvolt = <5000000>; 337 + regulator-max-microvolt = <5150000>; 338 + regulator-boot-on; 339 + }; 340 + 341 + reg_vsnvs: vsnvs { 342 + regulator-min-microvolt = <1000000>; 343 + regulator-max-microvolt = <3000000>; 344 + regulator-boot-on; 345 + regulator-always-on; 346 + }; 347 + 348 + reg_vrefddr: vrefddr { 349 + regulator-boot-on; 350 + regulator-always-on; 351 + }; 352 + 353 + /* 354 + * Per schematics, of all VGEN's, only VGEN5 has some 355 + * usage ... but even that - over DNI resistor 356 + */ 357 + vgen1 { 358 + regulator-min-microvolt = <800000>; 359 + regulator-max-microvolt = <1550000>; 360 + }; 361 + 362 + vgen2 { 363 + regulator-min-microvolt = <800000>; 364 + regulator-max-microvolt = <1550000>; 365 + }; 366 + 367 + vgen3 { 368 + regulator-min-microvolt = <1800000>; 369 + regulator-max-microvolt = <3300000>; 370 + }; 371 + 372 + vgen4 { 373 + regulator-min-microvolt = <1800000>; 374 + regulator-max-microvolt = <3300000>; 375 + }; 376 + 377 + reg_2p5v_s0: vgen5 { 378 + regulator-name = "V_2V5_S0"; 379 + regulator-min-microvolt = <1800000>; 380 + regulator-max-microvolt = <3300000>; 381 + }; 382 + 383 + vgen6 { 384 + regulator-min-microvolt = <1800000>; 385 + regulator-max-microvolt = <3300000>; 386 + }; 387 + }; 388 + }; 389 + }; 390 + 391 + /* I2C_GP */ 392 + &i2c1 { 393 + clock-frequency = <100000>; 394 + pinctrl-names = "default"; 395 + pinctrl-0 = <&pinctrl_i2c1>; 396 + }; 397 + 398 + /* HDMI_CTRL */ 399 + &i2c2 { 400 + clock-frequency = <100000>; 401 + pinctrl-names = "default"; 402 + pinctrl-0 = <&pinctrl_i2c2>; 403 + }; 404 + 405 + /* I2C_PM */ 406 + &i2c3 { 407 + clock-frequency = <100000>; 408 + pinctrl-names = "default"; 409 + pinctrl-0 = <&pinctrl_i2c3>; 410 + status = "okay"; 411 + 412 + smarc_eeprom: eeprom@50 { 413 + compatible = "atmel,24c32"; 414 + reg = <0x50>; 415 + pagesize = <32>; 416 + }; 417 + }; 418 + 419 + &iomuxc { 420 + pinctrl-names = "default"; 421 + pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>; 422 + 423 + pinctrl_audmux: audmuxgrp { 424 + fsl,pins = < 425 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 426 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0 427 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 428 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 429 + 430 + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 431 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 432 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 433 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 434 + 435 + /* AUDIO MCLK */ 436 + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0 437 + >; 438 + }; 439 + 440 + pinctrl_ecspi2: ecspi2grp { 441 + fsl,pins = < 442 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 443 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 444 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 445 + 446 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* CS0 */ 447 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */ 448 + >; 449 + }; 450 + 451 + pinctrl_ecspi4: ecspi4grp { 452 + fsl,pins = < 453 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 454 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 455 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 456 + 457 + /* SPI_IMX_CS2# - connected to internal flash */ 458 + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 459 + /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */ 460 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 461 + >; 462 + }; 463 + 464 + pinctrl_flexcan1: flexcan1grp { 465 + fsl,pins = < 466 + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 467 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 468 + >; 469 + }; 470 + 471 + pinctrl_flexcan2: flexcan2grp { 472 + fsl,pins = < 473 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 474 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 475 + >; 476 + }; 477 + 478 + pinctrl_gpio: gpiogrp { 479 + fsl,pins = < 480 + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /* GPIO0 / CAM0_PWR# */ 481 + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /* GPIO1 / CAM1_PWR# */ 482 + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /* GPIO2 / CAM0_RST# */ 483 + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /* GPIO3 / CAM1_RST# */ 484 + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /* GPIO4 / HDA_RST# */ 485 + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /* GPIO5 / PWM_OUT */ 486 + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /* GPIO6 / TACHIN */ 487 + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /* GPIO7 / PCAM_FLD */ 488 + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /* GPIO8 / CAN0_ERR# */ 489 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /* GPIO9 / CAN1_ERR# */ 490 + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10 */ 491 + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11 */ 492 + >; 493 + }; 494 + 495 + pinctrl_enet: enetgrp { 496 + fsl,pins = < 497 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 498 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 499 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 500 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 501 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 502 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 503 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 504 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 505 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 506 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 507 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 508 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 509 + 510 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 511 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 512 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 513 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */ 514 + >; 515 + }; 516 + 517 + pinctrl_i2c_gpio_cam: i2c-gpiocamgrp { 518 + fsl,pins = < 519 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */ 520 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */ 521 + >; 522 + }; 523 + 524 + pinctrl_i2c_gpio_intern: i2c-gpiointerngrp { 525 + fsl,pins = < 526 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */ 527 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */ 528 + >; 529 + }; 530 + 531 + pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp { 532 + fsl,pins = < 533 + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */ 534 + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */ 535 + >; 536 + }; 537 + 538 + pinctrl_i2c1: i2c1grp { 539 + fsl,pins = < 540 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 541 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 542 + >; 543 + }; 544 + 545 + pinctrl_i2c2: i2c2grp { 546 + fsl,pins = < 547 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 548 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 549 + >; 550 + }; 551 + 552 + pinctrl_i2c3: i2c3grp { 553 + fsl,pins = < 554 + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 555 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 556 + >; 557 + }; 558 + 559 + pinctrl_lcd: lcdgrp { 560 + fsl,pins = < 561 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f1 562 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f1 563 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f1 564 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f1 565 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f1 566 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f1 567 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f1 568 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f1 569 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f1 570 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f1 571 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1 572 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1 573 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1 574 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1 575 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1 576 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1 577 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1 578 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1 579 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1 580 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1 581 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1 582 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1 583 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1 584 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1 585 + 586 + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1 587 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f1 /* DE */ 588 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */ 589 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f1 /* VSYNC */ 590 + >; 591 + }; 592 + 593 + pinctrl_lcdbklt_en: lcdbkltengrp { 594 + fsl,pins = < 595 + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1 596 + >; 597 + }; 598 + 599 + pinctrl_lcdvdd_en: lcdvddengrp { 600 + fsl,pins = < 601 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 602 + >; 603 + }; 604 + 605 + pinctrl_mipi_csi: mipi-csigrp { 606 + fsl,pins = < 607 + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */ 608 + >; 609 + }; 610 + 611 + pinctrl_mgmt_gpios: mgmt-gpiosgrp { 612 + fsl,pins = < 613 + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */ 614 + MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /* SLEEP# */ 615 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* CHARGING# */ 616 + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CHARGER_PRSNT# */ 617 + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 /* CARRIER_STBY# */ 618 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */ 619 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */ 620 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* VDD_IO_SEL_D# */ 621 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* POWER_BTN# */ 622 + >; 623 + }; 624 + 625 + pinctrl_pcie: pciegrp { 626 + fsl,pins = < 627 + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */ 628 + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */ 629 + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */ 630 + >; 631 + }; 632 + 633 + pinctrl_pwm4: pwm4grp { 634 + fsl,pins = < 635 + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 636 + >; 637 + }; 638 + 639 + pinctrl_uart1: uart1grp { 640 + fsl,pins = < 641 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 642 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 643 + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 644 + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 645 + >; 646 + }; 647 + 648 + pinctrl_uart2: uart2grp { 649 + fsl,pins = < 650 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 651 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 652 + >; 653 + }; 654 + 655 + pinctrl_uart4: uart4grp { 656 + fsl,pins = < 657 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 658 + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 659 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 660 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 661 + >; 662 + }; 663 + 664 + pinctrl_uart5: uart5grp { 665 + fsl,pins = < 666 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 667 + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 668 + >; 669 + }; 670 + 671 + pinctrl_usbotg: usbotggrp { 672 + fsl,pins = < 673 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0 674 + /* power, oc muxed but not used by the driver */ 675 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */ 676 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */ 677 + >; 678 + }; 679 + 680 + pinctrl_usdhc3: usdhc3grp { 681 + fsl,pins = < 682 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059 683 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 684 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 685 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 686 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 687 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 688 + 689 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */ 690 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */ 691 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */ 692 + >; 693 + }; 694 + 695 + pinctrl_usdhc4: usdhc4grp { 696 + fsl,pins = < 697 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 698 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 699 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 700 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 701 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 702 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 703 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 704 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 705 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 706 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 707 + >; 708 + }; 709 + 710 + pinctrl_wdog1: wdog1rp { 711 + fsl,pins = < 712 + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 713 + >; 714 + }; 715 + }; 716 + 717 + &mipi_csi { 718 + pinctrl-names = "default"; 719 + pinctrl-0 = <&pinctrl_mipi_csi>; 720 + }; 721 + 722 + &pcie { 723 + pinctrl-names = "default"; 724 + pinctrl-0 = <&pinctrl_pcie>; 725 + wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>; 726 + reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; 727 + }; 728 + 729 + /* LCD_BKLT_PWM */ 730 + &pwm4 { 731 + pinctrl-names = "default"; 732 + pinctrl-0 = <&pinctrl_pwm4>; 733 + }; 734 + 735 + &reg_arm { 736 + vin-supply = <&reg_v_core_s0>; 737 + }; 738 + 739 + &reg_pu { 740 + vin-supply = <&reg_vddsoc_s0>; 741 + }; 742 + 743 + &reg_soc { 744 + vin-supply = <&reg_vddsoc_s0>; 745 + }; 746 + 747 + /* SER0 */ 748 + &uart1 { 749 + pinctrl-names = "default"; 750 + pinctrl-0 = <&pinctrl_uart1>; 751 + uart-has-rtscts; 752 + }; 753 + 754 + /* SER1 */ 755 + &uart2 { 756 + pinctrl-names = "default"; 757 + pinctrl-0 = <&pinctrl_uart2>; 758 + }; 759 + 760 + /* SER2 */ 761 + &uart4 { 762 + pinctrl-names = "default"; 763 + pinctrl-0 = <&pinctrl_uart4>; 764 + uart-has-rtscts; 765 + }; 766 + 767 + /* SER3 */ 768 + &uart5 { 769 + pinctrl-names = "default"; 770 + pinctrl-0 = <&pinctrl_uart5>; 771 + }; 772 + 773 + /* USB0 */ 774 + &usbotg { 775 + /* 776 + * no 'imx6-usb-charger-detection' 777 + * since USB_OTG_CHD_B pin is not wired 778 + */ 779 + pinctrl-names = "default"; 780 + pinctrl-0 = <&pinctrl_usbotg>; 781 + }; 782 + 783 + /* USB1/2 via hub */ 784 + &usbh1 { 785 + vbus-supply = <&reg_5p0v_s0>; 786 + }; 787 + 788 + /* SDIO */ 789 + &usdhc3 { 790 + pinctrl-names = "default"; 791 + pinctrl-0 = <&pinctrl_usdhc3>; 792 + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; 793 + wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 794 + no-1-8-v; 795 + }; 796 + 797 + /* SDMMC */ 798 + &usdhc4 { 799 + /* Internal eMMC, optional on some boards */ 800 + pinctrl-names = "default"; 801 + pinctrl-0 = <&pinctrl_usdhc4>; 802 + bus-width = <8>; 803 + no-sdio; 804 + no-sd; 805 + non-removable; 806 + vmmc-supply = <&reg_3p3v_s0>; 807 + vqmmc-supply = <&reg_1p8v_s0>; 808 + }; 809 + 810 + &wdog1 { 811 + /* CPLD is feeded by watchdog (hardwired) */ 812 + pinctrl-names = "default"; 813 + pinctrl-0 = <&pinctrl_wdog1>; 814 + status = "okay"; 815 + };

+16

arch/arm/boot/dts/imx6qdl-sabresd.dtsi

··· 745 745 vin-supply = <&sw1c_reg>; 746 746 }; 747 747 748 + &reg_vdd1p1 { 749 + vin-supply = <&vgen5_reg>; 750 + }; 751 + 752 + &reg_vdd3p0 { 753 + vin-supply = <&sw2_reg>; 754 + }; 755 + 756 + &reg_vdd2p5 { 757 + vin-supply = <&vgen5_reg>; 758 + }; 759 + 748 760 &snvs_poweroff { 761 + status = "okay"; 762 + }; 763 + 764 + &snvs_pwrkey { 749 765 status = "okay"; 750 766 }; 751 767

+6 -5

arch/arm/boot/dts/imx6qdl.dtsi

··· 675 675 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 676 676 reg = <0x020bc000 0x4000>; 677 677 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 678 - clocks = <&clks IMX6QDL_CLK_DUMMY>; 678 + clocks = <&clks IMX6QDL_CLK_IPG>; 679 679 }; 680 680 681 681 wdog2: wdog@20c0000 { 682 682 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 683 683 reg = <0x020c0000 0x4000>; 684 684 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 685 - clocks = <&clks IMX6QDL_CLK_DUMMY>; 685 + clocks = <&clks IMX6QDL_CLK_IPG>; 686 686 status = "disabled"; 687 687 }; 688 688 ··· 701 701 <0 54 IRQ_TYPE_LEVEL_HIGH>, 702 702 <0 127 IRQ_TYPE_LEVEL_HIGH>; 703 703 704 - regulator-1p1 { 704 + reg_vdd1p1: regulator-1p1 { 705 705 compatible = "fsl,anatop-regulator"; 706 706 regulator-name = "vdd1p1"; 707 707 regulator-min-microvolt = <1000000>; ··· 716 716 anatop-enable-bit = <0>; 717 717 }; 718 718 719 - regulator-3p0 { 719 + reg_vdd3p0: regulator-3p0 { 720 720 compatible = "fsl,anatop-regulator"; 721 721 regulator-name = "vdd3p0"; 722 722 regulator-min-microvolt = <2800000>; ··· 731 731 anatop-enable-bit = <0>; 732 732 }; 733 733 734 - regulator-2p5 { 734 + reg_vdd2p5: regulator-2p5 { 735 735 compatible = "fsl,anatop-regulator"; 736 736 regulator-name = "vdd2p5"; 737 737 regulator-min-microvolt = <2250000>; ··· 841 841 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 842 842 linux,keycode = <KEY_POWER>; 843 843 wakeup-source; 844 + status = "disabled"; 844 845 }; 845 846 846 847 snvs_lpgpr: snvs-lpgpr {

+12

arch/arm/boot/dts/imx6sl-evk.dts

··· 580 580 status = "okay"; 581 581 }; 582 582 583 + &reg_vdd1p1 { 584 + vin-supply = <&sw2_reg>; 585 + }; 586 + 587 + &reg_vdd3p0 { 588 + vin-supply = <&sw2_reg>; 589 + }; 590 + 591 + &reg_vdd2p5 { 592 + vin-supply = <&sw2_reg>; 593 + }; 594 + 583 595 &snvs_poweroff { 584 596 status = "okay"; 585 597 };

+6 -6

arch/arm/boot/dts/imx6sl.dtsi

··· 495 495 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; 496 496 reg = <0x020b8000 0x4000>; 497 497 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 498 - clocks = <&clks IMX6SL_CLK_DUMMY>; 498 + clocks = <&clks IMX6SL_CLK_IPG>; 499 499 status = "disabled"; 500 500 }; 501 501 ··· 503 503 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; 504 504 reg = <0x020bc000 0x4000>; 505 505 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 506 - clocks = <&clks IMX6SL_CLK_DUMMY>; 506 + clocks = <&clks IMX6SL_CLK_IPG>; 507 507 }; 508 508 509 509 wdog2: wdog@20c0000 { 510 510 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; 511 511 reg = <0x020c0000 0x4000>; 512 512 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 513 - clocks = <&clks IMX6SL_CLK_DUMMY>; 513 + clocks = <&clks IMX6SL_CLK_IPG>; 514 514 status = "disabled"; 515 515 }; 516 516 ··· 531 531 <0 54 IRQ_TYPE_LEVEL_HIGH>, 532 532 <0 127 IRQ_TYPE_LEVEL_HIGH>; 533 533 534 - regulator-1p1 { 534 + reg_vdd1p1: regulator-1p1 { 535 535 compatible = "fsl,anatop-regulator"; 536 536 regulator-name = "vdd1p1"; 537 537 regulator-min-microvolt = <1000000>; ··· 546 546 anatop-enable-bit = <0>; 547 547 }; 548 548 549 - regulator-3p0 { 549 + reg_vdd3p0: regulator-3p0 { 550 550 compatible = "fsl,anatop-regulator"; 551 551 regulator-name = "vdd3p0"; 552 552 regulator-min-microvolt = <2800000>; ··· 561 561 anatop-enable-bit = <0>; 562 562 }; 563 563 564 - regulator-2p5 { 564 + reg_vdd2p5: regulator-2p5 { 565 565 compatible = "fsl,anatop-regulator"; 566 566 regulator-name = "vdd2p5"; 567 567 regulator-min-microvolt = <2250000>;

+12

arch/arm/boot/dts/imx6sll-evk.dts

··· 265 265 status = "okay"; 266 266 }; 267 267 268 + &reg_3p0 { 269 + vin-supply = <&sw2_reg>; 270 + }; 271 + 272 + &snvs_poweroff { 273 + status = "okay"; 274 + }; 275 + 276 + &snvs_pwrkey { 277 + status = "okay"; 278 + }; 279 + 268 280 &uart1 { 269 281 pinctrl-names = "default"; 270 282 pinctrl-0 = <&pinctrl_uart1>;

+2

arch/arm/boot/dts/imx6sll.dtsi

··· 568 568 regmap = <&snvs>; 569 569 offset = <0x38>; 570 570 mask = <0x61>; 571 + status = "disabled"; 571 572 }; 572 573 573 574 snvs_pwrkey: snvs-powerkey { ··· 577 576 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 578 577 linux,keycode = <KEY_POWER>; 579 578 wakeup-source; 579 + status = "disabled"; 580 580 }; 581 581 }; 582 582

+16

arch/arm/boot/dts/imx6sx-sdb-reva.dts

··· 154 154 enable-active-high; 155 155 vin-supply = <&reg_can_en>; 156 156 }; 157 + 158 + &reg_vdd1p1 { 159 + vin-supply = <&vgen6_reg>; 160 + }; 161 + 162 + &reg_vdd3p0 { 163 + vin-supply = <&sw2_reg>; 164 + }; 165 + 166 + &reg_vdd2p5 { 167 + vin-supply = <&vgen6_reg>; 168 + }; 169 + 170 + &snvs_pwrkey { 171 + status = "okay"; 172 + };

+16

arch/arm/boot/dts/imx6sx-sdb.dts

··· 137 137 vin-supply = <&sw1a_reg>; 138 138 }; 139 139 140 + &reg_vdd1p1 { 141 + vin-supply = <&vgen6_reg>; 142 + }; 143 + 144 + &reg_vdd3p0 { 145 + vin-supply = <&sw2_reg>; 146 + }; 147 + 148 + &reg_vdd2p5 { 149 + vin-supply = <&vgen6_reg>; 150 + }; 151 + 140 152 &reg_can_stby { 141 153 /* Transceiver EN/STBY is active low on RevB board */ 142 154 gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; 155 + }; 156 + 157 + &snvs_pwrkey { 158 + status = "okay"; 143 159 };

+1 -38

arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 2 /* 2 3 * Copyright (c) 2016 Andreas Färber 3 - * 4 - * This file is dual-licensed: you can use it either under the terms 5 - * of the GPL or the X11 license, at your option. Note that this dual 6 - * licensing only applies to this file, and not this project as a 7 - * whole. 8 - * 9 - * a) This library is free software; you can redistribute it and/or 10 - * modify it under the terms of the GNU General Public License as 11 - * published by the Free Software Foundation; either version 2 of the 12 - * License, or (at your option) any later version. 13 - * 14 - * This library is distributed in the hope that it will be useful, 15 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 - * GNU General Public License for more details. 18 - * 19 - * Or, alternatively, 20 - * 21 - * b) Permission is hereby granted, free of charge, to any person 22 - * obtaining a copy of this software and associated documentation 23 - * files (the "Software"), to deal in the Software without 24 - * restriction, including without limitation the rights to use, 25 - * copy, modify, merge, publish, distribute, sublicense, and/or 26 - * sell copies of the Software, and to permit persons to whom the 27 - * Software is furnished to do so, subject to the following 28 - * conditions: 29 - * 30 - * The above copyright notice and this permission notice shall be 31 - * included in all copies or substantial portions of the Software. 32 - * 33 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 - * OTHER DEALINGS IN THE SOFTWARE. 41 4 */ 42 5 43 6 /dts-v1/;

+9 -38

arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 2 /* 2 3 * Copyright (c) 2016 Andreas Färber 3 - * 4 - * This file is dual-licensed: you can use it either under the terms 5 - * of the GPL or the X11 license, at your option. Note that this dual 6 - * licensing only applies to this file, and not this project as a 7 - * whole. 8 - * 9 - * a) This library is free software; you can redistribute it and/or 10 - * modify it under the terms of the GNU General Public License as 11 - * published by the Free Software Foundation; either version 2 of the 12 - * License, or (at your option) any later version. 13 - * 14 - * This library is distributed in the hope that it will be useful, 15 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 - * GNU General Public License for more details. 18 - * 19 - * Or, alternatively, 20 - * 21 - * b) Permission is hereby granted, free of charge, to any person 22 - * obtaining a copy of this software and associated documentation 23 - * files (the "Software"), to deal in the Software without 24 - * restriction, including without limitation the rights to use, 25 - * copy, modify, merge, publish, distribute, sublicense, and/or 26 - * sell copies of the Software, and to permit persons to whom the 27 - * Software is furnished to do so, subject to the following 28 - * conditions: 29 - * 30 - * The above copyright notice and this permission notice shall be 31 - * included in all copies or substantial portions of the Software. 32 - * 33 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 - * OTHER DEALINGS IN THE SOFTWARE. 41 4 */ 42 5 43 6 /dts-v1/; ··· 15 52 device_type = "memory"; 16 53 reg = <0x80000000 0x40000000>; 17 54 }; 55 + }; 56 + 57 + &i2c4 { /* Onboard Motion sensors */ 58 + status = "okay"; 59 + }; 60 + 61 + &uart3 { /* Bluetooth */ 62 + status = "okay"; 18 63 };

+9 -38

arch/arm/boot/dts/imx6sx-udoo-neo-full.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 2 /* 2 3 * Copyright (c) 2016 Andreas Färber 3 - * 4 - * This file is dual-licensed: you can use it either under the terms 5 - * of the GPL or the X11 license, at your option. Note that this dual 6 - * licensing only applies to this file, and not this project as a 7 - * whole. 8 - * 9 - * a) This library is free software; you can redistribute it and/or 10 - * modify it under the terms of the GNU General Public License as 11 - * published by the Free Software Foundation; either version 2 of the 12 - * License, or (at your option) any later version. 13 - * 14 - * This library is distributed in the hope that it will be useful, 15 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 - * GNU General Public License for more details. 18 - * 19 - * Or, alternatively, 20 - * 21 - * b) Permission is hereby granted, free of charge, to any person 22 - * obtaining a copy of this software and associated documentation 23 - * files (the "Software"), to deal in the Software without 24 - * restriction, including without limitation the rights to use, 25 - * copy, modify, merge, publish, distribute, sublicense, and/or 26 - * sell copies of the Software, and to permit persons to whom the 27 - * Software is furnished to do so, subject to the following 28 - * conditions: 29 - * 30 - * The above copyright notice and this permission notice shall be 31 - * included in all copies or substantial portions of the Software. 32 - * 33 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 - * OTHER DEALINGS IN THE SOFTWARE. 41 4 */ 42 5 43 6 /dts-v1/; ··· 30 67 reg = <0>; 31 68 }; 32 69 }; 70 + }; 71 + 72 + &i2c4 { /* Onboard Motion sensors */ 73 + status = "okay"; 74 + }; 75 + 76 + &uart3 { /* Bluetooth */ 77 + status = "okay"; 33 78 };

+37 -52

arch/arm/boot/dts/imx6sx-udoo-neo.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 2 /* 2 3 * Copyright (c) 2016 Andreas Färber 3 - * 4 - * This file is dual-licensed: you can use it either under the terms 5 - * of the GPL or the X11 license, at your option. Note that this dual 6 - * licensing only applies to this file, and not this project as a 7 - * whole. 8 - * 9 - * a) This library is free software; you can redistribute it and/or 10 - * modify it under the terms of the GNU General Public License as 11 - * published by the Free Software Foundation; either version 2 of the 12 - * License, or (at your option) any later version. 13 - * 14 - * This library is distributed in the hope that it will be useful, 15 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 - * GNU General Public License for more details. 18 - * 19 - * Or, alternatively, 20 - * 21 - * b) Permission is hereby granted, free of charge, to any person 22 - * obtaining a copy of this software and associated documentation 23 - * files (the "Software"), to deal in the Software without 24 - * restriction, including without limitation the rights to use, 25 - * copy, modify, merge, publish, distribute, sublicense, and/or 26 - * sell copies of the Software, and to permit persons to whom the 27 - * Software is furnished to do so, subject to the following 28 - * conditions: 29 - * 30 - * The above copyright notice and this permission notice shall be 31 - * included in all copies or substantial portions of the Software. 32 - * 33 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 - * OTHER DEALINGS IN THE SOFTWARE. 41 4 */ 42 5 43 6 #include "imx6sx.dtsi" ··· 69 106 gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; 70 107 startup-delay-us = <70000>; 71 108 enable-active-high; 72 - }; 73 - 74 - reg_bt: regulator-bt { 75 - compatible = "regulator-fixed"; 76 - pinctrl-names = "default"; 77 - pinctrl-0 = <&pinctrl_bt_reg>; 78 - enable-active-high; 79 - gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>; 80 - regulator-name = "bt_reg"; 81 - regulator-min-microvolt = <1800000>; 82 - regulator-max-microvolt = <1800000>; 83 - regulator-always-on; 84 109 }; 85 110 }; 86 111 ··· 176 225 }; 177 226 }; 178 227 228 + &i2c2 { /* Brick snap in sensors connector */ 229 + pinctrl-names = "default"; 230 + pinctrl-0 = <&pinctrl_i2c2>; 231 + clock-frequency = <100000>; 232 + status = "okay"; 233 + }; 234 + 235 + &i2c4 { /* Onboard Motion sensors */ 236 + pinctrl-names = "default"; 237 + pinctrl-0 = <&pinctrl_i2c4>; 238 + clock-frequency = <100000>; 239 + status = "disabled"; 240 + }; 241 + 179 242 &iomuxc { 180 243 pinctrl_bt_reg: btreggrp { 181 244 fsl,pins = ··· 219 254 fsl,pins = 220 255 <MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1>, 221 256 <MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1>; 257 + }; 258 + 259 + pinctrl_i2c2: i2c2grp { 260 + fsl,pins = 261 + <MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1>, 262 + <MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1>; 263 + }; 264 + 265 + pinctrl_i2c4: i2c4grp { 266 + fsl,pins = 267 + <MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x4001b8b1>, 268 + <MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x4001b8b1>; 222 269 }; 223 270 224 271 pinctrl_uart1: uart1grp { ··· 331 354 status = "disabled"; 332 355 }; 333 356 334 - &uart3 { /* Bluetooth */ 357 + &uart3 { /* Bluetooth - only on Extended/Full versions */ 335 358 pinctrl-names = "default"; 336 359 pinctrl-0 = <&pinctrl_uart3>; 337 360 uart-has-rtscts; 338 - status = "okay"; 361 + status = "disabled"; 362 + 363 + bluetooth { 364 + compatible = "ti,wl1831-st"; 365 + enable-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; 366 + pinctrl-names = "default"; 367 + pinctrl-0 = <&pinctrl_bt_reg>; 368 + max-speed = <921600>; 369 + }; 339 370 }; 340 371 341 372 /* Arduino serial */

+4 -3

arch/arm/boot/dts/imx6sx.dtsi

··· 600 600 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 601 601 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 602 602 603 - regulator-1p1 { 603 + reg_vdd1p1: regulator-1p1 { 604 604 compatible = "fsl,anatop-regulator"; 605 605 regulator-name = "vdd1p1"; 606 606 regulator-min-microvolt = <1000000>; ··· 615 615 anatop-enable-bit = <0>; 616 616 }; 617 617 618 - regulator-3p0 { 618 + reg_vdd3p0: regulator-3p0 { 619 619 compatible = "fsl,anatop-regulator"; 620 620 regulator-name = "vdd3p0"; 621 621 regulator-min-microvolt = <2800000>; ··· 630 630 anatop-enable-bit = <0>; 631 631 }; 632 632 633 - regulator-2p5 { 633 + reg_vdd2p5: regulator-2p5 { 634 634 compatible = "fsl,anatop-regulator"; 635 635 regulator-name = "vdd2p5"; 636 636 regulator-min-microvolt = <2250000>; ··· 738 738 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 739 739 linux,keycode = <KEY_POWER>; 740 740 wakeup-source; 741 + status = "disabled"; 741 742 }; 742 743 }; 743 744

+4

arch/arm/boot/dts/imx6ul-14x14-evk.dtsi

··· 238 238 status = "okay"; 239 239 }; 240 240 241 + &snvs_pwrkey { 242 + status = "okay"; 243 + }; 244 + 241 245 &tsc { 242 246 pinctrl-names = "default"; 243 247 pinctrl-0 = <&pinctrl_tsc>;

+1 -1

arch/arm/boot/dts/imx6ul-geam.dts

··· 169 169 display = <&display0>; 170 170 status = "okay"; 171 171 172 - display0: display { 172 + display0: display0 { 173 173 bits-per-pixel = <16>; 174 174 bus-width = <18>; 175 175

+1 -1

arch/arm/boot/dts/imx6ul-isiot.dtsi

··· 161 161 display = <&display0>; 162 162 status = "okay"; 163 163 164 - display0: display { 164 + display0: display0 { 165 165 bits-per-pixel = <16>; 166 166 bus-width = <18>; 167 167

+14

arch/arm/boot/dts/imx6ul.dtsi

··· 59 59 compatible = "arm,cortex-a7"; 60 60 device_type = "cpu"; 61 61 reg = <0>; 62 + clock-frequency = <696000000>; 62 63 clock-latency = <61036>; /* two CLK32 periods */ 63 64 #cooling-cells = <2>; 64 65 operating-points = < ··· 650 649 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 651 650 linux,keycode = <KEY_POWER>; 652 651 wakeup-source; 652 + status = "disabled"; 653 653 }; 654 654 655 655 snvs_lpgpr: snvs-lpgpr { ··· 858 856 <&clks IMX6UL_CLK_USDHC1>, 859 857 <&clks IMX6UL_CLK_USDHC1>; 860 858 clock-names = "ipg", "ahb", "per"; 859 + fsl,tuning-step= <2>; 860 + fsl,tuning-start-tap = <20>; 861 861 bus-width = <4>; 862 862 status = "disabled"; 863 863 }; ··· 873 869 <&clks IMX6UL_CLK_USDHC2>; 874 870 clock-names = "ipg", "ahb", "per"; 875 871 bus-width = <4>; 872 + fsl,tuning-step= <2>; 873 + fsl,tuning-start-tap = <20>; 876 874 status = "disabled"; 877 875 }; 878 876 ··· 966 960 <&clks IMX6UL_CLK_DUMMY>; 967 961 clock-names = "pix", "axi", "disp_axi"; 968 962 status = "disabled"; 963 + }; 964 + 965 + pxp: pxp@21cc000 { 966 + compatible = "fsl,imx6ul-pxp"; 967 + reg = <0x021cc000 0x4000>; 968 + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 969 + clocks = <&clks IMX6UL_CLK_PXP>; 970 + clock-names = "axi"; 969 971 }; 970 972 971 973 qspi: spi@21e0000 {

+9 -2

arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi

··· 145 145 }; 146 146 147 147 &usdhc1 { 148 - pinctrl-names = "default"; 148 + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 149 149 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; 150 - no-1-8-v; 150 + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; 151 + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; 152 + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; 151 153 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 152 154 disable-wp; 153 155 wakeup-source; 154 156 keep-power-in-suspend; 155 157 vmmc-supply = <&reg_3v3>; 158 + vqmmc-supply = <&reg_sd1_vmmc>; 159 + sd-uhs-sdr12; 160 + sd-uhs-sdr25; 161 + sd-uhs-sdr50; 162 + sd-uhs-sdr104; 156 163 status = "okay"; 157 164 };

+6

arch/arm/boot/dts/imx6ull-colibri.dtsi

··· 545 545 >; 546 546 }; 547 547 548 + pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp { 549 + fsl,pins = < 550 + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 551 + >; 552 + }; 553 + 548 554 pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { 549 555 fsl,pins = < 550 556 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14

+7

arch/arm/boot/dts/imx6ull.dtsi

··· 12 12 /delete-node/ &crypto; 13 13 14 14 &cpu0 { 15 + clock-frequency = <900000000>; 15 16 operating-points = < 16 17 /* kHz uV */ 17 18 900000 1275000 ··· 33 32 34 33 &ocotp { 35 34 compatible = "fsl,imx6ull-ocotp", "syscon"; 35 + }; 36 + 37 + &pxp { 38 + compatible = "fsl,imx6ull-pxp"; 39 + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 40 + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 36 41 }; 37 42 38 43 &usdhc1 {

+375

arch/arm/boot/dts/imx7d-meerkat96.dts

··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + /* 3 + * Copyright (C) 2019 Linaro Ltd. 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "imx7d.dtsi" 9 + 10 + / { 11 + model = "96Boards Meerkat96 Board"; 12 + compatible = "novtech,imx7d-meerkat96", "fsl,imx7d"; 13 + 14 + chosen { 15 + stdout-path = &uart6; 16 + }; 17 + 18 + memory@80000000 { 19 + device_type = "memory"; 20 + reg = <0x80000000 0x20000000>; /* 512MB */ 21 + }; 22 + 23 + reg_wlreg_on: regulator-wlreg-on { 24 + compatible = "regulator-fixed"; 25 + pinctrl-names = "default"; 26 + pinctrl-0 = <&pinctrl_wlreg_on>; 27 + regulator-name = "wlreg_on"; 28 + regulator-min-microvolt = <3300000>; 29 + regulator-max-microvolt = <3300000>; 30 + startup-delay-us = <100>; 31 + gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; 32 + enable-active-high; 33 + regulator-always-on; 34 + }; 35 + 36 + reg_3p3v: regulator-3p3v { 37 + compatible = "regulator-fixed"; 38 + regulator-name = "3P3V"; 39 + regulator-min-microvolt = <3300000>; 40 + regulator-max-microvolt = <3300000>; 41 + regulator-always-on; 42 + }; 43 + 44 + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 45 + compatible = "regulator-fixed"; 46 + regulator-name = "usb_otg1_vbus"; 47 + regulator-min-microvolt = <5000000>; 48 + regulator-max-microvolt = <5000000>; 49 + }; 50 + 51 + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 52 + compatible = "regulator-fixed"; 53 + regulator-name = "usb_otg2_vbus"; 54 + regulator-min-microvolt = <5000000>; 55 + regulator-max-microvolt = <5000000>; 56 + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; 57 + enable-active-high; 58 + }; 59 + 60 + leds { 61 + compatible = "gpio-leds"; 62 + pinctrl-names = "default"; 63 + pinctrl-0 = <&pinctrl_gpio_leds>; 64 + 65 + led1 { 66 + label = "green:user1"; 67 + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 68 + linux,default-trigger = "heartbeat"; 69 + default-state = "off"; 70 + }; 71 + 72 + led2 { 73 + label = "green:user2"; 74 + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; 75 + linux,default-trigger = "mmc0"; 76 + default-state = "off"; 77 + }; 78 + 79 + led3 { 80 + label = "green:user3"; 81 + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 82 + linux,default-trigger = "mmc1"; 83 + default-state = "off"; 84 + }; 85 + 86 + led4 { 87 + label = "green:user4"; 88 + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; 89 + linux,default-trigger = "none"; 90 + default-state = "off"; 91 + panic-indicator; 92 + }; 93 + 94 + led5 { 95 + label = "yellow:wlan"; 96 + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; 97 + linux,default-trigger = "phy0tx"; 98 + default-state = "off"; 99 + }; 100 + 101 + led6 { 102 + label = "blue:bt"; 103 + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; 104 + linux,default-trigger = "bluetooth-power"; 105 + default-state = "off"; 106 + }; 107 + }; 108 + }; 109 + 110 + &i2c1 { 111 + pinctrl-names = "default"; 112 + pinctrl-0 = <&pinctrl_i2c1>; 113 + status = "okay"; 114 + }; 115 + 116 + &i2c2 { 117 + pinctrl-names = "default"; 118 + pinctrl-0 = <&pinctrl_i2c2>; 119 + status = "okay"; 120 + }; 121 + 122 + &i2c3 { 123 + pinctrl-names = "default"; 124 + pinctrl-0 = <&pinctrl_i2c3>; 125 + status = "okay"; 126 + }; 127 + 128 + &i2c4 { 129 + pinctrl-names = "default"; 130 + pinctrl-0 = <&pinctrl_i2c4>; 131 + status = "okay"; 132 + }; 133 + 134 + &lcdif { 135 + pinctrl-names = "default"; 136 + pinctrl-0 = <&pinctrl_lcdif>; 137 + status = "okay"; 138 + }; 139 + 140 + &uart1 { 141 + pinctrl-names = "default"; 142 + pinctrl-0 = <&pinctrl_uart1>; 143 + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; 144 + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 145 + status = "okay"; 146 + }; 147 + 148 + &uart3 { 149 + pinctrl-names = "default"; 150 + pinctrl-0 = <&pinctrl_uart3>; 151 + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; 152 + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 153 + uart-has-rtscts; 154 + status = "okay"; 155 + }; 156 + 157 + &uart6 { 158 + pinctrl-names = "default"; 159 + pinctrl-0 = <&pinctrl_uart6>; 160 + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 161 + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 162 + status = "okay"; 163 + }; 164 + 165 + &uart7 { 166 + pinctrl-names = "default"; 167 + pinctrl-0 = <&pinctrl_uart7 &pinctrl_bt_gpios>; 168 + assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; 169 + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 170 + uart-has-rtscts; 171 + fsl,dte-mode; 172 + status = "okay"; 173 + 174 + bluetooth { 175 + compatible = "brcm,bcm43438-bt"; 176 + device-wakeup-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; 177 + host-wakeup-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; 178 + }; 179 + }; 180 + 181 + &usbotg1 { 182 + vbus-supply = <&reg_usb_otg1_vbus>; 183 + status = "okay"; 184 + }; 185 + 186 + &usbotg2 { 187 + vbus-supply = <&reg_usb_otg2_vbus>; 188 + dr_mode = "host"; 189 + status = "okay"; 190 + }; 191 + 192 + &usdhc1 { 193 + pinctrl-names = "default"; 194 + pinctrl-0 = <&pinctrl_usdhc1>; 195 + keep-power-in-suspend; 196 + tuning-step = <2>; 197 + vmmc-supply = <&reg_3p3v>; 198 + no-1-8-v; 199 + broken-cd; 200 + status = "okay"; 201 + }; 202 + 203 + &usdhc3 { 204 + #address-cells = <1>; 205 + #size-cells = <0>; 206 + pinctrl-names = "default"; 207 + pinctrl-0 = <&pinctrl_usdhc3>; 208 + bus-width = <4>; 209 + no-1-8-v; 210 + no-mmc; 211 + non-removable; 212 + keep-power-in-suspend; 213 + wakeup-source; 214 + vmmc-supply = <&reg_wlreg_on>; 215 + vqmmc-supply =<&reg_3p3v>; 216 + status = "okay"; 217 + 218 + brcmf: wifi@1 { 219 + reg = <1>; 220 + compatible = "brcm,bcm4329-fmac"; 221 + pinctrl-names = "default"; 222 + pinctrl-0 = <&pinctrl_wlan_irq>; 223 + interrupt-parent = <&gpio6>; 224 + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 225 + interrupt-names = "host-wake"; 226 + }; 227 + }; 228 + 229 + &iomuxc { 230 + pinctrl_bt_gpios: btgpiosgrp { 231 + fsl,pins = < 232 + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x59 233 + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x1f 234 + >; 235 + }; 236 + 237 + pinctrl_gpio_leds: gpioledsgrp { 238 + fsl,pins = < 239 + MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 240 + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x59 241 + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 242 + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59 243 + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 244 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 245 + >; 246 + }; 247 + 248 + pinctrl_i2c1: i2c1grp { 249 + fsl,pins = < 250 + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 251 + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 252 + >; 253 + }; 254 + 255 + pinctrl_i2c2: i2c2grp { 256 + fsl,pins = < 257 + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 258 + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 259 + >; 260 + }; 261 + 262 + pinctrl_i2c3: i2c3grp { 263 + fsl,pins = < 264 + MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f 265 + MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f 266 + >; 267 + }; 268 + 269 + pinctrl_i2c4: i2c4grp { 270 + fsl,pins = < 271 + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f 272 + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f 273 + >; 274 + }; 275 + 276 + pinctrl_lcdif: lcdifgrp { 277 + fsl,pins = < 278 + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 279 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 280 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 281 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 282 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 283 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 284 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 285 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 286 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 287 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 288 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 289 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 290 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 291 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 292 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 293 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 294 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 295 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 296 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 297 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 298 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 299 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 300 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 301 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 302 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 303 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 304 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 305 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 306 + MX7D_PAD_LCD_RESET__LCD_RESET 0x79 307 + >; 308 + }; 309 + 310 + pinctrl_uart1: uart1grp { 311 + fsl,pins = < 312 + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 313 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 314 + >; 315 + }; 316 + 317 + pinctrl_uart3: uart3grp { 318 + fsl,pins = < 319 + MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x79 320 + MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x79 321 + MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x79 322 + MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x79 323 + >; 324 + }; 325 + 326 + pinctrl_uart6: uart6grp { 327 + fsl,pins = < 328 + MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x79 329 + MX7D_PAD_SD1_WP__UART6_DCE_TX 0x79 330 + >; 331 + }; 332 + 333 + pinctrl_uart7: uart7grp { 334 + fsl,pins = < 335 + MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x79 336 + MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x79 337 + MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x79 338 + MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x79 339 + >; 340 + }; 341 + 342 + pinctrl_usdhc1: usdhc1grp { 343 + fsl,pins = < 344 + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 345 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 346 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 347 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 348 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 349 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 350 + >; 351 + }; 352 + 353 + pinctrl_usdhc3: usdhc3grp { 354 + fsl,pins = < 355 + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 356 + MX7D_PAD_SD3_CLK__SD3_CLK 0x0D 357 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 358 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 359 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 360 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 361 + >; 362 + }; 363 + 364 + pinctrl_wlan_irq: wlanirqgrp { 365 + fsl,pins = < 366 + MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x19 367 + >; 368 + }; 369 + 370 + pinctrl_wlreg_on: wlregongrp { 371 + fsl,pins = < 372 + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x19 373 + >; 374 + }; 375 + };

+14 -2

arch/arm/boot/dts/imx7d-sdb.dts

··· 263 263 }; 264 264 265 265 sw2_reg: sw2 { 266 - regulator-min-microvolt = <1500000>; 267 - regulator-max-microvolt = <1850000>; 266 + regulator-min-microvolt = <1800000>; 267 + regulator-max-microvolt = <1800000>; 268 268 regulator-boot-on; 269 269 regulator-always-on; 270 270 }; ··· 376 376 377 377 &pcie { 378 378 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; 379 + status = "okay"; 380 + }; 381 + 382 + &reg_1p0d { 383 + vin-supply = <&sw2_reg>; 384 + }; 385 + 386 + &reg_1p2 { 387 + vin-supply = <&sw2_reg>; 388 + }; 389 + 390 + &snvs_pwrkey { 379 391 status = "okay"; 380 392 }; 381 393

+1 -15

arch/arm/boot/dts/imx7d-zii-rpu2.dts

··· 16 16 compatible = "zii,imx7d-rpu2", "fsl,imx7d"; 17 17 18 18 chosen { 19 - stdout-path = &uart1; 19 + stdout-path = &uart2; 20 20 }; 21 21 22 22 cs2000_ref: oscillator { ··· 775 775 >; 776 776 }; 777 777 778 - pinctrl_i2c1_gpio: i2c1gpiogrp { 779 - fsl,pins = < 780 - MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x4000007f 781 - MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x4000007f 782 - >; 783 - }; 784 - 785 778 pinctrl_i2c2: i2c2grp { 786 779 fsl,pins = < 787 780 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 788 781 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 789 - >; 790 - }; 791 - 792 - pinctrl_i2c2_gpio: i2c2gpiogrp { 793 - fsl,pins = < 794 - MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x4000007f 795 - MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x4000007f 796 782 >; 797 783 }; 798 784

+13 -3

arch/arm/boot/dts/imx7d.dtsi

··· 12 12 clock-frequency = <996000000>; 13 13 operating-points-v2 = <&cpu0_opp_table>; 14 14 #cooling-cells = <2>; 15 + nvmem-cells = <&cpu_speed_grade>; 16 + nvmem-cell-names = "speed_grade"; 15 17 }; 16 18 17 19 cpu1: cpu@1 { ··· 41 39 42 40 opp-792000000 { 43 41 opp-hz = /bits/ 64 <792000000>; 44 - opp-microvolt = <975000>; 42 + opp-microvolt = <1000000>; 45 43 clock-latency-ns = <150000>; 44 + opp-supported-hw = <0xf>, <0xf>; 46 45 }; 47 46 48 47 opp-996000000 { 49 48 opp-hz = /bits/ 64 <996000000>; 50 - opp-microvolt = <1075000>; 49 + opp-microvolt = <1100000>; 51 50 clock-latency-ns = <150000>; 52 - opp-suspend; 51 + opp-supported-hw = <0xc>, <0xf>; 52 + }; 53 + 54 + opp-1200000000 { 55 + opp-hz = /bits/ 64 <1200000000>; 56 + opp-microvolt = <1225000>; 57 + clock-latency-ns = <150000>; 58 + opp-supported-hw = <0x8>, <0xf>; 53 59 }; 54 60 }; 55 61

+8 -3

arch/arm/boot/dts/imx7s.dtsi

··· 117 117 * non-configurable replicators don't show up on the 118 118 * AMBA bus. As such no need to add "arm,primecell" 119 119 */ 120 - compatible = "arm,coresight-replicator"; 120 + compatible = "arm,coresight-static-replicator"; 121 121 122 122 out-ports { 123 123 #address-cells = <1>; ··· 175 175 ranges; 176 176 177 177 funnel@30041000 { 178 - compatible = "arm,coresight-funnel", "arm,primecell"; 178 + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 179 179 reg = <0x30041000 0x1000>; 180 180 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 181 181 clock-names = "apb_pclk"; ··· 217 217 }; 218 218 219 219 funnel@30083000 { 220 - compatible = "arm,coresight-funnel", "arm,primecell"; 220 + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 221 221 reg = <0x30083000 0x1000>; 222 222 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 223 223 clock-names = "apb_pclk"; ··· 551 551 tempmon_temp_grade: temp-grade@10 { 552 552 reg = <0x10 0x4>; 553 553 }; 554 + 555 + cpu_speed_grade: speed-grade@10 { 556 + reg = <0x10 0x4>; 557 + }; 554 558 }; 555 559 556 560 anatop: anatop@30360000 { ··· 613 609 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 614 610 linux,keycode = <KEY_POWER>; 615 611 wakeup-source; 612 + status = "disabled"; 616 613 }; 617 614 }; 618 615

+55

arch/arm/boot/dts/imx7ulp-evk.dts

··· 22 22 reg = <0x60000000 0x40000000>; 23 23 }; 24 24 25 + backlight { 26 + compatible = "pwm-backlight"; 27 + pwms = <&tpm4 1 50000 0>; 28 + brightness-levels = <0 20 25 30 35 40 100>; 29 + default-brightness-level = <6>; 30 + status = "okay"; 31 + }; 32 + 33 + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 34 + compatible = "regulator-fixed"; 35 + pinctrl-names = "default"; 36 + pinctrl-0 = <&pinctrl_usbotg1_vbus>; 37 + regulator-name = "usb_otg1_vbus"; 38 + regulator-min-microvolt = <5000000>; 39 + regulator-max-microvolt = <5000000>; 40 + gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>; 41 + enable-active-high; 42 + }; 43 + 25 44 reg_vsd_3v3: regulator-vsd-3v3 { 26 45 compatible = "regulator-fixed"; 27 46 regulator-name = "VSD_3V3"; ··· 59 40 status = "okay"; 60 41 }; 61 42 43 + &tpm4 { 44 + pinctrl-names = "default"; 45 + pinctrl-0 = <&pinctrl_pwm0>; 46 + status = "okay"; 47 + }; 48 + 49 + &usbotg1 { 50 + vbus-supply = <&reg_usb_otg1_vbus>; 51 + pinctrl-names = "default"; 52 + pinctrl-0 = <&pinctrl_usbotg1_id>; 53 + srp-disable; 54 + hnp-disable; 55 + adp-disable; 56 + over-current-active-low; 57 + status = "okay"; 58 + }; 59 + 62 60 &usdhc0 { 63 61 pinctrl-names = "default"; 64 62 pinctrl-0 = <&pinctrl_usdhc0>; ··· 91 55 IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 92 56 >; 93 57 bias-pull-up; 58 + }; 59 + 60 + pinctrl_pwm0: pwm0grp { 61 + fsl,pins = < 62 + IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 63 + >; 64 + }; 65 + 66 + pinctrl_usbotg1_vbus: otg1vbusgrp { 67 + fsl,pins = < 68 + IMX7ULP_PAD_PTC0__PTC0 0x20000 69 + >; 70 + }; 71 + 72 + pinctrl_usbotg1_id: otg1idgrp { 73 + fsl,pins = < 74 + IMX7ULP_PAD_PTC13__USB0_ID 0x10003 75 + IMX7ULP_PAD_PTC16__USB1_OC2 0x10003 76 + >; 94 77 }; 95 78 96 79 pinctrl_usdhc0: usdhc0grp {

+38

arch/arm/boot/dts/imx7ulp.dtsi

··· 30 30 serial1 = &lpuart5; 31 31 serial2 = &lpuart6; 32 32 serial3 = &lpuart7; 33 + usbphy0 = &usbphy1; 33 34 }; 34 35 35 36 cpus { ··· 125 124 status = "disabled"; 126 125 }; 127 126 127 + tpm4: pwm@40250000 { 128 + compatible = "fsl,imx7ulp-pwm"; 129 + reg = <0x40250000 0x1000>; 130 + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; 131 + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; 132 + clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; 133 + #pwm-cells = <3>; 134 + status = "disabled"; 135 + }; 136 + 128 137 tpm5: tpm@40260000 { 129 138 compatible = "fsl,imx7ulp-tpm"; 130 139 reg = <0x40260000 0x1000>; ··· 142 131 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 143 132 <&pcc2 IMX7ULP_CLK_LPTPM5>; 144 133 clock-names = "ipg", "per"; 134 + }; 135 + 136 + usbotg1: usb@40330000 { 137 + compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; 138 + reg = <0x40330000 0x200>; 139 + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 140 + clocks = <&pcc2 IMX7ULP_CLK_USB0>; 141 + phys = <&usbphy1>; 142 + fsl,usbmisc = <&usbmisc1 0>; 143 + ahb-burst-config = <0x0>; 144 + tx-burst-size-dword = <0x8>; 145 + rx-burst-size-dword = <0x8>; 146 + status = "disabled"; 147 + }; 148 + 149 + usbmisc1: usbmisc@40330200 { 150 + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc"; 151 + #index-cells = <1>; 152 + reg = <0x40330200 0x200>; 153 + }; 154 + 155 + usbphy1: usb-phy@0x40350000 { 156 + compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy"; 157 + reg = <0x40350000 0x1000>; 158 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 159 + clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>; 160 + #phy-cells = <0>; 145 161 }; 146 162 147 163 usdhc0: mmc@40370000 {

+289

arch/arm/boot/dts/ls1021a-tsn.dts

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* Copyright 2016-2018 NXP Semiconductors 3 + * Copyright 2019 Vladimir Oltean <olteanv@gmail.com> 4 + */ 5 + 6 + /dts-v1/; 7 + #include "ls1021a.dtsi" 8 + 9 + / { 10 + model = "NXP LS1021A-TSN Board"; 11 + 12 + sys_mclk: clock-mclk { 13 + compatible = "fixed-clock"; 14 + #clock-cells = <0>; 15 + clock-frequency = <24576000>; 16 + }; 17 + 18 + reg_vdda_codec: regulator-3V3 { 19 + compatible = "regulator-fixed"; 20 + regulator-name = "3P3V"; 21 + regulator-min-microvolt = <3300000>; 22 + regulator-max-microvolt = <3300000>; 23 + regulator-always-on; 24 + }; 25 + 26 + reg_vddio_codec: regulator-2V5 { 27 + compatible = "regulator-fixed"; 28 + regulator-name = "2P5V"; 29 + regulator-min-microvolt = <2500000>; 30 + regulator-max-microvolt = <2500000>; 31 + regulator-always-on; 32 + }; 33 + }; 34 + 35 + &dspi0 { 36 + bus-num = <0>; 37 + status = "okay"; 38 + 39 + /* ADG704BRMZ 1:4 SPI mux/demux */ 40 + sja1105: ethernet-switch@1 { 41 + reg = <0x1>; 42 + #address-cells = <1>; 43 + #size-cells = <0>; 44 + compatible = "nxp,sja1105t"; 45 + /* 12 MHz */ 46 + spi-max-frequency = <12000000>; 47 + /* Sample data on trailing clock edge */ 48 + spi-cpha; 49 + /* SPI controller settings for SJA1105 timing requirements */ 50 + fsl,spi-cs-sck-delay = <1000>; 51 + fsl,spi-sck-cs-delay = <1000>; 52 + 53 + ports { 54 + #address-cells = <1>; 55 + #size-cells = <0>; 56 + 57 + port@0 { 58 + /* ETH5 written on chassis */ 59 + label = "swp5"; 60 + phy-handle = <&rgmii_phy6>; 61 + phy-mode = "rgmii-id"; 62 + reg = <0>; 63 + }; 64 + 65 + port@1 { 66 + /* ETH2 written on chassis */ 67 + label = "swp2"; 68 + phy-handle = <&rgmii_phy3>; 69 + phy-mode = "rgmii-id"; 70 + reg = <1>; 71 + }; 72 + 73 + port@2 { 74 + /* ETH3 written on chassis */ 75 + label = "swp3"; 76 + phy-handle = <&rgmii_phy4>; 77 + phy-mode = "rgmii-id"; 78 + reg = <2>; 79 + }; 80 + 81 + port@3 { 82 + /* ETH4 written on chassis */ 83 + label = "swp4"; 84 + phy-handle = <&rgmii_phy5>; 85 + phy-mode = "rgmii-id"; 86 + reg = <3>; 87 + }; 88 + 89 + port@4 { 90 + /* Internal port connected to eth2 */ 91 + ethernet = <&enet2>; 92 + phy-mode = "rgmii"; 93 + reg = <4>; 94 + 95 + fixed-link { 96 + speed = <1000>; 97 + full-duplex; 98 + }; 99 + }; 100 + }; 101 + }; 102 + }; 103 + 104 + &enet0 { 105 + tbi-handle = <&tbi0>; 106 + phy-handle = <&sgmii_phy2>; 107 + phy-mode = "sgmii"; 108 + status = "okay"; 109 + }; 110 + 111 + &enet1 { 112 + tbi-handle = <&tbi1>; 113 + phy-handle = <&sgmii_phy1>; 114 + phy-mode = "sgmii"; 115 + status = "okay"; 116 + }; 117 + 118 + /* RGMII delays added via PCB traces */ 119 + &enet2 { 120 + phy-mode = "rgmii"; 121 + status = "okay"; 122 + 123 + fixed-link { 124 + speed = <1000>; 125 + full-duplex; 126 + }; 127 + }; 128 + 129 + &esdhc { 130 + status = "okay"; 131 + }; 132 + 133 + &i2c0 { 134 + status = "okay"; 135 + 136 + /* 3 axis accelerometer */ 137 + accelerometer@1e { 138 + compatible = "fsl,fxls8471"; 139 + position = <0>; 140 + reg = <0x1e>; 141 + }; 142 + 143 + /* Audio codec (SAI2) */ 144 + audio-codec@2a { 145 + compatible = "fsl,sgtl5000"; 146 + VDDIO-supply = <&reg_vddio_codec>; 147 + VDDA-supply = <&reg_vdda_codec>; 148 + #sound-dai-cells = <0>; 149 + clocks = <&sys_mclk>; 150 + reg = <0x2a>; 151 + }; 152 + 153 + /* Current sensing circuit for 1V VDDCORE PMIC rail */ 154 + current-sensor@44 { 155 + compatible = "ti,ina220"; 156 + shunt-resistor = <1000>; 157 + reg = <0x44>; 158 + }; 159 + 160 + /* Current sensing circuit for 12V VCC rail */ 161 + current-sensor@45 { 162 + compatible = "ti,ina220"; 163 + shunt-resistor = <1000>; 164 + reg = <0x45>; 165 + }; 166 + 167 + /* Thermal monitor - case */ 168 + temperature-sensor@48 { 169 + compatible = "national,lm75"; 170 + reg = <0x48>; 171 + }; 172 + 173 + /* Thermal monitor - chip */ 174 + temperature-sensor@4c { 175 + compatible = "ti,tmp451"; 176 + reg = <0x4c>; 177 + }; 178 + 179 + eeprom@51 { 180 + compatible = "atmel,24c32"; 181 + reg = <0x51>; 182 + }; 183 + 184 + /* Unsupported devices: 185 + * - FXAS21002C Gyroscope at 0x20 186 + * - TI ADS7924 4-channel ADC at 0x49 187 + */ 188 + }; 189 + 190 + &ifc { 191 + status = "disabled"; 192 + }; 193 + 194 + &lpuart0 { 195 + status = "okay"; 196 + }; 197 + 198 + &lpuart3 { 199 + status = "okay"; 200 + }; 201 + 202 + &mdio0 { 203 + /* AR8031 */ 204 + sgmii_phy1: ethernet-phy@1 { 205 + reg = <0x1>; 206 + }; 207 + 208 + /* AR8031 */ 209 + sgmii_phy2: ethernet-phy@2 { 210 + reg = <0x2>; 211 + }; 212 + 213 + /* BCM5464 quad PHY */ 214 + rgmii_phy3: ethernet-phy@3 { 215 + reg = <0x3>; 216 + }; 217 + 218 + rgmii_phy4: ethernet-phy@4 { 219 + reg = <0x4>; 220 + }; 221 + 222 + rgmii_phy5: ethernet-phy@5 { 223 + reg = <0x5>; 224 + }; 225 + 226 + rgmii_phy6: ethernet-phy@6 { 227 + reg = <0x6>; 228 + }; 229 + 230 + /* SGMII PCS for enet0 */ 231 + tbi0: tbi-phy@1f { 232 + reg = <0x1f>; 233 + device_type = "tbi-phy"; 234 + }; 235 + }; 236 + 237 + &mdio1 { 238 + /* SGMII PCS for enet1 */ 239 + tbi1: tbi-phy@1f { 240 + reg = <0x1f>; 241 + device_type = "tbi-phy"; 242 + }; 243 + }; 244 + 245 + &qspi { 246 + status = "okay"; 247 + 248 + flash@0 { 249 + /* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */ 250 + compatible = "jedec,spi-nor", "s25fl256s1", "s25fl512s"; 251 + spi-max-frequency = <20000000>; 252 + #address-cells = <1>; 253 + #size-cells = <1>; 254 + reg = <0>; 255 + 256 + partitions { 257 + compatible = "fixed-partitions"; 258 + #address-cells = <1>; 259 + #size-cells = <1>; 260 + 261 + partition@0 { 262 + label = "RCW"; 263 + reg = <0x0 0x40000>; 264 + }; 265 + 266 + partition@40000 { 267 + label = "U-Boot"; 268 + reg = <0x40000 0x300000>; 269 + }; 270 + 271 + partition@340000 { 272 + label = "U-Boot Env"; 273 + reg = <0x340000 0x100000>; 274 + }; 275 + }; 276 + }; 277 + }; 278 + 279 + &sai2 { 280 + status = "okay"; 281 + }; 282 + 283 + &sata { 284 + status = "okay"; 285 + }; 286 + 287 + &uart0 { 288 + status = "okay"; 289 + };

+44 -8

arch/arm/boot/dts/vf610-zii-dev.dtsi

··· 177 177 status = "okay"; 178 178 }; 179 179 180 + &qspi0 { 181 + pinctrl-names = "default"; 182 + pinctrl-0 = <&pinctrl_qspi0>; 183 + status = "okay"; 184 + 185 + /* 186 + * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR 187 + * modes, so, spi-max-frequency is limited to 90MHz 188 + */ 189 + flash@0 { 190 + compatible = "jedec,spi-nor"; 191 + #address-cells = <1>; 192 + #size-cells = <1>; 193 + spi-max-frequency = <90000000>; 194 + spi-rx-bus-width = <4>; 195 + reg = <0>; 196 + m25p,fast-read; 197 + }; 198 + 199 + flash@2 { 200 + compatible = "jedec,spi-nor"; 201 + #address-cells = <1>; 202 + #size-cells = <1>; 203 + spi-max-frequency = <90000000>; 204 + spi-rx-bus-width = <4>; 205 + reg = <2>; 206 + m25p,fast-read; 207 + }; 208 + }; 209 + 180 210 &uart0 { 181 211 pinctrl-names = "default"; 182 212 pinctrl-0 = <&pinctrl_uart0>; ··· 390 360 391 361 pinctrl_qspi0: qspi0grp { 392 362 fsl,pins = < 393 - VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 394 - VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff 395 - VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 396 - VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 397 - VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 398 - VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 363 + VF610_PAD_PTD0__QSPI0_A_QSCK 0x38c2 364 + VF610_PAD_PTD1__QSPI0_A_CS0 0x38c2 365 + VF610_PAD_PTD2__QSPI0_A_DATA3 0x38c3 366 + VF610_PAD_PTD3__QSPI0_A_DATA2 0x38c3 367 + VF610_PAD_PTD4__QSPI0_A_DATA1 0x38c3 368 + VF610_PAD_PTD5__QSPI0_A_DATA0 0x38c3 369 + VF610_PAD_PTD7__QSPI0_B_QSCK 0x38c2 370 + VF610_PAD_PTD8__QSPI0_B_CS0 0x38c2 371 + VF610_PAD_PTD9__QSPI0_B_DATA3 0x38c3 372 + VF610_PAD_PTD10__QSPI0_B_DATA2 0x38c3 373 + VF610_PAD_PTD11__QSPI0_B_DATA1 0x38c3 374 + VF610_PAD_PTD12__QSPI0_B_DATA0 0x38c3 399 375 >; 400 376 }; 401 377 ··· 421 385 422 386 pinctrl_uart2: uart2grp { 423 387 fsl,pins = < 424 - VF610_PAD_PTD0__UART2_TX 0x21a2 425 - VF610_PAD_PTD1__UART2_RX 0x21a1 388 + VF610_PAD_PTD23__UART2_TX 0x21a2 389 + VF610_PAD_PTD22__UART2_RX 0x21a1 426 390 >; 427 391 }; 428 392