tjh.dev / kernel
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[PATCH] sh: Move TRA/EXPEVT/INTEVT definitions for reuse

Currently entry.S is home to these definitions, so we move them somewhere more
sensible. IPR IRQ handling depends on being to read from INTEVT.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

authored by

Paul Mundt and committed by
Linus Torvalds 091904ae 134ed142

+19 -17
+1 -17
arch/sh/kernel/entry.S
··· 16 16 #include <linux/config.h> 17 17 #include <asm/asm-offsets.h> 18 18 #include <asm/thread_info.h> 19 + #include <asm/cpu/mmu_context.h> 19 20 #include <asm/unistd.h> 20 21 21 22 #if !defined(CONFIG_NFSD) && !defined(CONFIG_NFSD_MODULE) ··· 75 74 76 75 ENOSYS = 38 77 76 EINVAL = 22 78 - 79 - #if defined(CONFIG_CPU_SH3) 80 - TRA = 0xffffffd0 81 - EXPEVT = 0xffffffd4 82 - #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 83 - defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 84 - INTEVT = 0xa4000000 ! INTEVTE2(0xa4000000) 85 - #else 86 - INTEVT = 0xffffffd8 87 - #endif 88 - MMU_TEA = 0xfffffffc ! TLB Exception Address Register 89 - #elif defined(CONFIG_CPU_SH4) 90 - TRA = 0xff000020 91 - EXPEVT = 0xff000024 92 - INTEVT = 0xff000028 93 - MMU_TEA = 0xff00000c ! TLB Exception Address Register 94 - #endif 95 77 96 78 #if defined(CONFIG_KGDB_NMI) 97 79 NMI_VEC = 0x1c0 ! Must catch early for debounce
+10
include/asm-sh/cpu-sh3/mmu_context.h
··· 24 24 #define MMU_NTLB_WAYS 4 25 25 #define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */ 26 26 27 + #define TRA 0xffffffd0 28 + #define EXPEVT 0xffffffd4 29 + 30 + #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 31 + defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 32 + #define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ 33 + #else 34 + #define INTEVT 0xffffffd8 35 + #endif 36 + 27 37 #endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */ 28 38
+8
include/asm-sh/cpu-sh4/mmu_context.h
··· 23 23 #define MMU_PAGE_ASSOC_BIT 0x80 24 24 25 25 #define MMU_NTLB_ENTRIES 64 /* for 7750 */ 26 + #ifdef CONFIG_SH_STORE_QUEUES 27 + #define MMU_CONTROL_INIT 0x05 /* SQMD=0, SV=0, TI=1, AT=1 */ 28 + #else 26 29 #define MMU_CONTROL_INIT 0x205 /* SQMD=1, SV=0, TI=1, AT=1 */ 30 + #endif 27 31 28 32 #define MMU_ITLB_DATA_ARRAY 0xF3000000 29 33 #define MMU_UTLB_DATA_ARRAY 0xF7000000 ··· 38 34 #define MMU_ITLB_ENTRIES 4 39 35 #define MMU_I_ENTRY_SHIFT 8 40 36 #define MMU_ITLB_VALID 0x100 37 + 38 + #define TRA 0xff000020 39 + #define EXPEVT 0xff000024 40 + #define INTEVT 0xff000028 41 41 42 42 #endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */ 43 43