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ARM: dts: sun8i: a23/a33: Change pinctrl nodes to avoid warning

All our pinctrl nodes were using a node name convention with a unit-address
to differentiate the different muxing options. However, since those nodes
didn't have a reg property, they were generating warnings in DTC.

In order to accomodate for this, convert the old nodes to the syntax we've
been using for the new SoCs, including removing the letter suffix of the
node labels to the bank of those pins to make things more readable.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Maxime Ripard 090e563c 4ead0ad7

+50 -41
+13 -13
arch/arm/boot/dts/sun8i-a23-a33.dtsi
··· 298 298 #interrupt-cells = <3>; 299 299 #gpio-cells = <3>; 300 300 301 - i2c0_pins_a: i2c0@0 { 301 + i2c0_pins: i2c0-pins { 302 302 pins = "PH2", "PH3"; 303 303 function = "i2c0"; 304 304 }; 305 305 306 - i2c1_pins_a: i2c1@0 { 306 + i2c1_pins: i2c1-pins { 307 307 pins = "PH4", "PH5"; 308 308 function = "i2c1"; 309 309 }; 310 310 311 - i2c2_pins_a: i2c2@0 { 311 + i2c2_pins: i2c2-pins { 312 312 pins = "PE12", "PE13"; 313 313 function = "i2c2"; 314 314 }; 315 315 316 - lcd_rgb666_pins: lcd-rgb666@0 { 316 + lcd_rgb666_pins: lcd-rgb666-pins { 317 317 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 318 318 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", 319 319 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", ··· 321 321 function = "lcd0"; 322 322 }; 323 323 324 - mmc0_pins_a: mmc0@0 { 324 + mmc0_pins: mmc0-pins { 325 325 pins = "PF0", "PF1", "PF2", 326 326 "PF3", "PF4", "PF5"; 327 327 function = "mmc0"; ··· 329 329 bias-pull-up; 330 330 }; 331 331 332 - mmc1_pins_a: mmc1@0 { 332 + mmc1_pg_pins: mmc1-pg-pins { 333 333 pins = "PG0", "PG1", "PG2", 334 334 "PG3", "PG4", "PG5"; 335 335 function = "mmc1"; ··· 337 337 bias-pull-up; 338 338 }; 339 339 340 - mmc2_8bit_pins: mmc2_8bit { 340 + mmc2_8bit_pins: mmc2-8bit-pins { 341 341 pins = "PC5", "PC6", "PC8", 342 342 "PC9", "PC10", "PC11", 343 343 "PC12", "PC13", "PC14", ··· 378 378 bias-pull-up; 379 379 }; 380 380 381 - pwm0_pins: pwm0 { 381 + pwm0_pin: pwm0-pin { 382 382 pins = "PH0"; 383 383 function = "pwm0"; 384 384 }; 385 385 386 - uart0_pins_a: uart0@0 { 386 + uart0_pf_pins: uart0-pf-pins { 387 387 pins = "PF2", "PF4"; 388 388 function = "uart0"; 389 389 }; 390 390 391 - uart1_pins_a: uart1@0 { 391 + uart1_pg_pins: uart1-pg-pins { 392 392 pins = "PG6", "PG7"; 393 393 function = "uart1"; 394 394 }; 395 395 396 - uart1_pins_cts_rts_a: uart1-cts-rts@0 { 396 + uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins { 397 397 pins = "PG8", "PG9"; 398 398 function = "uart1"; 399 399 }; ··· 658 658 #interrupt-cells = <3>; 659 659 #gpio-cells = <3>; 660 660 661 - r_rsb_pins: r_rsb { 661 + r_rsb_pins: r-rsb-pins { 662 662 pins = "PL0", "PL1"; 663 663 function = "s_rsb"; 664 664 drive-strength = <20>; 665 665 bias-pull-up; 666 666 }; 667 667 668 - r_uart_pins_a: r_uart@0 { 668 + r_uart_pins_a: r-uart-pins { 669 669 pins = "PL2", "PL3"; 670 670 function = "s_uart"; 671 671 };
+3 -3
arch/arm/boot/dts/sun8i-a23-evb.dts
··· 66 66 67 67 &i2c0 { 68 68 pinctrl-names = "default"; 69 - pinctrl-0 = <&i2c0_pins_a>; 69 + pinctrl-0 = <&i2c0_pins>; 70 70 status = "okay"; 71 71 }; 72 72 73 73 &i2c1 { 74 74 pinctrl-names = "default"; 75 - pinctrl-0 = <&i2c1_pins_a>; 75 + pinctrl-0 = <&i2c1_pins>; 76 76 status = "okay"; 77 77 }; 78 78 ··· 104 104 105 105 &mmc0 { 106 106 pinctrl-names = "default"; 107 - pinctrl-0 = <&mmc0_pins_a>; 107 + pinctrl-0 = <&mmc0_pins>; 108 108 vmmc-supply = <&reg_vcc3v0>; 109 109 bus-width = <4>; 110 110 cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
+1 -1
arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts
··· 69 69 70 70 &mmc1 { 71 71 pinctrl-names = "default"; 72 - pinctrl-0 = <&mmc1_pins_a>; 72 + pinctrl-0 = <&mmc1_pg_pins>; 73 73 vmmc-supply = <&reg_dldo1>; 74 74 mmc-pwrseq = <&wifi_pwrseq>; 75 75 bus-width = <4>;
+1 -1
arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts
··· 62 62 63 63 &mmc1 { 64 64 pinctrl-names = "default"; 65 - pinctrl-0 = <&mmc1_pins_a>; 65 + pinctrl-0 = <&mmc1_pg_pins>; 66 66 vmmc-supply = <&reg_dldo1>; 67 67 mmc-pwrseq = <&wifi_pwrseq>; 68 68 bus-width = <4>;
+1 -1
arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts
··· 79 79 80 80 &mmc1 { 81 81 pinctrl-names = "default"; 82 - pinctrl-0 = <&mmc1_pins_a>; 82 + pinctrl-0 = <&mmc1_pg_pins>; 83 83 vmmc-supply = <&reg_dldo1>; 84 84 bus-width = <4>; 85 85 non-removable;
+3 -3
arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts
··· 72 72 73 73 &mmc1 { 74 74 pinctrl-names = "default"; 75 - pinctrl-0 = <&mmc1_pins_a>; 75 + pinctrl-0 = <&mmc1_pg_pins>; 76 76 vmmc-supply = <&reg_dldo1>; 77 77 bus-width = <4>; 78 78 non-removable; ··· 97 97 98 98 &uart1 { 99 99 pinctrl-names = "default"; 100 - pinctrl-0 = <&uart1_pins_a>, 101 - <&uart1_pins_cts_rts_a>; 100 + pinctrl-0 = <&uart1_pg_pins>, 101 + <&uart1_cts_rts_pg_pins>; 102 102 status = "okay"; 103 103 };
+2 -2
arch/arm/boot/dts/sun8i-a33-olinuxino.dts
··· 83 83 84 84 &mmc0 { 85 85 pinctrl-names = "default"; 86 - pinctrl-0 = <&mmc0_pins_a>; 86 + pinctrl-0 = <&mmc0_pins>; 87 87 vmmc-supply = <&reg_dcdc1>; 88 88 bus-width = <4>; 89 89 cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ ··· 207 207 208 208 &uart0 { 209 209 pinctrl-names = "default"; 210 - pinctrl-0 = <&uart0_pins_b>; 210 + pinctrl-0 = <&uart0_pb_pins>; 211 211 status = "okay"; 212 212 }; 213 213
+2 -2
arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
··· 141 141 142 142 &mmc0 { 143 143 pinctrl-names = "default"; 144 - pinctrl-0 = <&mmc0_pins_a>; 144 + pinctrl-0 = <&mmc0_pins>; 145 145 vmmc-supply = <&reg_dcdc1>; 146 146 bus-width = <4>; 147 147 cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ ··· 268 268 269 269 &uart0 { 270 270 pinctrl-names = "default"; 271 - pinctrl-0 = <&uart0_pins_b>; 271 + pinctrl-0 = <&uart0_pb_pins>; 272 272 status = "okay"; 273 273 }; 274 274
+1 -1
arch/arm/boot/dts/sun8i-a33.dtsi
··· 552 552 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 553 553 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 554 554 555 - uart0_pins_b: uart0@1 { 555 + uart0_pb_pins: uart0-pb-pins { 556 556 pins = "PB0", "PB1"; 557 557 function = "uart0"; 558 558 };
+1 -1
arch/arm/boot/dts/sun8i-q8-common.dtsi
··· 70 70 71 71 &mmc1 { 72 72 pinctrl-names = "default"; 73 - pinctrl-0 = <&mmc1_pins_a>; 73 + pinctrl-0 = <&mmc1_pg_pins>; 74 74 vmmc-supply = <&reg_dldo1>; 75 75 mmc-pwrseq = <&wifi_pwrseq>; 76 76 bus-width = <4>;
+7 -7
arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
··· 127 127 /* This is the i2c bus exposed on the DSI connector for the touch panel */ 128 128 &i2c0 { 129 129 pinctrl-names = "default"; 130 - pinctrl-0 = <&i2c0_pins_a>; 130 + pinctrl-0 = <&i2c0_pins>; 131 131 status = "disabled"; 132 132 }; 133 133 134 134 /* This is the i2c bus exposed on the GPIO header */ 135 135 &i2c1 { 136 136 pinctrl-names = "default"; 137 - pinctrl-0 = <&i2c1_pins_a>; 137 + pinctrl-0 = <&i2c1_pins>; 138 138 status = "disabled"; 139 139 }; 140 140 141 141 /* This is the i2c bus exposed on the CSI connector to control the sensor */ 142 142 &i2c2 { 143 143 pinctrl-names = "default"; 144 - pinctrl-0 = <&i2c2_pins_a>; 144 + pinctrl-0 = <&i2c2_pins>; 145 145 status = "disabled"; 146 146 }; 147 147 148 148 &mmc0 { 149 149 pinctrl-names = "default"; 150 - pinctrl-0 = <&mmc0_pins_a>; 150 + pinctrl-0 = <&mmc0_pins>; 151 151 vmmc-supply = <&reg_dcdc1>; 152 152 bus-width = <4>; 153 153 cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ ··· 156 156 157 157 &mmc1 { 158 158 pinctrl-names = "default"; 159 - pinctrl-0 = <&mmc1_pins_a>; 159 + pinctrl-0 = <&mmc1_pg_pins>; 160 160 vmmc-supply = <&reg_aldo1>; 161 161 mmc-pwrseq = <&wifi_pwrseq>; 162 162 bus-width = <4>; ··· 292 292 293 293 &uart0 { 294 294 pinctrl-names = "default"; 295 - pinctrl-0 = <&uart0_pins_b>; 295 + pinctrl-0 = <&uart0_pb_pins>; 296 296 status = "okay"; 297 297 }; 298 298 299 299 &uart1 { 300 300 pinctrl-names = "default"; 301 - pinctrl-0 = <&uart1_pins_a>, <&uart1_pins_cts_rts_a>; 301 + pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>; 302 302 status = "okay"; 303 303 }; 304 304
+1 -1
arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts
··· 25 25 * PF can also be used for the SD card so PB is preferred. 26 26 */ 27 27 pinctrl-names = "default"; 28 - pinctrl-0 = <&uart0_pins_a>; 28 + pinctrl-0 = <&uart0_pf_pins>; 29 29 status = "okay"; 30 30 }; 31 31
+4 -4
arch/arm/boot/dts/sun8i-r16-parrot.dts
··· 96 96 97 97 &i2c1 { 98 98 pinctrl-names = "default"; 99 - pinctrl-0 = <&i2c1_pins_a>; 99 + pinctrl-0 = <&i2c1_pins>; 100 100 status = "okay"; 101 101 102 102 /* ··· 127 127 128 128 &mmc0 { 129 129 pinctrl-names = "default"; 130 - pinctrl-0 = <&mmc0_pins_a>; 130 + pinctrl-0 = <&mmc0_pins>; 131 131 vmmc-supply = <&reg_dcdc1>; 132 132 cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ 133 133 bus-width = <4>; ··· 136 136 137 137 &mmc1 { 138 138 pinctrl-names = "default"; 139 - pinctrl-0 = <&mmc1_pins_a>; 139 + pinctrl-0 = <&mmc1_pg_pins>; 140 140 vmmc-supply = <&reg_aldo1>; 141 141 mmc-pwrseq = <&wifi_pwrseq>; 142 142 bus-width = <4>; ··· 303 303 304 304 &uart0 { 305 305 pinctrl-names = "default"; 306 - pinctrl-0 = <&uart0_pins_b>; 306 + pinctrl-0 = <&uart0_pb_pins>; 307 307 status = "okay"; 308 308 }; 309 309
+10 -1
arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
··· 62 62 }; 63 63 64 64 &i2c0 { 65 + pinctrl-0 = <&i2c0_pins>; 65 66 /* 66 67 * The gsl1680 is rated at 400KHz and it will not work reliable at 67 68 * 100KHz, this has been confirmed on multiple different q8 tablets. ··· 80 79 }; 81 80 }; 82 81 82 + &i2c1 { 83 + pinctrl-0 = <&i2c1_pins>; 84 + }; 85 + 83 86 &mmc0 { 84 87 pinctrl-names = "default"; 85 - pinctrl-0 = <&mmc0_pins_a>; 88 + pinctrl-0 = <&mmc0_pins>; 86 89 vmmc-supply = <&reg_dcdc1>; 87 90 bus-width = <4>; 88 91 cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ ··· 99 94 function = "gpio_in"; 100 95 bias-pull-up; 101 96 }; 97 + }; 98 + 99 + &pwm { 100 + pinctrl-0 = <&pwm0_pin>; 102 101 }; 103 102 104 103 &r_rsb {