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drm/i915/audio: Consider fractional vdsc bpp while computing tu_data
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.
v2:
-Fix tu_data calculation while dealing with U6.4 format. (Stan)
v3:
-Use BPP_X16_FMT to print vdsc bpp.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
Link: https://patchwork.freedesktop.org/patch/msgid/20231110101020.4067342-5-ankit.k.nautiyal@intel.com
+8
-8
+8
-8
drivers/gpu/drm/i915/display/intel_audio.c
+8
-8
drivers/gpu/drm/i915/display/intel_audio.c
···
521
521
unsigned int link_clks_available, link_clks_required;
522
522
unsigned int tu_data, tu_line, link_clks_active;
523
523
unsigned int h_active, h_total, hblank_delta, pixel_clk;
524
-
unsigned int fec_coeff, cdclk, vdsc_bpp;
524
+
unsigned int fec_coeff, cdclk, vdsc_bppx16;
525
525
unsigned int link_clk, lanes;
526
526
unsigned int hblank_rise;
527
527
528
528
h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
529
529
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
530
530
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
531
-
vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
531
+
vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;
532
532
cdclk = i915->display.cdclk.hw.cdclk;
533
533
/* fec= 0.972261, using rounding multiplier of 1000000 */
534
534
fec_coeff = 972261;
535
535
link_clk = crtc_state->port_clock;
536
536
lanes = crtc_state->lane_count;
537
537
538
-
drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
539
-
"lanes = %u vdsc_bpp = %u cdclk = %u\n",
540
-
h_active, link_clk, lanes, vdsc_bpp, cdclk);
538
+
drm_dbg_kms(&i915->drm,
539
+
"h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " BPP_X16_FMT " cdclk = %u\n",
540
+
h_active, link_clk, lanes, BPP_X16_ARGS(vdsc_bppx16), cdclk);
541
541
542
-
if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
542
+
if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
543
543
return 0;
544
544
545
545
link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
···
551
551
hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
552
552
mul_u32_u32(link_clk, cdclk));
553
553
554
-
tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000),
555
-
mul_u32_u32(link_clk * lanes, fec_coeff));
554
+
tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),
555
+
mul_u32_u32(link_clk * lanes * 16, fec_coeff));
556
556
tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
557
557
mul_u32_u32(64 * pixel_clk, 1000000));
558
558
link_clks_active = (tu_line - 1) * 64 + tu_data;