commit 08f41f7c35eca72aab1908a9ddb3f93a645b7cb8 · tjh.dev/kernel

+1

MAINTAINERS

··· 1362 1362 F: drivers/*/*rockchip* 1363 1363 F: drivers/*/*/*rockchip* 1364 1364 F: sound/soc/rockchip/ 1365 + N: rockchip 1365 1366 1366 1367 ARM/SAMSUNG EXYNOS ARM ARCHITECTURES 1367 1368 M: Kukjin Kim <kgene@kernel.org>

+1

arch/arm/Kconfig

··· 619 619 select GENERIC_CLOCKEVENTS 620 620 select GPIO_PXA 621 621 select HAVE_IDE 622 + select IRQ_DOMAIN 622 623 select MULTI_IRQ_HANDLER 623 624 select PLAT_PXA 624 625 select SPARSE_IRQ

+19

arch/arm/boot/dts/dm8168-evm.dts

··· 36 36 >; 37 37 }; 38 38 39 + mmc_pins: pinmux_mmc_pins { 40 + pinctrl-single,pins = < 41 + DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */ 42 + DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */ 43 + DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */ 44 + DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */ 45 + DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */ 46 + DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */ 47 + DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */ 48 + DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */ 49 + DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */ 50 + >; 51 + }; 52 + 39 53 usb0_pins: pinmux_usb0_pins { 40 54 pinctrl-single,pins = < 41 55 DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */ ··· 151 137 }; 152 138 153 139 &mmc1 { 140 + pinctrl-names = "default"; 141 + pinctrl-0 = <&mmc_pins>; 154 142 vmmc-supply = <&vmmcsd_fixed>; 143 + bus-width = <4>; 144 + cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; 145 + wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; 155 146 }; 156 147 157 148 /* At least dm8168-evm rev c won't support multipoint, later may */

+14 -4

arch/arm/boot/dts/dm816x.dtsi

··· 150 150 }; 151 151 152 152 gpio1: gpio@48032000 { 153 - compatible = "ti,omap3-gpio"; 153 + compatible = "ti,omap4-gpio"; 154 154 ti,hwmods = "gpio1"; 155 + ti,gpio-always-on; 155 156 reg = <0x48032000 0x1000>; 156 - interrupts = <97>; 157 + interrupts = <96>; 158 + gpio-controller; 159 + #gpio-cells = <2>; 160 + interrupt-controller; 161 + #interrupt-cells = <2>; 157 162 }; 158 163 159 164 gpio2: gpio@4804c000 { 160 - compatible = "ti,omap3-gpio"; 165 + compatible = "ti,omap4-gpio"; 161 166 ti,hwmods = "gpio2"; 167 + ti,gpio-always-on; 162 168 reg = <0x4804c000 0x1000>; 163 - interrupts = <99>; 169 + interrupts = <98>; 170 + gpio-controller; 171 + #gpio-cells = <2>; 172 + interrupt-controller; 173 + #interrupt-cells = <2>; 164 174 }; 165 175 166 176 gpmc: gpmc@50000000 {

-2

arch/arm/boot/dts/dra7.dtsi

··· 1111 1111 "wkupclk", "refclk", 1112 1112 "div-clk", "phy-div"; 1113 1113 #phy-cells = <0>; 1114 - ti,hwmods = "pcie1-phy"; 1115 1114 }; 1116 1115 1117 1116 pcie2_phy: pciephy@4a095000 { ··· 1129 1130 "wkupclk", "refclk", 1130 1131 "div-clk", "phy-div"; 1131 1132 #phy-cells = <0>; 1132 - ti,hwmods = "pcie2-phy"; 1133 1133 status = "disabled"; 1134 1134 }; 1135 1135 };

+4

arch/arm/boot/dts/omap3.dtsi

··· 92 92 ti,hwmods = "aes"; 93 93 reg = <0x480c5000 0x50>; 94 94 interrupts = <0>; 95 + dmas = <&sdma 65 &sdma 66>; 96 + dma-names = "tx", "rx"; 95 97 }; 96 98 97 99 prm: prm@48306000 { ··· 552 550 ti,hwmods = "sham"; 553 551 reg = <0x480c3000 0x64>; 554 552 interrupts = <49>; 553 + dmas = <&sdma 69>; 554 + dma-names = "rx"; 555 555 }; 556 556 557 557 smartreflex_core: smartreflex@480cb000 {

+1

arch/arm/boot/dts/rk3288.dtsi

··· 411 411 "mac_clk_rx", "mac_clk_tx", 412 412 "clk_mac_ref", "clk_mac_refout", 413 413 "aclk_mac", "pclk_mac"; 414 + status = "disabled"; 414 415 }; 415 416 416 417 usb_host0_ehci: usb@ff500000 {

+1 -1

arch/arm/boot/dts/socfpga.dtsi

··· 660 660 #address-cells = <1>; 661 661 #size-cells = <0>; 662 662 reg = <0xfff01000 0x1000>; 663 - interrupts = <0 156 4>; 663 + interrupts = <0 155 4>; 664 664 num-cs = <4>; 665 665 clocks = <&spi_m_clk>; 666 666 status = "disabled";

+16

arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts

··· 56 56 model = "Olimex A10-OLinuXino-LIME"; 57 57 compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10"; 58 58 59 + cpus { 60 + cpu0: cpu@0 { 61 + /* 62 + * The A10-Lime is known to be unstable 63 + * when running at 1008 MHz 64 + */ 65 + operating-points = < 66 + /* kHz uV */ 67 + 912000 1350000 68 + 864000 1300000 69 + 624000 1250000 70 + >; 71 + cooling-max-level = <2>; 72 + }; 73 + }; 74 + 59 75 soc@01c00000 { 60 76 emac: ethernet@01c0b000 { 61 77 pinctrl-names = "default";

+1 -2

arch/arm/boot/dts/sun4i-a10.dtsi

··· 75 75 clock-latency = <244144>; /* 8 32k periods */ 76 76 operating-points = < 77 77 /* kHz uV */ 78 - 1056000 1500000 79 78 1008000 1400000 80 79 912000 1350000 81 80 864000 1300000 ··· 82 83 >; 83 84 #cooling-cells = <2>; 84 85 cooling-min-level = <0>; 85 - cooling-max-level = <4>; 86 + cooling-max-level = <3>; 86 87 }; 87 88 }; 88 89

+1 -2

arch/arm/boot/dts/sun5i-a13.dtsi

··· 47 47 clock-latency = <244144>; /* 8 32k periods */ 48 48 operating-points = < 49 49 /* kHz uV */ 50 - 1104000 1500000 51 50 1008000 1400000 52 51 912000 1350000 53 52 864000 1300000 ··· 56 57 >; 57 58 #cooling-cells = <2>; 58 59 cooling-min-level = <0>; 59 - cooling-max-level = <6>; 60 + cooling-max-level = <5>; 60 61 }; 61 62 }; 62 63

+1 -2

arch/arm/boot/dts/sun7i-a20.dtsi

··· 105 105 clock-latency = <244144>; /* 8 32k periods */ 106 106 operating-points = < 107 107 /* kHz uV */ 108 - 1008000 1450000 109 108 960000 1400000 110 109 912000 1400000 111 110 864000 1300000 ··· 115 116 >; 116 117 #cooling-cells = <2>; 117 118 cooling-min-level = <0>; 118 - cooling-max-level = <7>; 119 + cooling-max-level = <6>; 119 120 }; 120 121 121 122 cpu@1 {

+2

arch/arm/mach-omap2/id.c

··· 720 720 return kasprintf(GFP_KERNEL, "OMAP4"); 721 721 else if (soc_is_omap54xx()) 722 722 return kasprintf(GFP_KERNEL, "OMAP5"); 723 + else if (soc_is_am33xx() || soc_is_am335x()) 724 + return kasprintf(GFP_KERNEL, "AM33xx"); 723 725 else if (soc_is_am43xx()) 724 726 return kasprintf(GFP_KERNEL, "AM43xx"); 725 727 else if (soc_is_dra7xx())

+48 -63

arch/arm/mach-pxa/irq.c

··· 11 11 * it under the terms of the GNU General Public License version 2 as 12 12 * published by the Free Software Foundation. 13 13 */ 14 + #include <linux/bitops.h> 14 15 #include <linux/init.h> 15 16 #include <linux/module.h> 16 17 #include <linux/interrupt.h> ··· 41 40 #define ICHP_VAL_IRQ (1 << 31) 42 41 #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) 43 42 #define IPR_VALID (1 << 31) 44 - #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) 45 43 46 44 #define MAX_INTERNAL_IRQS 128 47 45 ··· 51 51 static void __iomem *pxa_irq_base; 52 52 static int pxa_internal_irq_nr; 53 53 static bool cpu_has_ipr; 54 + static struct irq_domain *pxa_irq_domain; 54 55 55 56 static inline void __iomem *irq_base(int i) 56 57 { ··· 67 66 void pxa_mask_irq(struct irq_data *d) 68 67 { 69 68 void __iomem *base = irq_data_get_irq_chip_data(d); 69 + irq_hw_number_t irq = irqd_to_hwirq(d); 70 70 uint32_t icmr = __raw_readl(base + ICMR); 71 71 72 - icmr &= ~(1 << IRQ_BIT(d->irq)); 72 + icmr &= ~BIT(irq & 0x1f); 73 73 __raw_writel(icmr, base + ICMR); 74 74 } 75 75 76 76 void pxa_unmask_irq(struct irq_data *d) 77 77 { 78 78 void __iomem *base = irq_data_get_irq_chip_data(d); 79 + irq_hw_number_t irq = irqd_to_hwirq(d); 79 80 uint32_t icmr = __raw_readl(base + ICMR); 80 81 81 - icmr |= 1 << IRQ_BIT(d->irq); 82 + icmr |= BIT(irq & 0x1f); 82 83 __raw_writel(icmr, base + ICMR); 83 84 } 84 85 ··· 121 118 } while (1); 122 119 } 123 120 124 - void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) 121 + static int pxa_irq_map(struct irq_domain *h, unsigned int virq, 122 + irq_hw_number_t hw) 125 123 { 126 - int irq, i, n; 124 + void __iomem *base = irq_base(hw / 32); 127 125 128 - BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 126 + /* initialize interrupt priority */ 127 + if (cpu_has_ipr) 128 + __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw)); 129 + 130 + irq_set_chip_and_handler(virq, &pxa_internal_irq_chip, 131 + handle_level_irq); 132 + irq_set_chip_data(virq, base); 133 + set_irq_flags(virq, IRQF_VALID); 134 + 135 + return 0; 136 + } 137 + 138 + static struct irq_domain_ops pxa_irq_ops = { 139 + .map = pxa_irq_map, 140 + .xlate = irq_domain_xlate_onecell, 141 + }; 142 + 143 + static __init void 144 + pxa_init_irq_common(struct device_node *node, int irq_nr, 145 + int (*fn)(struct irq_data *, unsigned int)) 146 + { 147 + int n; 129 148 130 149 pxa_internal_irq_nr = irq_nr; 131 - cpu_has_ipr = !cpu_is_pxa25x(); 132 - pxa_irq_base = io_p2v(0x40d00000); 150 + pxa_irq_domain = irq_domain_add_legacy(node, irq_nr, 151 + PXA_IRQ(0), 0, 152 + &pxa_irq_ops, NULL); 153 + if (!pxa_irq_domain) 154 + panic("Unable to add PXA IRQ domain\n"); 155 + irq_set_default_host(pxa_irq_domain); 133 156 134 157 for (n = 0; n < irq_nr; n += 32) { 135 158 void __iomem *base = irq_base(n >> 5); 136 159 137 160 __raw_writel(0, base + ICMR); /* disable all IRQs */ 138 161 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 139 - for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { 140 - /* initialize interrupt priority */ 141 - if (cpu_has_ipr) 142 - __raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i)); 143 - 144 - irq = PXA_IRQ(i); 145 - irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, 146 - handle_level_irq); 147 - irq_set_chip_data(irq, base); 148 - set_irq_flags(irq, IRQF_VALID); 149 - } 150 162 } 151 - 152 163 /* only unmasked interrupts kick us out of idle */ 153 164 __raw_writel(1, irq_base(0) + ICCR); 154 165 155 166 pxa_internal_irq_chip.irq_set_wake = fn; 167 + } 168 + 169 + void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) 170 + { 171 + BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 172 + 173 + pxa_irq_base = io_p2v(0x40d00000); 174 + cpu_has_ipr = !cpu_is_pxa25x(); 175 + pxa_init_irq_common(NULL, irq_nr, fn); 156 176 } 157 177 158 178 #ifdef CONFIG_PM ··· 229 203 }; 230 204 231 205 #ifdef CONFIG_OF 232 - static struct irq_domain *pxa_irq_domain; 233 - 234 - static int pxa_irq_map(struct irq_domain *h, unsigned int virq, 235 - irq_hw_number_t hw) 236 - { 237 - void __iomem *base = irq_base(hw / 32); 238 - 239 - /* initialize interrupt priority */ 240 - if (cpu_has_ipr) 241 - __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw)); 242 - 243 - irq_set_chip_and_handler(hw, &pxa_internal_irq_chip, 244 - handle_level_irq); 245 - irq_set_chip_data(hw, base); 246 - set_irq_flags(hw, IRQF_VALID); 247 - 248 - return 0; 249 - } 250 - 251 - static struct irq_domain_ops pxa_irq_ops = { 252 - .map = pxa_irq_map, 253 - .xlate = irq_domain_xlate_onecell, 254 - }; 255 - 256 206 static const struct of_device_id intc_ids[] __initconst = { 257 207 { .compatible = "marvell,pxa-intc", }, 258 208 {} ··· 238 236 { 239 237 struct device_node *node; 240 238 struct resource res; 241 - int n, ret; 239 + int ret; 242 240 243 241 node = of_find_matching_node(NULL, intc_ids); 244 242 if (!node) { ··· 269 267 return; 270 268 } 271 269 272 - pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0, 273 - &pxa_irq_ops, NULL); 274 - if (!pxa_irq_domain) 275 - panic("Unable to add PXA IRQ domain\n"); 276 - 277 - irq_set_default_host(pxa_irq_domain); 278 - 279 - for (n = 0; n < pxa_internal_irq_nr; n += 32) { 280 - void __iomem *base = irq_base(n >> 5); 281 - 282 - __raw_writel(0, base + ICMR); /* disable all IRQs */ 283 - __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 284 - } 285 - 286 - /* only unmasked interrupts kick us out of idle */ 287 - __raw_writel(1, irq_base(0) + ICCR); 288 - 289 - pxa_internal_irq_chip.irq_set_wake = fn; 270 + pxa_init_irq_common(node, pxa_internal_irq_nr, fn); 290 271 } 291 272 #endif /* CONFIG_OF */

+1 -1

arch/arm/mach-pxa/zeus.c

··· 412 412 }; 413 413 414 414 static struct platform_device can_regulator_device = { 415 - .name = "reg-fixed-volage", 415 + .name = "reg-fixed-voltage", 416 416 .id = 0, 417 417 .dev = { 418 418 .platform_data = &can_regulator_pdata,

+2 -6

arch/arm/mach-sunxi/Kconfig

··· 1 1 menuconfig ARCH_SUNXI 2 2 bool "Allwinner SoCs" if ARCH_MULTI_V7 3 3 select ARCH_REQUIRE_GPIOLIB 4 + select ARCH_HAS_RESET_CONTROLLER 4 5 select CLKSRC_MMIO 5 6 select GENERIC_IRQ_CHIP 6 7 select PINCTRL 7 8 select SUN4I_TIMER 9 + select RESET_CONTROLLER 8 10 9 11 if ARCH_SUNXI 10 12 ··· 22 20 config MACH_SUN6I 23 21 bool "Allwinner A31 (sun6i) SoCs support" 24 22 default ARCH_SUNXI 25 - select ARCH_HAS_RESET_CONTROLLER 26 23 select ARM_GIC 27 24 select MFD_SUN6I_PRCM 28 - select RESET_CONTROLLER 29 25 select SUN5I_HSTIMER 30 26 31 27 config MACH_SUN7I ··· 37 37 config MACH_SUN8I 38 38 bool "Allwinner A23 (sun8i) SoCs support" 39 39 default ARCH_SUNXI 40 - select ARCH_HAS_RESET_CONTROLLER 41 40 select ARM_GIC 42 41 select MFD_SUN6I_PRCM 43 - select RESET_CONTROLLER 44 42 45 43 config MACH_SUN9I 46 44 bool "Allwinner (sun9i) SoCs support" 47 45 default ARCH_SUNXI 48 - select ARCH_HAS_RESET_CONTROLLER 49 46 select ARM_GIC 50 - select RESET_CONTROLLER 51 47 52 48 endif

+14 -1

arch/arm/plat-omap/dmtimer.c

··· 799 799 struct device *dev = &pdev->dev; 800 800 const struct of_device_id *match; 801 801 const struct dmtimer_platform_data *pdata; 802 + int ret; 802 803 803 804 match = of_match_device(of_match_ptr(omap_timer_match), dev); 804 805 pdata = match ? match->data : dev->platform_data; ··· 861 860 } 862 861 863 862 if (!timer->reserved) { 864 - pm_runtime_get_sync(dev); 863 + ret = pm_runtime_get_sync(dev); 864 + if (ret < 0) { 865 + dev_err(dev, "%s: pm_runtime_get_sync failed!\n", 866 + __func__); 867 + goto err_get_sync; 868 + } 865 869 __omap_dm_timer_init_regs(timer); 866 870 pm_runtime_put(dev); 867 871 } ··· 879 873 dev_dbg(dev, "Device Probed.\n"); 880 874 881 875 return 0; 876 + 877 + err_get_sync: 878 + pm_runtime_put_noidle(dev); 879 + pm_runtime_disable(dev); 880 + return ret; 882 881 } 883 882 884 883 /** ··· 909 898 break; 910 899 } 911 900 spin_unlock_irqrestore(&dm_timer_lock, flags); 901 + 902 + pm_runtime_disable(&pdev->dev); 912 903 913 904 return ret; 914 905 }

+1 -1

arch/arm64/boot/dts/arm/juno-clocks.dtsi

··· 8 8 */ 9 9 10 10 /* SoC fixed clocks */ 11 - soc_uartclk: refclk72738khz { 11 + soc_uartclk: refclk7273800hz { 12 12 compatible = "fixed-clock"; 13 13 #clock-cells = <0>; 14 14 clock-frequency = <7273800>;