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Merge tag 'exynos-drm-next-for-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next

New feature
- Add Decon driver support for Exynos7870 SoC
. This patch adds driver data and support for Exynos7870 SoC
in the Exynos7 Decon driver

Bug fixups for exynos7_drm_decon.c module
- Properly clear channels during bind
. This patch implements shadow protection/unprotection to clear
DECON channels properly, preventing kernel panic
- Fix ideal_clk by converting it to HZ
. This patch corrects the clkdiv values by converting ideal_clk to Hz
for consistency
- Fix uninitialized crtc reference in functions
. This patch modifies functions to accept a pointer to
the decon_context struct to avoid uninitialized references

Cleanups
- Remove unused prototype for crtc
. This patch removes unused prototypes
exynos_drm_crtc_wait_pending_update
exynos_drm_crtc_finish_update
- And just typo fixup

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Inki Dae <inki.dae@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241104031341.36549-1-inki.dae@samsung.com

Dave Airlie 086ed1d5 fb6c5b1f

+87 -55
+79 -43
drivers/gpu/drm/exynos/exynos7_drm_decon.c
··· 37 37 38 38 #define WINDOWS_NR 2 39 39 40 + struct decon_data { 41 + unsigned int vidw_buf_start_base; 42 + unsigned int shadowcon_win_protect_shift; 43 + unsigned int wincon_burstlen_shift; 44 + }; 45 + 46 + static struct decon_data exynos7_decon_data = { 47 + .vidw_buf_start_base = 0x80, 48 + .shadowcon_win_protect_shift = 10, 49 + .wincon_burstlen_shift = 11, 50 + }; 51 + 52 + static struct decon_data exynos7870_decon_data = { 53 + .vidw_buf_start_base = 0x880, 54 + .shadowcon_win_protect_shift = 8, 55 + .wincon_burstlen_shift = 10, 56 + }; 57 + 40 58 struct decon_context { 41 59 struct device *dev; 42 60 struct drm_device *drm_dev; ··· 73 55 wait_queue_head_t wait_vsync_queue; 74 56 atomic_t wait_vsync_event; 75 57 58 + const struct decon_data *data; 76 59 struct drm_encoder *encoder; 77 60 }; 78 61 79 62 static const struct of_device_id decon_driver_dt_match[] = { 80 - {.compatible = "samsung,exynos7-decon"}, 63 + { 64 + .compatible = "samsung,exynos7-decon", 65 + .data = &exynos7_decon_data, 66 + }, 67 + { 68 + .compatible = "samsung,exynos7870-decon", 69 + .data = &exynos7870_decon_data, 70 + }, 81 71 {}, 82 72 }; 83 73 MODULE_DEVICE_TABLE(of, decon_driver_dt_match); ··· 107 81 DRM_PLANE_TYPE_CURSOR, 108 82 }; 109 83 110 - static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) 84 + /** 85 + * decon_shadow_protect_win() - disable updating values from shadow registers at vsync 86 + * 87 + * @ctx: display and enhancement controller context 88 + * @win: window to protect registers for 89 + * @protect: 1 to protect (disable updates) 90 + */ 91 + static void decon_shadow_protect_win(struct decon_context *ctx, 92 + unsigned int win, bool protect) 111 93 { 112 - struct decon_context *ctx = crtc->ctx; 94 + u32 bits, val; 95 + unsigned int shift = ctx->data->shadowcon_win_protect_shift; 113 96 97 + bits = SHADOWCON_WINx_PROTECT(shift, win); 98 + 99 + val = readl(ctx->regs + SHADOWCON); 100 + if (protect) 101 + val |= bits; 102 + else 103 + val &= ~bits; 104 + writel(val, ctx->regs + SHADOWCON); 105 + } 106 + 107 + static void decon_wait_for_vblank(struct decon_context *ctx) 108 + { 114 109 if (ctx->suspended) 115 110 return; 116 111 ··· 147 100 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); 148 101 } 149 102 150 - static void decon_clear_channels(struct exynos_drm_crtc *crtc) 103 + static void decon_clear_channels(struct decon_context *ctx) 151 104 { 152 - struct decon_context *ctx = crtc->ctx; 153 105 unsigned int win, ch_enabled = 0; 106 + u32 val; 154 107 155 108 /* Check if any channel is enabled. */ 156 109 for (win = 0; win < WINDOWS_NR; win++) { 157 - u32 val = readl(ctx->regs + WINCON(win)); 110 + val = readl(ctx->regs + WINCON(win)); 158 111 159 112 if (val & WINCONx_ENWIN) { 113 + decon_shadow_protect_win(ctx, win, true); 114 + 160 115 val &= ~WINCONx_ENWIN; 161 116 writel(val, ctx->regs + WINCON(win)); 162 117 ch_enabled = 1; 118 + 119 + decon_shadow_protect_win(ctx, win, false); 163 120 } 164 121 } 165 122 123 + val = readl(ctx->regs + DECON_UPDATE); 124 + val |= DECON_UPDATE_STANDALONE_F; 125 + writel(val, ctx->regs + DECON_UPDATE); 126 + 166 127 /* Wait for vsync, as disable channel takes effect at next vsync */ 167 128 if (ch_enabled) 168 - decon_wait_for_vblank(ctx->crtc); 129 + decon_wait_for_vblank(ctx); 169 130 } 170 131 171 132 static int decon_ctx_initialize(struct decon_context *ctx, ··· 181 126 { 182 127 ctx->drm_dev = drm_dev; 183 128 184 - decon_clear_channels(ctx->crtc); 129 + decon_clear_channels(ctx); 185 130 186 131 return exynos_drm_register_dma(drm_dev, ctx->dev, &ctx->dma_priv); 187 132 } ··· 195 140 static u32 decon_calc_clkdiv(struct decon_context *ctx, 196 141 const struct drm_display_mode *mode) 197 142 { 198 - unsigned long ideal_clk = mode->clock; 143 + unsigned long ideal_clk = mode->clock * 1000; 199 144 u32 clkdiv; 200 145 201 146 /* Find the clock divider value that gets us closest to ideal_clk */ ··· 318 263 { 319 264 unsigned long val; 320 265 int padding; 266 + unsigned int shift = ctx->data->wincon_burstlen_shift; 321 267 322 268 val = readl(ctx->regs + WINCON(win)); 323 269 val &= ~WINCONx_BPPMODE_MASK; ··· 326 270 switch (fb->format->format) { 327 271 case DRM_FORMAT_RGB565: 328 272 val |= WINCONx_BPPMODE_16BPP_565; 329 - val |= WINCONx_BURSTLEN_16WORD; 273 + val |= WINCONx_BURSTLEN_16WORD(shift); 330 274 break; 331 275 case DRM_FORMAT_XRGB8888: 332 276 val |= WINCONx_BPPMODE_24BPP_xRGB; 333 - val |= WINCONx_BURSTLEN_16WORD; 277 + val |= WINCONx_BURSTLEN_16WORD(shift); 334 278 break; 335 279 case DRM_FORMAT_XBGR8888: 336 280 val |= WINCONx_BPPMODE_24BPP_xBGR; 337 - val |= WINCONx_BURSTLEN_16WORD; 281 + val |= WINCONx_BURSTLEN_16WORD(shift); 338 282 break; 339 283 case DRM_FORMAT_RGBX8888: 340 284 val |= WINCONx_BPPMODE_24BPP_RGBx; 341 - val |= WINCONx_BURSTLEN_16WORD; 285 + val |= WINCONx_BURSTLEN_16WORD(shift); 342 286 break; 343 287 case DRM_FORMAT_BGRX8888: 344 288 val |= WINCONx_BPPMODE_24BPP_BGRx; 345 - val |= WINCONx_BURSTLEN_16WORD; 289 + val |= WINCONx_BURSTLEN_16WORD(shift); 346 290 break; 347 291 case DRM_FORMAT_ARGB8888: 348 292 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | 349 293 WINCONx_ALPHA_SEL; 350 - val |= WINCONx_BURSTLEN_16WORD; 294 + val |= WINCONx_BURSTLEN_16WORD(shift); 351 295 break; 352 296 case DRM_FORMAT_ABGR8888: 353 297 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | 354 298 WINCONx_ALPHA_SEL; 355 - val |= WINCONx_BURSTLEN_16WORD; 299 + val |= WINCONx_BURSTLEN_16WORD(shift); 356 300 break; 357 301 case DRM_FORMAT_RGBA8888: 358 302 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | 359 303 WINCONx_ALPHA_SEL; 360 - val |= WINCONx_BURSTLEN_16WORD; 304 + val |= WINCONx_BURSTLEN_16WORD(shift); 361 305 break; 362 306 case DRM_FORMAT_BGRA8888: 363 307 default: 364 308 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | 365 309 WINCONx_ALPHA_SEL; 366 - val |= WINCONx_BURSTLEN_16WORD; 310 + val |= WINCONx_BURSTLEN_16WORD(shift); 367 311 break; 368 312 } 369 313 ··· 379 323 380 324 padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width; 381 325 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) { 382 - val &= ~WINCONx_BURSTLEN_MASK; 383 - val |= WINCONx_BURSTLEN_8WORD; 326 + val &= ~WINCONx_BURSTLEN_MASK(shift); 327 + val |= WINCONx_BURSTLEN_8WORD(shift); 384 328 } 385 329 386 330 writel(val, ctx->regs + WINCON(win)); ··· 397 341 398 342 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 399 343 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 400 - } 401 - 402 - /** 403 - * decon_shadow_protect_win() - disable updating values from shadow registers at vsync 404 - * 405 - * @ctx: display and enhancement controller context 406 - * @win: window to protect registers for 407 - * @protect: 1 to protect (disable updates) 408 - */ 409 - static void decon_shadow_protect_win(struct decon_context *ctx, 410 - unsigned int win, bool protect) 411 - { 412 - u32 bits, val; 413 - 414 - bits = SHADOWCON_WINx_PROTECT(win); 415 - 416 - val = readl(ctx->regs + SHADOWCON); 417 - if (protect) 418 - val |= bits; 419 - else 420 - val &= ~bits; 421 - writel(val, ctx->regs + SHADOWCON); 422 344 } 423 345 424 346 static void decon_atomic_begin(struct exynos_drm_crtc *crtc) ··· 425 391 unsigned int win = plane->index; 426 392 unsigned int cpp = fb->format->cpp[0]; 427 393 unsigned int pitch = fb->pitches[0]; 394 + unsigned int vidw_addr0_base = ctx->data->vidw_buf_start_base; 428 395 429 396 if (ctx->suspended) 430 397 return; ··· 442 407 443 408 /* buffer start address */ 444 409 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0); 445 - writel(val, ctx->regs + VIDW_BUF_START(win)); 410 + writel(val, ctx->regs + VIDW_BUF_START(vidw_addr0_base, win)); 446 411 447 412 padding = (pitch / cpp) - fb->width; 448 413 ··· 724 689 725 690 ctx->dev = dev; 726 691 ctx->suspended = true; 692 + ctx->data = of_device_get_match_data(dev); 727 693 728 694 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 729 695 if (i80_if_timings)
-3
drivers/gpu/drm/exynos/exynos_drm_crtc.h
··· 19 19 enum exynos_drm_output_type out_type, 20 20 const struct exynos_drm_crtc_ops *ops, 21 21 void *context); 22 - void exynos_drm_crtc_wait_pending_update(struct exynos_drm_crtc *exynos_crtc); 23 - void exynos_drm_crtc_finish_update(struct exynos_drm_crtc *exynos_crtc, 24 - struct exynos_drm_plane *exynos_plane); 25 22 26 23 /* This function gets crtc device matched with out_type. */ 27 24 struct exynos_drm_crtc *exynos_drm_crtc_get_by_type(struct drm_device *drm_dev,
+1 -1
drivers/gpu/drm/exynos/exynos_drm_gsc.c
··· 1286 1286 return ret; 1287 1287 } 1288 1288 1289 - /* context initailization */ 1289 + /* context initialization */ 1290 1290 ctx->id = pdev->id; 1291 1291 1292 1292 platform_set_drvdata(pdev, ctx);
+7 -8
drivers/gpu/drm/exynos/regs-decon7.h
··· 48 48 /* SHADOWCON */ 49 49 #define SHADOWCON 0x30 50 50 51 - #define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win))) 51 + #define SHADOWCON_WINx_PROTECT(_shf, _win) (1 << ((_shf) + (_win))) 52 52 53 53 /* WINCONx */ 54 54 #define WINCON(_win) (0x50 + ((_win) * 4)) ··· 58 58 #define WINCONx_BUFSEL_SHIFT 28 59 59 #define WINCONx_TRIPLE_BUF_MODE (0x1 << 18) 60 60 #define WINCONx_DOUBLE_BUF_MODE (0x0 << 18) 61 - #define WINCONx_BURSTLEN_16WORD (0x0 << 11) 62 - #define WINCONx_BURSTLEN_8WORD (0x1 << 11) 63 - #define WINCONx_BURSTLEN_MASK (0x1 << 11) 64 - #define WINCONx_BURSTLEN_SHIFT 11 61 + #define WINCONx_BURSTLEN_16WORD(_shf) (0x0 << (_shf)) 62 + #define WINCONx_BURSTLEN_8WORD(_shf) (0x1 << (_shf)) 63 + #define WINCONx_BURSTLEN_MASK(_shf) (0x1 << (_shf)) 65 64 #define WINCONx_BLD_PLANE (0 << 8) 66 65 #define WINCONx_BLD_PIX (1 << 8) 67 66 #define WINCONx_ALPHA_MUL (1 << 7) ··· 88 89 #define VIDOSD_H(_x) (0x80 + ((_x) * 4)) 89 90 90 91 /* Frame buffer start addresses: VIDWxxADD0n */ 91 - #define VIDW_BUF_START(_win) (0x80 + ((_win) * 0x10)) 92 - #define VIDW_BUF_START1(_win) (0x84 + ((_win) * 0x10)) 93 - #define VIDW_BUF_START2(_win) (0x88 + ((_win) * 0x10)) 92 + #define VIDW_BUF_START(_base, _win) ((_base) + ((_win) * 0x10)) 93 + #define VIDW_BUF_START1(_base, _win) ((_base) + ((_win) * 0x10)) 94 + #define VIDW_BUF_START2(_base, _win) ((_base) + ((_win) * 0x10)) 94 95 95 96 #define VIDW_WHOLE_X(_win) (0x0130 + ((_win) * 8)) 96 97 #define VIDW_WHOLE_Y(_win) (0x0134 + ((_win) * 8))