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linux
OMAPDSS: HDMI: fix regsd write
HDMI PLL's REGSD field is only set by the driver if the PLL's output
clock is over 1GHz. This is clearly an error, as REGSD should be set
always.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
+4
-5
+4
-5
drivers/video/fbdev/omap2/dss/hdmi_pll.c
+4
-5
drivers/video/fbdev/omap2/dss/hdmi_pll.c
···
124
124
r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
125
125
r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
126
126
127
-
if (fmt->dcofreq) {
128
-
/* divider programming for frequency beyond 1000Mhz */
129
-
REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
127
+
if (fmt->dcofreq)
130
128
r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
131
-
} else {
129
+
else
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130
r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
133
-
}
134
131
135
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hdmi_write_reg(pll->base, PLLCTRL_CFG2, r);
133
+
134
+
REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
136
135
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136
r = hdmi_read_reg(pll->base, PLLCTRL_CFG4);
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137
r = FLD_MOD(r, fmt->regm2, 24, 18);