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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge merom:v2.6/linux
* merom:v2.6/linux:
x86-64: write IO APIC irq routing entries in correct order
x86-64: clean up io-apic accesses
+69
-37
+69
-3
arch/x86_64/kernel/io_apic.c
+69
-3
arch/x86_64/kernel/io_apic.c
···
88
88
short apic, pin, next;
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} irq_2_pin[PIN_MAP_SIZE];
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+
struct io_apic {
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+
unsigned int index;
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+
unsigned int unused[3];
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+
unsigned int data;
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+
};
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+
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+
static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
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+
{
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+
return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
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+
+ (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
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+
}
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+
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+
static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
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+
{
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+
struct io_apic __iomem *io_apic = io_apic_base(apic);
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+
writel(reg, &io_apic->index);
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+
return readl(&io_apic->data);
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+
}
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+
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static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
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+
{
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struct io_apic __iomem *io_apic = io_apic_base(apic);
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+
writel(reg, &io_apic->index);
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+
writel(value, &io_apic->data);
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+
}
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+
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+
/*
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* Re-write a value: to be used for read-modify-write
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+
* cycles where the read already set up the index register.
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+
*/
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+
static inline void io_apic_modify(unsigned int apic, unsigned int value)
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+
{
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+
struct io_apic __iomem *io_apic = io_apic_base(apic);
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+
writel(value, &io_apic->data);
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+
}
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+
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+
/*
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* Synchronize the IO-APIC and the CPU by doing
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+
* a dummy read from the IO-APIC
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+
*/
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+
static inline void io_apic_sync(unsigned int apic)
132
+
{
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+
struct io_apic __iomem *io_apic = io_apic_base(apic);
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+
readl(&io_apic->data);
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+
}
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+
91
137
#define __DO_ACTION(R, ACTION, FINAL) \
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\
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{ \
···
172
126
return eu.entry;
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127
}
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128
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+
/*
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+
* When we write a new IO APIC routing entry, we need to write the high
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+
* word first! If the mask bit in the low word is clear, we will enable
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+
* the interrupt, and we need to make sure the entry is fully populated
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+
* before that happens.
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+
*/
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static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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136
{
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unsigned long flags;
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union entry_union eu;
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eu.entry = e;
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+
spin_lock_irqsave(&ioapic_lock, flags);
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+
io_apic_write(apic, 0x11 + 2*pin, eu.w2);
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+
io_apic_write(apic, 0x10 + 2*pin, eu.w1);
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+
spin_unlock_irqrestore(&ioapic_lock, flags);
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+
}
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+
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+
/*
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+
* When we mask an IO APIC routing entry, we need to write the low
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+
* word first, in order to set the mask bit before we change the
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+
* high bits!
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+
*/
151
+
static void ioapic_mask_entry(int apic, int pin)
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+
{
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+
unsigned long flags;
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+
union entry_union eu = { .entry.mask = 1 };
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+
180
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spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(apic, 0x10 + 2*pin, eu.w1);
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io_apic_write(apic, 0x11 + 2*pin, eu.w2);
···
324
256
/*
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* Disable it in the IO-APIC irq-routing table:
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*/
327
-
memset(&entry, 0, sizeof(entry));
328
-
entry.mask = 1;
329
-
ioapic_write_entry(apic, pin, entry);
259
+
ioapic_mask_entry(apic, pin);
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}
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static void clear_IO_APIC (void)
-34
include/asm-x86_64/io_apic.h
-34
include/asm-x86_64/io_apic.h
···
12
12
13
13
#define APIC_MISMATCH_DEBUG
14
14
15
-
#define IO_APIC_BASE(idx) \
16
-
((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
17
-
+ (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
18
-
19
15
/*
20
16
* The structure of the IO-APIC:
21
17
*/
···
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/* non-0 if default (table-less) MP configuration */
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extern int mpc_default_type;
117
-
118
-
static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
119
-
{
120
-
*IO_APIC_BASE(apic) = reg;
121
-
return *(IO_APIC_BASE(apic)+4);
122
-
}
123
-
124
-
static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
125
-
{
126
-
*IO_APIC_BASE(apic) = reg;
127
-
*(IO_APIC_BASE(apic)+4) = value;
128
-
}
129
-
130
-
/*
131
-
* Re-write a value: to be used for read-modify-write
132
-
* cycles where the read already set up the index register.
133
-
*/
134
-
static inline void io_apic_modify(unsigned int apic, unsigned int value)
135
-
{
136
-
*(IO_APIC_BASE(apic)+4) = value;
137
-
}
138
-
139
-
/*
140
-
* Synchronize the IO-APIC and the CPU by doing
141
-
* a dummy read from the IO-APIC
142
-
*/
143
-
static inline void io_apic_sync(unsigned int apic)
144
-
{
145
-
(void) *(IO_APIC_BASE(apic)+4);
146
-
}
147
121
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122
/* 1 if "noapic" boot option passed */
149
123
extern int skip_ioapic_setup;