tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

ARM: dts: vf610: make pinctrl nodes board specific

Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that
boards that share the same pinctrl setting do not have to define it time
and time again in <board>.dts. However, along with the devices and use
cases being added continuously, the pinctrl setting nodes under iomuxc
becomes more than expected. This bloats device tree blob for particular
board unnecessarily since only a small subset of those pinctrl setting
nodes will be used by the board. It impacts not only the DTB file size
but also the run-time device tree lookup efficiency.

The patch moves all the pinctrl data into individual boards as needed.
With the changes, the pinctrl setting nodes becomes local to particular
board, and it makes no sense to continue numbering the setting for
given peripheral. Thus, all the pinctrl phandler name gets updated to
have only peripheral name in there.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Fugang Duan <B38611@freescale.com>

Shawn Guo 07ed1eed 5a2a7d57

+88 -177
+27 -2
arch/arm/boot/dts/vf610-cosmic.dts
··· 36 36 &fec1 { 37 37 phy-mode = "rmii"; 38 38 pinctrl-names = "default"; 39 - pinctrl-0 = <&pinctrl_fec1_1>; 39 + pinctrl-0 = <&pinctrl_fec1>; 40 40 status = "okay"; 41 + }; 42 + 43 + &iomuxc { 44 + vf610-cosmic { 45 + pinctrl_fec1: fec1grp { 46 + fsl,pins = < 47 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 48 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 49 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 50 + VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 51 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 52 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 53 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 54 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 55 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 56 + >; 57 + }; 58 + 59 + pinctrl_uart1: uart1grp { 60 + fsl,pins = < 61 + VF610_PAD_PTB4__UART1_TX 0x21a2 62 + VF610_PAD_PTB5__UART1_RX 0x21a1 63 + >; 64 + }; 65 + }; 41 66 }; 42 67 43 68 &uart1 { 44 69 pinctrl-names = "default"; 45 - pinctrl-0 = <&pinctrl_uart1_1>; 70 + pinctrl-0 = <&pinctrl_uart1>; 46 71 status = "okay"; 47 72 };
+61 -5
arch/arm/boot/dts/vf610-twr.dts
··· 39 39 &dspi0 { 40 40 bus-num = <0>; 41 41 pinctrl-names = "default"; 42 - pinctrl-0 = <&pinctrl_dspi0_1>; 42 + pinctrl-0 = <&pinctrl_dspi0>; 43 43 status = "okay"; 44 44 45 45 sflash: at26df081a@0 { ··· 56 56 &fec0 { 57 57 phy-mode = "rmii"; 58 58 pinctrl-names = "default"; 59 - pinctrl-0 = <&pinctrl_fec0_1>; 59 + pinctrl-0 = <&pinctrl_fec0>; 60 60 status = "okay"; 61 61 }; 62 62 63 63 &fec1 { 64 64 phy-mode = "rmii"; 65 65 pinctrl-names = "default"; 66 - pinctrl-0 = <&pinctrl_fec1_1>; 66 + pinctrl-0 = <&pinctrl_fec1>; 67 67 status = "okay"; 68 68 }; 69 69 70 70 &i2c0 { 71 71 clock-frequency = <100000>; 72 72 pinctrl-names = "default"; 73 - pinctrl-0 = <&pinctrl_i2c0_1>; 73 + pinctrl-0 = <&pinctrl_i2c0>; 74 74 status = "okay"; 75 + }; 76 + 77 + &iomuxc { 78 + vf610-twr { 79 + pinctrl_dspi0: dspi0grp { 80 + fsl,pins = < 81 + VF610_PAD_PTB19__DSPI0_CS0 0x1182 82 + VF610_PAD_PTB20__DSPI0_SIN 0x1181 83 + VF610_PAD_PTB21__DSPI0_SOUT 0x1182 84 + VF610_PAD_PTB22__DSPI0_SCK 0x1182 85 + >; 86 + }; 87 + 88 + pinctrl_fec0: fec0grp { 89 + fsl,pins = < 90 + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 91 + VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 92 + VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 93 + VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 94 + VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 95 + VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 96 + VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 97 + VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 98 + VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 99 + VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 100 + >; 101 + }; 102 + 103 + pinctrl_fec1: fec1grp { 104 + fsl,pins = < 105 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 106 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 107 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 108 + VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 109 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 110 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 111 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 112 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 113 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 114 + >; 115 + }; 116 + 117 + pinctrl_i2c0: i2c0grp { 118 + fsl,pins = < 119 + VF610_PAD_PTB14__I2C0_SCL 0x30d3 120 + VF610_PAD_PTB15__I2C0_SDA 0x30d3 121 + >; 122 + }; 123 + 124 + pinctrl_uart1: uart1grp { 125 + fsl,pins = < 126 + VF610_PAD_PTB4__UART1_TX 0x21a2 127 + VF610_PAD_PTB5__UART1_RX 0x21a1 128 + >; 129 + }; 130 + }; 75 131 }; 76 132 77 133 &uart1 { 78 134 pinctrl-names = "default"; 79 - pinctrl-0 = <&pinctrl_uart1_1>; 135 + pinctrl-0 = <&pinctrl_uart1>; 80 136 status = "okay"; 81 137 };
-170
arch/arm/boot/dts/vf610.dtsi
··· 175 175 compatible = "fsl,vf610-iomuxc"; 176 176 reg = <0x40048000 0x1000>; 177 177 #gpio-range-cells = <3>; 178 - 179 - /* functions and groups pins */ 180 - 181 - dcu0 { 182 - pinctrl_dcu0_1: dcu0grp_1 { 183 - fsl,pins = < 184 - VF610_PAD_PTB8__GPIO_30 0x42 185 - VF610_PAD_PTE0__DCU0_HSYNC 0x42 186 - VF610_PAD_PTE1__DCU0_VSYNC 0x42 187 - VF610_PAD_PTE2__DCU0_PCLK 0x42 188 - VF610_PAD_PTE4__DCU0_DE 0x42 189 - VF610_PAD_PTE5__DCU0_R0 0x42 190 - VF610_PAD_PTE6__DCU0_R1 0x42 191 - VF610_PAD_PTE7__DCU0_R2 0x42 192 - VF610_PAD_PTE8__DCU0_R3 0x42 193 - VF610_PAD_PTE9__DCU0_R4 0x42 194 - VF610_PAD_PTE10__DCU0_R5 0x42 195 - VF610_PAD_PTE11__DCU0_R6 0x42 196 - VF610_PAD_PTE12__DCU0_R7 0x42 197 - VF610_PAD_PTE13__DCU0_G0 0x42 198 - VF610_PAD_PTE14__DCU0_G1 0x42 199 - VF610_PAD_PTE15__DCU0_G2 0x42 200 - VF610_PAD_PTE16__DCU0_G3 0x42 201 - VF610_PAD_PTE17__DCU0_G4 0x42 202 - VF610_PAD_PTE18__DCU0_G5 0x42 203 - VF610_PAD_PTE19__DCU0_G6 0x42 204 - VF610_PAD_PTE20__DCU0_G7 0x42 205 - VF610_PAD_PTE21__DCU0_B0 0x42 206 - VF610_PAD_PTE22__DCU0_B1 0x42 207 - VF610_PAD_PTE23__DCU0_B2 0x42 208 - VF610_PAD_PTE24__DCU0_B3 0x42 209 - VF610_PAD_PTE25__DCU0_B4 0x42 210 - VF610_PAD_PTE26__DCU0_B5 0x42 211 - VF610_PAD_PTE27__DCU0_B6 0x42 212 - VF610_PAD_PTE28__DCU0_B7 0x42 213 - >; 214 - }; 215 - }; 216 - 217 - dspi0 { 218 - pinctrl_dspi0_1: dspi0grp_1 { 219 - fsl,pins = < 220 - VF610_PAD_PTB19__DSPI0_CS0 0x1182 221 - VF610_PAD_PTB20__DSPI0_SIN 0x1181 222 - VF610_PAD_PTB21__DSPI0_SOUT 0x1182 223 - VF610_PAD_PTB22__DSPI0_SCK 0x1182 224 - >; 225 - }; 226 - }; 227 - 228 - esdhc1 { 229 - pinctrl_esdhc1_1: esdhc1grp_1 { 230 - fsl,pins = < 231 - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 232 - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef 233 - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef 234 - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef 235 - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef 236 - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef 237 - VF610_PAD_PTA7__GPIO_134 0x219d 238 - >; 239 - }; 240 - }; 241 - 242 - fec0 { 243 - pinctrl_fec0_1: fec0grp_1 { 244 - fsl,pins = < 245 - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 246 - VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 247 - VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 248 - VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 249 - VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 250 - VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 251 - VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 252 - VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 253 - VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 254 - VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 255 - >; 256 - }; 257 - }; 258 - 259 - fec1 { 260 - pinctrl_fec1_1: fec1grp_1 { 261 - fsl,pins = < 262 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 263 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 264 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 265 - VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 266 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 267 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 268 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 269 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 270 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 271 - >; 272 - }; 273 - }; 274 - 275 - i2c0 { 276 - pinctrl_i2c0_1: i2c0grp_1 { 277 - fsl,pins = < 278 - VF610_PAD_PTB14__I2C0_SCL 0x30d3 279 - VF610_PAD_PTB15__I2C0_SDA 0x30d3 280 - >; 281 - }; 282 - }; 283 - 284 - pwm0 { 285 - pinctrl_pwm0_1: pwm0grp_1 { 286 - fsl,pins = < 287 - VF610_PAD_PTB0__FTM0_CH0 0x1582 288 - VF610_PAD_PTB1__FTM0_CH1 0x1582 289 - VF610_PAD_PTB2__FTM0_CH2 0x1582 290 - VF610_PAD_PTB3__FTM0_CH3 0x1582 291 - VF610_PAD_PTB6__FTM0_CH6 0x1582 292 - VF610_PAD_PTB7__FTM0_CH7 0x1582 293 - >; 294 - }; 295 - }; 296 - 297 - qspi0 { 298 - pinctrl_qspi0_1: qspi0grp_1 { 299 - fsl,pins = < 300 - VF610_PAD_PTD0__QSPI0_A_QSCK 0x307b 301 - VF610_PAD_PTD1__QSPI0_A_CS0 0x307f 302 - VF610_PAD_PTD2__QSPI0_A_DATA3 0x3073 303 - VF610_PAD_PTD3__QSPI0_A_DATA2 0x3073 304 - VF610_PAD_PTD4__QSPI0_A_DATA1 0x3073 305 - VF610_PAD_PTD5__QSPI0_A_DATA0 0x307b 306 - VF610_PAD_PTD7__QSPI0_B_QSCK 0x307b 307 - VF610_PAD_PTD8__QSPI0_B_CS0 0x307f 308 - VF610_PAD_PTD9__QSPI0_B_DATA3 0x3073 309 - VF610_PAD_PTD10__QSPI0_B_DATA2 0x3073 310 - VF610_PAD_PTD11__QSPI0_B_DATA1 0x3073 311 - VF610_PAD_PTD12__QSPI0_B_DATA0 0x307b 312 - >; 313 - }; 314 - }; 315 - 316 - sai2 { 317 - pinctrl_sai2_1: sai2grp_1 { 318 - fsl,pins = < 319 - VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed 320 - VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee 321 - VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed 322 - VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed 323 - VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed 324 - VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed 325 - VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed 326 - >; 327 - }; 328 - }; 329 - 330 - uart1 { 331 - pinctrl_uart1_1: uart1grp_1 { 332 - fsl,pins = < 333 - VF610_PAD_PTB4__UART1_TX 0x21a2 334 - VF610_PAD_PTB5__UART1_RX 0x21a1 335 - >; 336 - }; 337 - }; 338 - 339 - usbvbus { 340 - pinctrl_usbvbus_1: usbvbusgrp_1 { 341 - fsl,pins = < 342 - VF610_PAD_PTA24__USB1_VBUS_EN 0x219c 343 - VF610_PAD_PTA16__USB0_VBUS_EN 0x219c 344 - >; 345 - }; 346 - }; 347 - 348 178 }; 349 179 350 180 gpio1: gpio@40049000 {