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MIPS: DSP: Set all register masks to 0x3ff. 0x2ff was a typo and the value 0x1f of DSP_MASK was refering to an old version of the documentation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
Ralf Baechle
and committed by
07a801de
f12555d2
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-3
include/asm-mips/dsp.h
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include/asm-mips/dsp.h
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#include <asm/mipsregs.h>
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#define DSP_DEFAULT 0x00000000
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#define DSP_MASK 0x1f
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#define __enable_dsp_hazard() \
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do { \
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tsk->thread.dsp.dspr[3] = mflo2(); \
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tsk->thread.dsp.dspr[4] = mfhi3(); \
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tsk->thread.dsp.dspr[5] = mflo3(); \
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tsk->thread.dsp.dspcontrol = rddsp(0x2ff); \
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} while (0)
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#define save_dsp(tsk) \
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mtlo2(tsk->thread.dsp.dspr[3]); \
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mthi3(tsk->thread.dsp.dspr[4]); \
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mtlo3(tsk->thread.dsp.dspr[5]); \
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wrdsp(tsk->thread.dsp.dspcontrol, 0x2ff); \
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} while (0)
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#define restore_dsp(tsk) \
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#include <asm/mipsregs.h>
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#define DSP_DEFAULT 0x00000000
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#define DSP_MASK 0x3ff
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#define __enable_dsp_hazard() \
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do { \
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tsk->thread.dsp.dspr[3] = mflo2(); \
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tsk->thread.dsp.dspr[4] = mfhi3(); \
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tsk->thread.dsp.dspr[5] = mflo3(); \
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tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); \
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} while (0)
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#define save_dsp(tsk) \
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mtlo2(tsk->thread.dsp.dspr[3]); \
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mthi3(tsk->thread.dsp.dspr[4]); \
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mtlo3(tsk->thread.dsp.dspr[5]); \
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wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); \
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} while (0)
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#define restore_dsp(tsk) \