pinctrl: Rename sh-pfc to renesas

The drivers/pinctrl/sh-pfc subdirectory was originally created to group
pin control drivers for various Renesas SuperH and SH-Mobile platforms.
However, the name "sh-pfc" no longer reflects its contents, as the
directory now contains pin control drivers for Renesas SuperH, ARM32,
and ARM64 SoCs.

Hence rename the subdirectory from drivers/pinctrl/sh-pfc to
drivers/pinctrl/renesas, and the related Kconfig symbol from
PINCTRL_SH_PFC to PINCTRL_RENESAS.

Rename the git branch in MAINTAINERS, too, for consistency.

Signed-off-by: Geert Uytterhoeven <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]

MAINTAINERS

···
 M:	Geert Uytterhoeven <[e-mail]>
 L:	[e-mail]
 S:	Supported
-T:	git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc
+T:	git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-pinctrl
 F:	Documentation/devicetree/bindings/pinctrl/renesas,*
-F:	drivers/pinctrl/sh-pfc/
+F:	drivers/pinctrl/renesas/
 
 PIN CONTROLLER - SAMSUNG
 M:	Tomasz Figa <[e-mail]>

drivers/pinctrl/Kconfig

···
 source "drivers/pinctrl/nuvoton/Kconfig"
 source "drivers/pinctrl/pxa/Kconfig"
 source "drivers/pinctrl/qcom/Kconfig"
+source "drivers/pinctrl/renesas/Kconfig"
 source "drivers/pinctrl/samsung/Kconfig"
-source "drivers/pinctrl/sh-pfc/Kconfig"
 source "drivers/pinctrl/spear/Kconfig"
 source "drivers/pinctrl/sprd/Kconfig"
 source "drivers/pinctrl/stm32/Kconfig"

drivers/pinctrl/Makefile

···
 obj-$(CONFIG_ARCH_NPCM7XX)	+= nuvoton/
 obj-$(CONFIG_PINCTRL_PXA)	+= pxa/
 obj-$(CONFIG_ARCH_QCOM)		+= qcom/
+obj-$(CONFIG_PINCTRL_RENESAS)	+= renesas/
 obj-$(CONFIG_PINCTRL_SAMSUNG)	+= samsung/
-obj-$(CONFIG_PINCTRL_SH_PFC)	+= sh-pfc/
 obj-$(CONFIG_PINCTRL_SPEAR)	+= spear/
 obj-y				+= sprd/
 obj-$(CONFIG_PINCTRL_STM32)	+= stm32/

drivers/pinctrl/sh-pfc/Kconfig drivers/pinctrl/renesas/Kconfig

···
 
 menu "Renesas pinctrl drivers"
 
-config PINCTRL_SH_PFC
+config PINCTRL_RENESAS
 	bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH)
 	default y if ARCH_RENESAS || SUPERH
 	select PINMUX

drivers/pinctrl/sh-pfc/Makefile drivers/pinctrl/renesas/Makefile

···
 # SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_PINCTRL_SH_PFC)	+= core.o pinctrl.o
+obj-$(CONFIG_PINCTRL_RENESAS)		+= core.o pinctrl.o
 obj-$(CONFIG_PINCTRL_SH_PFC_GPIO)	+= gpio.o
-obj-$(CONFIG_PINCTRL_PFC_EMEV2)	+= pfc-emev2.o
+obj-$(CONFIG_PINCTRL_PFC_EMEV2)		+= pfc-emev2.o
 obj-$(CONFIG_PINCTRL_PFC_R8A73A4)	+= pfc-r8a73a4.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7740)	+= pfc-r8a7740.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7742)	+= pfc-r8a7790.o

drivers/pinctrl/sh-pfc/pfc-r8a7796.c drivers/pinctrl/renesas/pfc-r8a77965.c

···
 // SPDX-License-Identifier: GPL-2.0
 /*
- * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
+ * R8A77965 processor support - PFC hardware block.
  *
+ * Copyright (C) 2018 Jacopo Mondi <[e-mail]>
  * Copyright (C) 2016-2019 Renesas Electronics Corp.
  *
- * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+ * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
  *
  * R-Car Gen3 processor support - PFC hardware block.
  *
···
 	PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),		\
 	PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS),	\
 	PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS),	\
+	PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS),	\
 	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
 	PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS),		\
 	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),		\
···
 #define IP0_7_4		FM(AVB_MAGIC)		F_(0, 0)	FM(MSIOF2_SS1_C)	FM(SCK4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	FM(FSCLKST2_N_A) F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	F_(0, 0)		FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	F_(0, 0)		FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)F_(0, 0)		F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_23_20	FM(PWM1_A)		F_(0, 0)	F_(0, 0)		FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_27_24	FM(PWM2_A)		F_(0, 0)	F_(0, 0)		FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
···
 #define IP9_15_12	FM(SD2_DAT1)		F_(0, 0)	FM(NFDATA11)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_19_16	FM(SD2_DAT2)		F_(0, 0)	FM(NFDATA12)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_23_20	FM(SD2_DAT3)		F_(0, 0)	FM(NFDATA13)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_27_24	FM(SD2_DS)		F_(0, 0)	FM(NFALE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_27_24	FM(SD2_DS)		F_(0, 0)	FM(NFALE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_31_28	FM(SD3_CLK)		F_(0, 0)	FM(NFWE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP10_3_0	FM(SD3_CMD)		F_(0, 0)	FM(NFRE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP10_7_4	FM(SD3_DAT0)		F_(0, 0)	FM(NFDATA0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
···
 #define IP15_31_28	FM(SSI_SDATA4)		FM(HSCK2_A)	FM(MSIOF1_RXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)	FM(RIF0_D0_A)	FM(RIF2_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP16_3_0	FM(SSI_SCK6)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP16_7_4	FM(SSI_WS6)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP16_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP16_15_12	FM(SSI_SCK78)		FM(HRX2_B)	FM(MSIOF1_SCK_C)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_A)	FM(STP_ISCLK_1_A)	FM(RIF1_CLK_A)	FM(RIF3_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP16_19_16	FM(SSI_WS78)		FM(HTX2_B)	FM(MSIOF1_SYNC_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_A)	FM(STP_ISD_1_A)		FM(RIF1_SYNC_A)	FM(RIF3_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP16_23_20	FM(SSI_SDATA7)		FM(HCTS2_N_B)	FM(MSIOF1_RXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_A)	FM(STP_ISEN_1_A)	FM(RIF1_D0_A)	FM(RIF3_D0_A)		F_(0, 0)	FM(TCLK2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
···
 	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 	FM(PRESETOUT) \
-	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
+	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
 	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 
 #define PINMUX_PHYS \
···
 	PINMUX_IPSR_GPSR(IP0_15_12,	AVB_LINK),
 	PINMUX_IPSR_MSEL(IP0_15_12,	MSIOF2_SCK_C,		SEL_MSIOF2_2),
 	PINMUX_IPSR_MSEL(IP0_15_12,	TX4_A,			SEL_SCIF4_0),
+	PINMUX_IPSR_GPSR(IP0_19_16,	FSCLKST2_N_A),
 
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
+	PINMUX_IPSR_PHYS_MSEL(IP0_19_16,	AVB_AVTP_MATCH_A,	I2C_SEL_5_0, SEL_ETHERAVB_0),
+	PINMUX_IPSR_PHYS_MSEL(IP0_19_16,	MSIOF2_RXD_C,	I2C_SEL_5_0, SEL_MSIOF2_2),
+	PINMUX_IPSR_PHYS_MSEL(IP0_19_16,	CTS4_N_A,	I2C_SEL_5_0, SEL_SCIF4_0),
 	PINMUX_IPSR_PHYS(IP0_19_16,	SCL5,			I2C_SEL_5_1),
 
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
+	PINMUX_IPSR_PHYS_MSEL(IP0_23_20,	AVB_AVTP_CAPTURE_A,	I2C_SEL_5_0, SEL_ETHERAVB_0),
+	PINMUX_IPSR_PHYS_MSEL(IP0_23_20,	MSIOF2_TXD_C,		I2C_SEL_5_0, SEL_MSIOF2_2),
+	PINMUX_IPSR_PHYS_MSEL(IP0_23_20,	RTS4_N_A,		I2C_SEL_5_0, SEL_SCIF4_0),
 	PINMUX_IPSR_PHYS(IP0_23_20,	SDA5,			I2C_SEL_5_1),
 
 	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
···
 	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
 	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
 	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
+	PINMUX_IPSR_GPSR(IP1_15_12,	FSCLKST2_N_B),
 	PINMUX_IPSR_MSEL(IP1_15_12,	MSIOF3_TXD_E,		SEL_MSIOF3_4),
 
 	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
···
 	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
 	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
 
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,		I2C_SEL_3_0,	SEL_PWM1_0),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,		I2C_SEL_3_0,	SEL_VIN4_1),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
-	PINMUX_IPSR_PHYS(IP1_23_20,	SCL3,			I2C_SEL_3_1),
+	PINMUX_IPSR_PHYS_MSEL(IP1_23_20,	PWM1_A,		I2C_SEL_3_0,	SEL_PWM1_0),
+	PINMUX_IPSR_PHYS_MSEL(IP1_23_20,	HRX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
+	PINMUX_IPSR_PHYS_MSEL(IP1_23_20,	VI4_DATA7_B,	I2C_SEL_3_0,	SEL_VIN4_1),
+	PINMUX_IPSR_PHYS_MSEL(IP1_23_20,	IERX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
+	PINMUX_IPSR_PHYS(IP1_23_20,	SCL3,		I2C_SEL_3_1),
 
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,		I2C_SEL_3_0,	SEL_PWM2_0),
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
-	PINMUX_IPSR_PHYS(IP1_27_24,	SDA3,			I2C_SEL_3_1),
+	PINMUX_IPSR_PHYS_MSEL(IP1_27_24,	PWM2_A,		I2C_SEL_3_0,	SEL_PWM2_0),
+	PINMUX_IPSR_PHYS_MSEL(IP1_27_24,	HTX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
+	PINMUX_IPSR_PHYS_MSEL(IP1_27_24,	IETX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
+	PINMUX_IPSR_PHYS(IP1_27_24,	SDA3,		I2C_SEL_3_1),
 
 	PINMUX_IPSR_GPSR(IP1_31_28,	A0),
 	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT16),
···
 
 	PINMUX_IPSR_GPSR(IP9_27_24,	SD2_DS),
 	PINMUX_IPSR_GPSR(IP9_27_24,	NFALE),
+	PINMUX_IPSR_GPSR(IP9_27_24,	SATA_DEVSLP_B),
 
 	PINMUX_IPSR_GPSR(IP9_31_28,	SD3_CLK),
 	PINMUX_IPSR_GPSR(IP9_31_28,	NFWE_N),
···
 	PINMUX_IPSR_MSEL(IP11_15_12,	SDA2_B,			SEL_I2C2_1),
 
 	PINMUX_IPSR_MSEL(IP11_19_16,	SD1_CD,			I2C_SEL_0_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A,		I2C_SEL_0_0,	SEL_NDF_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
+	PINMUX_IPSR_PHYS_MSEL(IP11_19_16,	NFRB_N_A,	I2C_SEL_0_0, SEL_NDF_0),
+	PINMUX_IPSR_PHYS_MSEL(IP11_19_16,	SIM0_CLK_B,	I2C_SEL_0_0, SEL_SIMCARD_1),
 	PINMUX_IPSR_PHYS(IP11_19_16,	SCL0,			I2C_SEL_0_1),
 
 	PINMUX_IPSR_MSEL(IP11_23_20,	SD1_WP,			I2C_SEL_0_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A,		I2C_SEL_0_0,	SEL_NDF_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
+	PINMUX_IPSR_PHYS_MSEL(IP11_23_20,	NFCE_N_A,	I2C_SEL_0_0, SEL_NDF_0),
+	PINMUX_IPSR_PHYS_MSEL(IP11_23_20,	SIM0_D_B,	I2C_SEL_0_0, SEL_SIMCARD_1),
 	PINMUX_IPSR_PHYS(IP11_23_20,	SDA0,			I2C_SEL_0_1),
 
 	PINMUX_IPSR_GPSR(IP11_27_24,	SCK0),
···
 
 	PINMUX_IPSR_GPSR(IP16_11_8,	SSI_SDATA6),
 	PINMUX_IPSR_MSEL(IP16_11_8,	SIM0_CLK_D,		SEL_SIMCARD_3),
+	PINMUX_IPSR_GPSR(IP16_11_8,	SATA_DEVSLP_A),
 
 	PINMUX_IPSR_GPSR(IP16_15_12,	SSI_SCK78),
 	PINMUX_IPSR_MSEL(IP16_15_12,	HRX2_B,			SEL_HSCIF2_1),
···
 	/* TX, RX */
 	RCAR_GP_PIN(1, 23),	RCAR_GP_PIN(1, 24),
 };
+
 static const unsigned int can0_data_a_mux[] = {
 	CAN0_TX_A_MARK,		CAN0_RX_A_MARK,
 };
+
 static const unsigned int can0_data_b_pins[] = {
 	/* TX, RX */
 	RCAR_GP_PIN(2, 0),	RCAR_GP_PIN(2, 1),
 };
+
 static const unsigned int can0_data_b_mux[] = {
 	CAN0_TX_B_MARK,		CAN0_RX_B_MARK,
 };
+
 static const unsigned int can1_data_pins[] = {
 	/* TX, RX */
 	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 26),
 };
+
 static const unsigned int can1_data_mux[] = {
 	CAN1_TX_MARK,		CAN1_RX_MARK,
 };
···
 	/* CLK */
 	RCAR_GP_PIN(1, 25),
 };
+
 static const unsigned int can_clk_mux[] = {
 	CAN_CLK_MARK,
 };
···
 	/* TX, RX */
 	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
 };
+
 static const unsigned int canfd0_data_a_mux[] = {
 	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
 };
+
 static const unsigned int canfd0_data_b_pins[] = {
 	/* TX, RX */
 	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
 };
+
 static const unsigned int canfd0_data_b_mux[] = {
 	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
 };
+
 static const unsigned int canfd1_data_pins[] = {
 	/* TX, RX */
 	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
 };
+
 static const unsigned int canfd1_data_mux[] = {
 	CANFD1_TX_MARK,         CANFD1_RX_MARK,
 };
···
 	/* CLK, SYNC */
 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
 };
+
 static const unsigned int drif0_ctrl_a_mux[] = {
 	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
 };
+
 static const unsigned int drif0_data0_a_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(6, 10),
 };
+
 static const unsigned int drif0_data0_a_mux[] = {
 	RIF0_D0_A_MARK,
 };
+
 static const unsigned int drif0_data1_a_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(6, 7),
 };
+
 static const unsigned int drif0_data1_a_mux[] = {
 	RIF0_D1_A_MARK,
 };
+
 static const unsigned int drif0_ctrl_b_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
 };
+
 static const unsigned int drif0_ctrl_b_mux[] = {
 	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
 };
+
 static const unsigned int drif0_data0_b_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(5, 1),
 };
+
 static const unsigned int drif0_data0_b_mux[] = {
 	RIF0_D0_B_MARK,
 };
+
 static const unsigned int drif0_data1_b_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(5, 2),
 };
+
 static const unsigned int drif0_data1_b_mux[] = {
 	RIF0_D1_B_MARK,
 };
+
 static const unsigned int drif0_ctrl_c_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
 };
+
 static const unsigned int drif0_ctrl_c_mux[] = {
 	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
 };
+
 static const unsigned int drif0_data0_c_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(5, 13),
 };
+
 static const unsigned int drif0_data0_c_mux[] = {
 	RIF0_D0_C_MARK,
 };
+
 static const unsigned int drif0_data1_c_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(5, 14),
 };
+
 static const unsigned int drif0_data1_c_mux[] = {
 	RIF0_D1_C_MARK,
 };
+
 /* - DRIF1 --------------------------------------------------------------- */
 static const unsigned int drif1_ctrl_a_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
 };
+
 static const unsigned int drif1_ctrl_a_mux[] = {
 	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
 };
+
 static const unsigned int drif1_data0_a_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(6, 19),
 };
+
 static const unsigned int drif1_data0_a_mux[] = {
 	RIF1_D0_A_MARK,
 };
+
 static const unsigned int drif1_data1_a_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(6, 20),
 };
+
 static const unsigned int drif1_data1_a_mux[] = {
 	RIF1_D1_A_MARK,
 };
+
 static const unsigned int drif1_ctrl_b_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
 };
+
 static const unsigned int drif1_ctrl_b_mux[] = {
 	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
 };
+
 static const unsigned int drif1_data0_b_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(5, 7),
 };
+
 static const unsigned int drif1_data0_b_mux[] = {
 	RIF1_D0_B_MARK,
 };
+
 static const unsigned int drif1_data1_b_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(5, 8),
 };
+
 static const unsigned int drif1_data1_b_mux[] = {
 	RIF1_D1_B_MARK,
 };
+
 static const unsigned int drif1_ctrl_c_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
 };
+
 static const unsigned int drif1_ctrl_c_mux[] = {
 	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
 };
+
 static const unsigned int drif1_data0_c_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(5, 6),
 };
+
 static const unsigned int drif1_data0_c_mux[] = {
 	RIF1_D0_C_MARK,
 };
+
 static const unsigned int drif1_data1_c_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(5, 10),
 };
+
 static const unsigned int drif1_data1_c_mux[] = {
 	RIF1_D1_C_MARK,
 };
+
 /* - DRIF2 --------------------------------------------------------------- */
 static const unsigned int drif2_ctrl_a_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
 };
+
 static const unsigned int drif2_ctrl_a_mux[] = {
 	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
 };
+
 static const unsigned int drif2_data0_a_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(6, 7),
 };
+
 static const unsigned int drif2_data0_a_mux[] = {
 	RIF2_D0_A_MARK,
 };
+
 static const unsigned int drif2_data1_a_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(6, 10),
 };
+
 static const unsigned int drif2_data1_a_mux[] = {
 	RIF2_D1_A_MARK,
 };
+
 static const unsigned int drif2_ctrl_b_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
 };
+
 static const unsigned int drif2_ctrl_b_mux[] = {
 	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
 };
+
 static const unsigned int drif2_data0_b_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(6, 30),
 };
+
 static const unsigned int drif2_data0_b_mux[] = {
 	RIF2_D0_B_MARK,
 };
+
 static const unsigned int drif2_data1_b_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(6, 31),
 };
+
 static const unsigned int drif2_data1_b_mux[] = {
 	RIF2_D1_B_MARK,
 };
+
 /* - DRIF3 --------------------------------------------------------------- */
 static const unsigned int drif3_ctrl_a_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
 };
+
 static const unsigned int drif3_ctrl_a_mux[] = {
 	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
 };
+
 static const unsigned int drif3_data0_a_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(6, 19),
 };
+
 static const unsigned int drif3_data0_a_mux[] = {
 	RIF3_D0_A_MARK,
 };
+
 static const unsigned int drif3_data1_a_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(6, 20),
 };
+
 static const unsigned int drif3_data1_a_mux[] = {
 	RIF3_D1_A_MARK,
 };
+
 static const unsigned int drif3_ctrl_b_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
 };
+
 static const unsigned int drif3_ctrl_b_mux[] = {
 	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
 };
+
 static const unsigned int drif3_data0_b_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(6, 28),
 };
+
 static const unsigned int drif3_data0_b_mux[] = {
 	RIF3_D0_B_MARK,
 };
+
 static const unsigned int drif3_data1_b_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(6, 29),
 };
+
 static const unsigned int drif3_data1_b_mux[] = {
 	RIF3_D1_B_MARK,
 };
···
 	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
 	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
 };
+
 static const unsigned int du_rgb666_mux[] = {
 	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
 	DU_DR3_MARK, DU_DR2_MARK,
···
 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
 	DU_DB3_MARK, DU_DB2_MARK,
 };
+
 static const unsigned int du_rgb888_pins[] = {
 	/* R[7:0], G[7:0], B[7:0] */
 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
···
 	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
 	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
 };
+
 static const unsigned int du_rgb888_mux[] = {
 	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
 	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
···
 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
 	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
 };
+
 static const unsigned int du_clk_out_0_pins[] = {
 	/* CLKOUT */
 	RCAR_GP_PIN(1, 27),
 };
+
 static const unsigned int du_clk_out_0_mux[] = {
 	DU_DOTCLKOUT0_MARK
 };
+
 static const unsigned int du_clk_out_1_pins[] = {
 	/* CLKOUT */
 	RCAR_GP_PIN(2, 3),
 };
+
 static const unsigned int du_clk_out_1_mux[] = {
 	DU_DOTCLKOUT1_MARK
 };
+
 static const unsigned int du_sync_pins[] = {
 	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
 };
+
 static const unsigned int du_sync_mux[] = {
 	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
 };
+
 static const unsigned int du_oddf_pins[] = {
 	/* EXDISP/EXODDF/EXCDE */
 	RCAR_GP_PIN(2, 2),
 };
+
 static const unsigned int du_oddf_mux[] = {
 	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
 };
+
 static const unsigned int du_cde_pins[] = {
 	/* CDE */
 	RCAR_GP_PIN(2, 0),
 };
+
 static const unsigned int du_cde_mux[] = {
 	DU_CDE_MARK,
 };
+
 static const unsigned int du_disp_pins[] = {
 	/* DISP */
 	RCAR_GP_PIN(2, 1),
 };
+
 static const unsigned int du_disp_mux[] = {
 	DU_DISP_MARK,
 };
···
 	/* RX, TX */
 	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
 };
+
 static const unsigned int hscif0_data_mux[] = {
 	HRX0_MARK, HTX0_MARK,
 };
+
 static const unsigned int hscif0_clk_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(5, 12),
 };
+
 static const unsigned int hscif0_clk_mux[] = {
 	HSCK0_MARK,
 };
+
 static const unsigned int hscif0_ctrl_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
 };
+
 static const unsigned int hscif0_ctrl_mux[] = {
 	HRTS0_N_MARK, HCTS0_N_MARK,
 };
+
 /* - HSCIF1 ----------------------------------------------------------------- */
 static const unsigned int hscif1_data_a_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
 };
+
 static const unsigned int hscif1_data_a_mux[] = {
 	HRX1_A_MARK, HTX1_A_MARK,
 };
+
 static const unsigned int hscif1_clk_a_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(6, 21),
 };
+
 static const unsigned int hscif1_clk_a_mux[] = {
 	HSCK1_A_MARK,
 };
+
 static const unsigned int hscif1_ctrl_a_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
 };
+
 static const unsigned int hscif1_ctrl_a_mux[] = {
 	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
 };
···
 	/* RX, TX */
 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
 };
+
 static const unsigned int hscif1_data_b_mux[] = {
 	HRX1_B_MARK, HTX1_B_MARK,
 };
+
 static const unsigned int hscif1_clk_b_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(5, 0),
 };
+
 static const unsigned int hscif1_clk_b_mux[] = {
 	HSCK1_B_MARK,
 };
+
 static const unsigned int hscif1_ctrl_b_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
 };
+
 static const unsigned int hscif1_ctrl_b_mux[] = {
 	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
 };
+
 /* - HSCIF2 ----------------------------------------------------------------- */
 static const unsigned int hscif2_data_a_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
 };
+
 static const unsigned int hscif2_data_a_mux[] = {
 	HRX2_A_MARK, HTX2_A_MARK,
 };
+
 static const unsigned int hscif2_clk_a_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(6, 10),
 };
+
 static const unsigned int hscif2_clk_a_mux[] = {
 	HSCK2_A_MARK,
 };
+
 static const unsigned int hscif2_ctrl_a_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
 };
+
 static const unsigned int hscif2_ctrl_a_mux[] = {
 	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
 };
···
 	/* RX, TX */
 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
 };
+
 static const unsigned int hscif2_data_b_mux[] = {
 	HRX2_B_MARK, HTX2_B_MARK,
 };
+
 static const unsigned int hscif2_clk_b_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(6, 21),
 };
+
 static const unsigned int hscif2_clk_b_mux[] = {
 	HSCK2_B_MARK,
 };
+
 static const unsigned int hscif2_ctrl_b_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
 };
+
 static const unsigned int hscif2_ctrl_b_mux[] = {
 	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
 };
···
 	/* RX, TX */
 	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
 };
+
 static const unsigned int hscif2_data_c_mux[] = {
 	HRX2_C_MARK, HTX2_C_MARK,
 };
+
 static const unsigned int hscif2_clk_c_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(6, 24),
 };
+
 static const unsigned int hscif2_clk_c_mux[] = {
 	HSCK2_C_MARK,
 };
+
 static const unsigned int hscif2_ctrl_c_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
 };
+
 static const unsigned int hscif2_ctrl_c_mux[] = {
 	HRTS2_N_C_MARK, HCTS2_N_C_MARK,
 };
+
 /* - HSCIF3 ----------------------------------------------------------------- */
 static const unsigned int hscif3_data_a_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
 };
+
 static const unsigned int hscif3_data_a_mux[] = {
 	HRX3_A_MARK, HTX3_A_MARK,
 };
+
 static const unsigned int hscif3_clk_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(1, 22),
 };
+
 static const unsigned int hscif3_clk_mux[] = {
 	HSCK3_MARK,
 };
+
 static const unsigned int hscif3_ctrl_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
 };
+
 static const unsigned int hscif3_ctrl_mux[] = {
 	HRTS3_N_MARK, HCTS3_N_MARK,
 };
···
 	/* RX, TX */
 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
 };
+
 static const unsigned int hscif3_data_b_mux[] = {
 	HRX3_B_MARK, HTX3_B_MARK,
 };
+
 static const unsigned int hscif3_data_c_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
 };
+
 static const unsigned int hscif3_data_c_mux[] = {
 	HRX3_C_MARK, HTX3_C_MARK,
 };
+
 static const unsigned int hscif3_data_d_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
 };
+
 static const unsigned int hscif3_data_d_mux[] = {
 	HRX3_D_MARK, HTX3_D_MARK,
 };
+
 /* - HSCIF4 ----------------------------------------------------------------- */
 static const unsigned int hscif4_data_a_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
 };
+
 static const unsigned int hscif4_data_a_mux[] = {
 	HRX4_A_MARK, HTX4_A_MARK,
 };
+
 static const unsigned int hscif4_clk_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(1, 11),
 };
+
 static const unsigned int hscif4_clk_mux[] = {
 	HSCK4_MARK,
 };
+
 static const unsigned int hscif4_ctrl_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
 };
+
 static const unsigned int hscif4_ctrl_mux[] = {
 	HRTS4_N_MARK, HCTS4_N_MARK,
 };
···
 	/* RX, TX */
 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
 };
+
 static const unsigned int hscif4_data_b_mux[] = {
 	HRX4_B_MARK, HTX4_B_MARK,
 };
···
 	/* SDA, SCL */
 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
 };
+
 static const unsigned int i2c1_a_mux[] = {
 	SDA1_A_MARK, SCL1_A_MARK,
 };
+
 static const unsigned int i2c1_b_pins[] = {
 	/* SDA, SCL */
 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
 };
+
 static const unsigned int i2c1_b_mux[] = {
 	SDA1_B_MARK, SCL1_B_MARK,
 };
+
 static const unsigned int i2c2_a_pins[] = {
 	/* SDA, SCL */
 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
 };
+
 static const unsigned int i2c2_a_mux[] = {
 	SDA2_A_MARK, SCL2_A_MARK,
 };
+
 static const unsigned int i2c2_b_pins[] = {
 	/* SDA, SCL */
 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
 };
+
 static const unsigned int i2c2_b_mux[] = {
 	SDA2_B_MARK, SCL2_B_MARK,
 };
···
 	/* SDA, SCL */
 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
 };
+
 static const unsigned int i2c6_a_mux[] = {
 	SDA6_A_MARK, SCL6_A_MARK,
 };
+
 static const unsigned int i2c6_b_pins[] = {
 	/* SDA, SCL */
 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
 };
+
 static const unsigned int i2c6_b_mux[] = {
 	SDA6_B_MARK, SCL6_B_MARK,
 };
+
 static const unsigned int i2c6_c_pins[] = {
 	/* SDA, SCL */
 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
 };
+
 static const unsigned int i2c6_c_mux[] = {
 	SDA6_C_MARK, SCL6_C_MARK,
 };
···
 static const unsigned int msiof3_rxd_d_mux[] = {
 	MSIOF3_RXD_D_MARK,
 };
-
 static const unsigned int msiof3_clk_e_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(2, 3),
···
 	PWM6_B_MARK,
 };
 
+/* - SATA --------------------------------------------------------------------*/
+static const unsigned int sata0_devslp_a_pins[] = {
+	/* DEVSLP */
+	RCAR_GP_PIN(6, 16),
+};
+
+static const unsigned int sata0_devslp_a_mux[] = {
+	SATA_DEVSLP_A_MARK,
+};
+
+static const unsigned int sata0_devslp_b_pins[] = {
+	/* DEVSLP */
+	RCAR_GP_PIN(4, 6),
+};
+
+static const unsigned int sata0_devslp_b_mux[] = {
+	SATA_DEVSLP_B_MARK,
+};
+
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX, TX */
···
 static const unsigned int scif1_ctrl_mux[] = {
 	RTS1_N_MARK, CTS1_N_MARK,
 };
-
 static const unsigned int scif1_data_b_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
···
 static const unsigned int scif5_clk_a_mux[] = {
 	SCK5_A_MARK,
 };
-
 static const unsigned int scif5_data_b_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
···
 static const unsigned int scif5_clk_b_mux[] = {
 	SCK5_B_MARK,
 };
-
 /* - SCIF Clock ------------------------------------------------------------- */
 static const unsigned int scif_clk_a_pins[] = {
 	/* SCIF_CLK */
···
 	/* D0 */
 	RCAR_GP_PIN(3, 2),
 };
+
 static const unsigned int sdhi0_data1_mux[] = {
 	SD0_DAT0_MARK,
 };
+
 static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
 	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
 };
+
 static const unsigned int sdhi0_data4_mux[] = {
 	SD0_DAT0_MARK, SD0_DAT1_MARK,
 	SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
+
 static const unsigned int sdhi0_ctrl_pins[] = {
 	/* CLK, CMD */
 	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
 };
+
 static const unsigned int sdhi0_ctrl_mux[] = {
 	SD0_CLK_MARK, SD0_CMD_MARK,
 };
+
 static const unsigned int sdhi0_cd_pins[] = {
 	/* CD */
 	RCAR_GP_PIN(3, 12),
 };
+
 static const unsigned int sdhi0_cd_mux[] = {
 	SD0_CD_MARK,
 };
+
 static const unsigned int sdhi0_wp_pins[] = {
 	/* WP */
 	RCAR_GP_PIN(3, 13),
 };
+
 static const unsigned int sdhi0_wp_mux[] = {
 	SD0_WP_MARK,
 };
+
 /* - SDHI1 ------------------------------------------------------------------ */
 static const unsigned int sdhi1_data1_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(3, 8),
 };
+
 static const unsigned int sdhi1_data1_mux[] = {
 	SD1_DAT0_MARK,
 };
+
 static const unsigned int sdhi1_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
+
 static const unsigned int sdhi1_data4_mux[] = {
 	SD1_DAT0_MARK, SD1_DAT1_MARK,
 	SD1_DAT2_MARK, SD1_DAT3_MARK,
 };
+
 static const unsigned int sdhi1_ctrl_pins[] = {
 	/* CLK, CMD */
 	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
 };
+
 static const unsigned int sdhi1_ctrl_mux[] = {
 	SD1_CLK_MARK, SD1_CMD_MARK,
 };
+
 static const unsigned int sdhi1_cd_pins[] = {
 	/* CD */
 	RCAR_GP_PIN(3, 14),
 };
+
 static const unsigned int sdhi1_cd_mux[] = {
 	SD1_CD_MARK,
 };
+
 static const unsigned int sdhi1_wp_pins[] = {
 	/* WP */
 	RCAR_GP_PIN(3, 15),
 };
+
 static const unsigned int sdhi1_wp_mux[] = {
 	SD1_WP_MARK,
 };
+
 /* - SDHI2 ------------------------------------------------------------------ */
 static const unsigned int sdhi2_data1_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(4, 2),
 };
+
 static const unsigned int sdhi2_data1_mux[] = {
 	SD2_DAT0_MARK,
 };
+
 static const unsigned int sdhi2_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
 };
+
 static const unsigned int sdhi2_data4_mux[] = {
 	SD2_DAT0_MARK, SD2_DAT1_MARK,
 	SD2_DAT2_MARK, SD2_DAT3_MARK,
 };
+
 static const unsigned int sdhi2_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
···
 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
+
 static const unsigned int sdhi2_data8_mux[] = {
 	SD2_DAT0_MARK, SD2_DAT1_MARK,
 	SD2_DAT2_MARK, SD2_DAT3_MARK,
 	SD2_DAT4_MARK, SD2_DAT5_MARK,
 	SD2_DAT6_MARK, SD2_DAT7_MARK,
 };
+
 static const unsigned int sdhi2_ctrl_pins[] = {
 	/* CLK, CMD */
 	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
 };
+
 static const unsigned int sdhi2_ctrl_mux[] = {
 	SD2_CLK_MARK, SD2_CMD_MARK,
 };
+
 static const unsigned int sdhi2_cd_a_pins[] = {
 	/* CD */
 	RCAR_GP_PIN(4, 13),
 };
+
 static const unsigned int sdhi2_cd_a_mux[] = {
 	SD2_CD_A_MARK,
 };
+
 static const unsigned int sdhi2_cd_b_pins[] = {
 	/* CD */
 	RCAR_GP_PIN(5, 10),
 };
+
 static const unsigned int sdhi2_cd_b_mux[] = {
 	SD2_CD_B_MARK,
 };
+
 static const unsigned int sdhi2_wp_a_pins[] = {
 	/* WP */
 	RCAR_GP_PIN(4, 14),
 };
+
 static const unsigned int sdhi2_wp_a_mux[] = {
 	SD2_WP_A_MARK,
 };
+
 static const unsigned int sdhi2_wp_b_pins[] = {
 	/* WP */
 	RCAR_GP_PIN(5, 11),
 };
+
 static const unsigned int sdhi2_wp_b_mux[] = {
 	SD2_WP_B_MARK,
 };
+
 static const unsigned int sdhi2_ds_pins[] = {
 	/* DS */
 	RCAR_GP_PIN(4, 6),
 };
+
 static const unsigned int sdhi2_ds_mux[] = {
 	SD2_DS_MARK,
 };
+
 /* - SDHI3 ------------------------------------------------------------------ */
 static const unsigned int sdhi3_data1_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(4, 9),
 };
+
 static const unsigned int sdhi3_data1_mux[] = {
 	SD3_DAT0_MARK,
 };
+
 static const unsigned int sdhi3_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
 };
+
 static const unsigned int sdhi3_data4_mux[] = {
 	SD3_DAT0_MARK, SD3_DAT1_MARK,
 	SD3_DAT2_MARK, SD3_DAT3_MARK,
 };
+
 static const unsigned int sdhi3_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
···
 	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
 };
+
 static const unsigned int sdhi3_data8_mux[] = {
 	SD3_DAT0_MARK, SD3_DAT1_MARK,
 	SD3_DAT2_MARK, SD3_DAT3_MARK,
 	SD3_DAT4_MARK, SD3_DAT5_MARK,
 	SD3_DAT6_MARK, SD3_DAT7_MARK,
 };
+
 static const unsigned int sdhi3_ctrl_pins[] = {
 	/* CLK, CMD */
 	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
 };
+
 static const unsigned int sdhi3_ctrl_mux[] = {
 	SD3_CLK_MARK, SD3_CMD_MARK,
 };
+
 static const unsigned int sdhi3_cd_pins[] = {
 	/* CD */
 	RCAR_GP_PIN(4, 15),
 };
+
 static const unsigned int sdhi3_cd_mux[] = {
 	SD3_CD_MARK,
 };
+
 static const unsigned int sdhi3_wp_pins[] = {
 	/* WP */
 	RCAR_GP_PIN(4, 16),
 };
+
 static const unsigned int sdhi3_wp_mux[] = {
 	SD3_WP_MARK,
 };
+
 static const unsigned int sdhi3_ds_pins[] = {
 	/* DS */
 	RCAR_GP_PIN(4, 17),
 };
+
 static const unsigned int sdhi3_ds_mux[] = {
 	SD3_DS_MARK,
 };
···
 	/* TCLK */
 	RCAR_GP_PIN(6, 23),
 };
+
 static const unsigned int tmu_tclk1_a_mux[] = {
 	TCLK1_A_MARK,
 };
+
 static const unsigned int tmu_tclk1_b_pins[] = {
 	/* TCLK */
 	RCAR_GP_PIN(5, 19),
 };
+
 static const unsigned int tmu_tclk1_b_mux[] = {
 	TCLK1_B_MARK,
 };
+
 static const unsigned int tmu_tclk2_a_pins[] = {
 	/* TCLK */
 	RCAR_GP_PIN(6, 19),
 };
+
 static const unsigned int tmu_tclk2_a_mux[] = {
 	TCLK2_A_MARK,
 };
+
 static const unsigned int tmu_tclk2_b_pins[] = {
 	/* TCLK */
 	RCAR_GP_PIN(6, 28),
 };
+
 static const unsigned int tmu_tclk2_b_mux[] = {
 	TCLK2_B_MARK,
 };
···
 	/* PWEN, OVC */
 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
 };
+
 static const unsigned int usb0_mux[] = {
 	USB0_PWEN_MARK, USB0_OVC_MARK,
 };
+
 /* - USB1 ------------------------------------------------------------------- */
 static const unsigned int usb1_pins[] = {
 	/* PWEN, OVC */
 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
 };
+
 static const unsigned int usb1_mux[] = {
 	USB1_PWEN_MARK, USB1_OVC_MARK,
 };
···
 	/* PWEN, OVC */
 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
 };
+
 static const unsigned int usb30_mux[] = {
 	USB30_PWEN_MARK, USB30_OVC_MARK,
 };
···
 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+	RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
+	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
+	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
+	RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
+	RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
 };
+
 static const unsigned int vin4_data18_a_mux[] = {
 	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
 	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
 	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-	VI4_DATA10_MARK, VI4_DATA11_MARK,
-	VI4_DATA12_MARK, VI4_DATA13_MARK,
-	VI4_DATA14_MARK, VI4_DATA15_MARK,
-	VI4_DATA18_MARK, VI4_DATA19_MARK,
-	VI4_DATA20_MARK, VI4_DATA21_MARK,
-	VI4_DATA22_MARK, VI4_DATA23_MARK,
+	VI4_DATA10_MARK,  VI4_DATA11_MARK,
+	VI4_DATA12_MARK,  VI4_DATA13_MARK,
+	VI4_DATA14_MARK,  VI4_DATA15_MARK,
+	VI4_DATA18_MARK,  VI4_DATA19_MARK,
+	VI4_DATA20_MARK,  VI4_DATA21_MARK,
+	VI4_DATA22_MARK,  VI4_DATA23_MARK,
 };
+
+static const union vin_data vin4_data_a_pins = {
+	.data24 = {
+		RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 9),
+		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+		RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 1),
+		RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
+		RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
+		RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
+		RCAR_GP_PIN(0, 0),  RCAR_GP_PIN(0, 1),
+		RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
+		RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
+		RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
+	},
+};
+
+static const union vin_data vin4_data_a_mux = {
+	.data24 = {
+		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+		VI4_DATA8_MARK,   VI4_DATA9_MARK,
+		VI4_DATA10_MARK,  VI4_DATA11_MARK,
+		VI4_DATA12_MARK,  VI4_DATA13_MARK,
+		VI4_DATA14_MARK,  VI4_DATA15_MARK,
+		VI4_DATA16_MARK,  VI4_DATA17_MARK,
+		VI4_DATA18_MARK,  VI4_DATA19_MARK,
+		VI4_DATA20_MARK,  VI4_DATA21_MARK,
+		VI4_DATA22_MARK,  VI4_DATA23_MARK,
+	},
+};
+
 static const unsigned int vin4_data18_b_pins[] = {
 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
···
 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 };
+
 static const unsigned int vin4_data18_b_mux[] = {
 	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
 	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
 	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-	VI4_DATA10_MARK, VI4_DATA11_MARK,
-	VI4_DATA12_MARK, VI4_DATA13_MARK,
-	VI4_DATA14_MARK, VI4_DATA15_MARK,
-	VI4_DATA18_MARK, VI4_DATA19_MARK,
-	VI4_DATA20_MARK, VI4_DATA21_MARK,
-	VI4_DATA22_MARK, VI4_DATA23_MARK,
+	VI4_DATA10_MARK,  VI4_DATA11_MARK,
+	VI4_DATA12_MARK,  VI4_DATA13_MARK,
+	VI4_DATA14_MARK,  VI4_DATA15_MARK,
+	VI4_DATA18_MARK,  VI4_DATA19_MARK,
+	VI4_DATA20_MARK,  VI4_DATA21_MARK,
+	VI4_DATA22_MARK,  VI4_DATA23_MARK,
 };
-static const union vin_data vin4_data_a_pins = {
-	.data24 = {
-		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-	},
-};
-static const union vin_data vin4_data_a_mux = {
-	.data24 = {
-		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-		VI4_DATA8_MARK,  VI4_DATA9_MARK,
-		VI4_DATA10_MARK, VI4_DATA11_MARK,
-		VI4_DATA12_MARK, VI4_DATA13_MARK,
-		VI4_DATA14_MARK, VI4_DATA15_MARK,
-		VI4_DATA16_MARK, VI4_DATA17_MARK,
-		VI4_DATA18_MARK, VI4_DATA19_MARK,
-		VI4_DATA20_MARK, VI4_DATA21_MARK,
-		VI4_DATA22_MARK, VI4_DATA23_MARK,
-	},
-};
+
 static const union vin_data vin4_data_b_pins = {
 	.data24 = {
 		RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
···
 		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 	},
 };
+
 static const union vin_data vin4_data_b_mux = {
 	.data24 = {
 		VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
 		VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
 		VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
 		VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-		VI4_DATA8_MARK,  VI4_DATA9_MARK,
-		VI4_DATA10_MARK, VI4_DATA11_MARK,
-		VI4_DATA12_MARK, VI4_DATA13_MARK,
-		VI4_DATA14_MARK, VI4_DATA15_MARK,
-		VI4_DATA16_MARK, VI4_DATA17_MARK,
-		VI4_DATA18_MARK, VI4_DATA19_MARK,
-		VI4_DATA20_MARK, VI4_DATA21_MARK,
-		VI4_DATA22_MARK, VI4_DATA23_MARK,
+		VI4_DATA8_MARK,   VI4_DATA9_MARK,
+		VI4_DATA10_MARK,  VI4_DATA11_MARK,
+		VI4_DATA12_MARK,  VI4_DATA13_MARK,
+		VI4_DATA14_MARK,  VI4_DATA15_MARK,
+		VI4_DATA16_MARK,  VI4_DATA17_MARK,
+		VI4_DATA18_MARK,  VI4_DATA19_MARK,
+		VI4_DATA20_MARK,  VI4_DATA21_MARK,
+		VI4_DATA22_MARK,  VI4_DATA23_MARK,
 	},
 };
+
 static const unsigned int vin4_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
+	/* VSYNC_N, HSYNC_N */
+	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
 };
+
 static const unsigned int vin4_sync_mux[] = {
 	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
 };
+
 static const unsigned int vin4_field_pins[] = {
-	/* FIELD */
 	RCAR_GP_PIN(1, 16),
 };
+
 static const unsigned int vin4_field_mux[] = {
 	VI4_FIELD_MARK,
 };
+
 static const unsigned int vin4_clkenb_pins[] = {
-	/* CLKENB */
 	RCAR_GP_PIN(1, 19),
 };
+
 static const unsigned int vin4_clkenb_mux[] = {
 	VI4_CLKENB_MARK,
 };
+
 static const unsigned int vin4_clk_pins[] = {
-	/* CLK */
 	RCAR_GP_PIN(1, 27),
 };
+
 static const unsigned int vin4_clk_mux[] = {
 	VI4_CLK_MARK,
 };
···
 		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
 		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+		RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
+		RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
 	},
 };
+
 static const union vin_data16 vin5_data_mux = {
 	.data16 = {
 		VI5_DATA0_MARK, VI5_DATA1_MARK,
···
 		VI5_DATA14_MARK, VI5_DATA15_MARK,
 	},
 };
+
 static const unsigned int vin5_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
+	/* VSYNC_N, HSYNC_N */
+	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
 };
+
 static const unsigned int vin5_sync_mux[] = {
 	VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
 };
+
 static const unsigned int vin5_field_pins[] = {
 	RCAR_GP_PIN(1, 11),
 };
+
 static const unsigned int vin5_field_mux[] = {
-	/* FIELD */
 	VI5_FIELD_MARK,
 };
+
 static const unsigned int vin5_clkenb_pins[] = {
 	RCAR_GP_PIN(1, 20),
 };
+
 static const unsigned int vin5_clkenb_mux[] = {
-	/* CLKENB */
 	VI5_CLKENB_MARK,
 };
+
 static const unsigned int vin5_clk_pins[] = {
 	RCAR_GP_PIN(1, 21),
 };
+
 static const unsigned int vin5_clk_mux[] = {
-	/* CLK */
 	VI5_CLK_MARK,
 };
 
 static const struct {
-	struct sh_pfc_pin_group common[316];
+	struct sh_pfc_pin_group common[318];
 	struct sh_pfc_pin_group automotive[30];
 } pinmux_groups = {
 	.common = {
···
 		SH_PFC_PIN_GROUP(avb_link),
 		SH_PFC_PIN_GROUP(avb_magic),
 		SH_PFC_PIN_GROUP(avb_phy_int),
-		SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
+		SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),	/* Deprecated */
 		SH_PFC_PIN_GROUP(avb_mdio),
 		SH_PFC_PIN_GROUP(avb_mii),
 		SH_PFC_PIN_GROUP(avb_avtp_pps),
···
 		SH_PFC_PIN_GROUP(pwm5_b),
 		SH_PFC_PIN_GROUP(pwm6_a),
 		SH_PFC_PIN_GROUP(pwm6_b),
+		SH_PFC_PIN_GROUP(sata0_devslp_a),
+		SH_PFC_PIN_GROUP(sata0_devslp_b),
 		SH_PFC_PIN_GROUP(scif0_data),
 		SH_PFC_PIN_GROUP(scif0_clk),
 		SH_PFC_PIN_GROUP(scif0_ctrl),
···
 	"pwm6_b",
 };
 
+static const char * const sata0_groups[] = {
+	"sata0_devslp_a",
+	"sata0_devslp_b",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
···
 	"scif1_ctrl",
 	"scif1_data_b",
 };
-
 static const char * const scif2_groups[] = {
 	"scif2_data_a",
 	"scif2_clk",
···
 };
 
 static const struct {
-	struct sh_pfc_function common[50];
+	struct sh_pfc_function common[51];
 	struct sh_pfc_function automotive[4];
 } pinmux_functions = {
 	.common = {
···
 		SH_PFC_FUNCTION(pwm4),
 		SH_PFC_FUNCTION(pwm5),
 		SH_PFC_FUNCTION(pwm6),
+		SH_PFC_FUNCTION(sata0),
 		SH_PFC_FUNCTION(scif0),
 		SH_PFC_FUNCTION(scif1),
 		SH_PFC_FUNCTION(scif2),
···
 		{ PIN_DU_DOTCLKIN1,    0, 2 },	/* DU_DOTCLKIN1 */
 	} },
 	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
-		{ PIN_DU_DOTCLKIN2,   28, 2 },	/* DU_DOTCLKIN2 */
+		{ PIN_DU_DOTCLKIN3,   24, 2 },	/* DU_DOTCLKIN3 */
 		{ PIN_FSCLKST,        20, 2 },	/* FSCLKST */
 		{ PIN_TMS,             4, 2 },	/* TMS */
 	} },
···
 	{ /* sentinel */ },
 };
 
-static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
 {
 	int bit = -EINVAL;
 
···
 		[31] = PIN_DU_DOTCLKIN1,	/* DU_DOTCLKIN1 */
 	} },
 	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
-		[ 0] = PIN_DU_DOTCLKIN2,	/* DU_DOTCLKIN2 */
-		[ 1] = SH_PFC_PIN_NONE,
+		[ 0] = SH_PFC_PIN_NONE,
+		[ 1] = PIN_DU_DOTCLKIN3,	/* DU_DOTCLKIN3 */
 		[ 2] = PIN_FSCLKST,		/* FSCLKST */
 		[ 3] = PIN_EXTALR,		/* EXTALR*/
 		[ 4] = PIN_TRST_N,		/* TRST# */
···
 	{ /* sentinel */ },
 };
 
-static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
+static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
 					    unsigned int pin)
 {
 	const struct pinmux_bias_reg *reg;
···
 		return PIN_CONFIG_BIAS_PULL_DOWN;
 }
 
-static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
 				   unsigned int bias)
 {
 	const struct pinmux_bias_reg *reg;
···
 	sh_pfc_write(pfc, reg->puen, enable);
 }
 
-static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
-	.pin_to_pocctrl = r8a7796_pin_to_pocctrl,
-	.get_bias = r8a7796_pinmux_get_bias,
-	.set_bias = r8a7796_pinmux_set_bias,
+static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
+	.pin_to_pocctrl = r8a77965_pin_to_pocctrl,
+	.get_bias = r8a77965_pinmux_get_bias,
+	.set_bias = r8a77965_pinmux_set_bias,
 };
 
-#ifdef CONFIG_PINCTRL_PFC_R8A774A1
-const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
-	.name = "r8a774a1_pfc",
-	.ops = &r8a7796_pinmux_ops,
+#ifdef CONFIG_PINCTRL_PFC_R8A774B1
+const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
+	.name = "r8a774b1_pfc",
+	.ops = &r8a77965_pinmux_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
···
 };
 #endif
 
-#ifdef CONFIG_PINCTRL_PFC_R8A77960
-const struct sh_pfc_soc_info r8a77960_pinmux_info = {
-	.name = "r8a77960_pfc",
-	.ops = &r8a7796_pinmux_ops,
-	.unlock_reg = 0xe6060000, /* PMMR */
-
-	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
-	.pins = pinmux_pins,
-	.nr_pins = ARRAY_SIZE(pinmux_pins),
-	.groups = pinmux_groups.common,
-	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
-		ARRAY_SIZE(pinmux_groups.automotive),
-	.functions = pinmux_functions.common,
-	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
-		ARRAY_SIZE(pinmux_functions.automotive),
-
-	.cfg_regs = pinmux_config_regs,
-	.drive_regs = pinmux_drive_regs,
-	.bias_regs = pinmux_bias_regs,
-	.ioctrl_regs = pinmux_ioctrl_regs,
-
-	.pinmux_data = pinmux_data,
-	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_PFC_R8A77961
-const struct sh_pfc_soc_info r8a77961_pinmux_info = {
-	.name = "r8a77961_pfc",
-	.ops = &r8a7796_pinmux_ops,
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
+const struct sh_pfc_soc_info r8a77965_pinmux_info = {
+	.name = "r8a77965_pfc",
+	.ops = &r8a77965_pinmux_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

drivers/pinctrl/sh-pfc/pfc-r8a77965.c drivers/pinctrl/renesas/pfc-r8a7796.c

···
 // SPDX-License-Identifier: GPL-2.0
 /*
- * R8A77965 processor support - PFC hardware block.
+ * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
  *
- * Copyright (C) 2018 Jacopo Mondi <[e-mail]>
  * Copyright (C) 2016-2019 Renesas Electronics Corp.
  *
- * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+ * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
  *
  * R-Car Gen3 processor support - PFC hardware block.
  *
···
 	PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),		\
 	PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS),	\
 	PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS),	\
-	PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS),	\
+	PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS),	\
 	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
 	PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS),		\
 	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),		\
···
 #define IP0_7_4		FM(AVB_MAGIC)		F_(0, 0)	FM(MSIOF2_SS1_C)	FM(SCK4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	FM(FSCLKST2_N_A) F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	F_(0, 0)		FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	F_(0, 0)		FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)F_(0, 0)		F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_23_20	FM(PWM1_A)		F_(0, 0)	F_(0, 0)		FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_27_24	FM(PWM2_A)		F_(0, 0)	F_(0, 0)		FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
···
 #define IP9_15_12	FM(SD2_DAT1)		F_(0, 0)	FM(NFDATA11)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_19_16	FM(SD2_DAT2)		F_(0, 0)	FM(NFDATA12)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_23_20	FM(SD2_DAT3)		F_(0, 0)	FM(NFDATA13)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_27_24	FM(SD2_DS)		F_(0, 0)	FM(NFALE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_27_24	FM(SD2_DS)		F_(0, 0)	FM(NFALE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_31_28	FM(SD3_CLK)		F_(0, 0)	FM(NFWE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP10_3_0	FM(SD3_CMD)		F_(0, 0)	FM(NFRE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP10_7_4	FM(SD3_DAT0)		F_(0, 0)	FM(NFDATA0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
···
 #define IP15_31_28	FM(SSI_SDATA4)		FM(HSCK2_A)	FM(MSIOF1_RXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)	FM(RIF0_D0_A)	FM(RIF2_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP16_3_0	FM(SSI_SCK6)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP16_7_4	FM(SSI_WS6)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP16_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP16_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP16_15_12	FM(SSI_SCK78)		FM(HRX2_B)	FM(MSIOF1_SCK_C)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_A)	FM(STP_ISCLK_1_A)	FM(RIF1_CLK_A)	FM(RIF3_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP16_19_16	FM(SSI_WS78)		FM(HTX2_B)	FM(MSIOF1_SYNC_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_A)	FM(STP_ISD_1_A)		FM(RIF1_SYNC_A)	FM(RIF3_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP16_23_20	FM(SSI_SDATA7)		FM(HCTS2_N_B)	FM(MSIOF1_RXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_A)	FM(STP_ISEN_1_A)	FM(RIF1_D0_A)	FM(RIF3_D0_A)		F_(0, 0)	FM(TCLK2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
···
 	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 	FM(PRESETOUT) \
-	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
+	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
 	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 
 #define PINMUX_PHYS \
···
 	PINMUX_IPSR_GPSR(IP0_15_12,	AVB_LINK),
 	PINMUX_IPSR_MSEL(IP0_15_12,	MSIOF2_SCK_C,		SEL_MSIOF2_2),
 	PINMUX_IPSR_MSEL(IP0_15_12,	TX4_A,			SEL_SCIF4_0),
-	PINMUX_IPSR_GPSR(IP0_19_16,	FSCLKST2_N_A),
 
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16,	AVB_AVTP_MATCH_A,	I2C_SEL_5_0, SEL_ETHERAVB_0),
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16,	MSIOF2_RXD_C,	I2C_SEL_5_0, SEL_MSIOF2_2),
-	PINMUX_IPSR_PHYS_MSEL(IP0_19_16,	CTS4_N_A,	I2C_SEL_5_0, SEL_SCIF4_0),
+	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
+	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
+	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
 	PINMUX_IPSR_PHYS(IP0_19_16,	SCL5,			I2C_SEL_5_1),
 
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20,	AVB_AVTP_CAPTURE_A,	I2C_SEL_5_0, SEL_ETHERAVB_0),
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20,	MSIOF2_TXD_C,		I2C_SEL_5_0, SEL_MSIOF2_2),
-	PINMUX_IPSR_PHYS_MSEL(IP0_23_20,	RTS4_N_A,		I2C_SEL_5_0, SEL_SCIF4_0),
+	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
+	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
+	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
 	PINMUX_IPSR_PHYS(IP0_23_20,	SDA5,			I2C_SEL_5_1),
 
 	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
···
 	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
 	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
 	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
-	PINMUX_IPSR_GPSR(IP1_15_12,	FSCLKST2_N_B),
 	PINMUX_IPSR_MSEL(IP1_15_12,	MSIOF3_TXD_E,		SEL_MSIOF3_4),
 
 	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
···
 	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
 	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
 
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20,	PWM1_A,		I2C_SEL_3_0,	SEL_PWM1_0),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20,	HRX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20,	VI4_DATA7_B,	I2C_SEL_3_0,	SEL_VIN4_1),
-	PINMUX_IPSR_PHYS_MSEL(IP1_23_20,	IERX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
-	PINMUX_IPSR_PHYS(IP1_23_20,	SCL3,		I2C_SEL_3_1),
+	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,		I2C_SEL_3_0,	SEL_PWM1_0),
+	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
+	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,		I2C_SEL_3_0,	SEL_VIN4_1),
+	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
+	PINMUX_IPSR_PHYS(IP1_23_20,	SCL3,			I2C_SEL_3_1),
 
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24,	PWM2_A,		I2C_SEL_3_0,	SEL_PWM2_0),
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24,	HTX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
-	PINMUX_IPSR_PHYS_MSEL(IP1_27_24,	IETX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
-	PINMUX_IPSR_PHYS(IP1_27_24,	SDA3,		I2C_SEL_3_1),
+	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,		I2C_SEL_3_0,	SEL_PWM2_0),
+	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
+	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
+	PINMUX_IPSR_PHYS(IP1_27_24,	SDA3,			I2C_SEL_3_1),
 
 	PINMUX_IPSR_GPSR(IP1_31_28,	A0),
 	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT16),
···
 
 	PINMUX_IPSR_GPSR(IP9_27_24,	SD2_DS),
 	PINMUX_IPSR_GPSR(IP9_27_24,	NFALE),
-	PINMUX_IPSR_GPSR(IP9_27_24,	SATA_DEVSLP_B),
 
 	PINMUX_IPSR_GPSR(IP9_31_28,	SD3_CLK),
 	PINMUX_IPSR_GPSR(IP9_31_28,	NFWE_N),
···
 	PINMUX_IPSR_MSEL(IP11_15_12,	SDA2_B,			SEL_I2C2_1),
 
 	PINMUX_IPSR_MSEL(IP11_19_16,	SD1_CD,			I2C_SEL_0_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_19_16,	NFRB_N_A,	I2C_SEL_0_0, SEL_NDF_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_19_16,	SIM0_CLK_B,	I2C_SEL_0_0, SEL_SIMCARD_1),
+	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A,		I2C_SEL_0_0,	SEL_NDF_0),
+	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
 	PINMUX_IPSR_PHYS(IP11_19_16,	SCL0,			I2C_SEL_0_1),
 
 	PINMUX_IPSR_MSEL(IP11_23_20,	SD1_WP,			I2C_SEL_0_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_23_20,	NFCE_N_A,	I2C_SEL_0_0, SEL_NDF_0),
-	PINMUX_IPSR_PHYS_MSEL(IP11_23_20,	SIM0_D_B,	I2C_SEL_0_0, SEL_SIMCARD_1),
+	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A,		I2C_SEL_0_0,	SEL_NDF_0),
+	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
 	PINMUX_IPSR_PHYS(IP11_23_20,	SDA0,			I2C_SEL_0_1),
 
 	PINMUX_IPSR_GPSR(IP11_27_24,	SCK0),
···
 
 	PINMUX_IPSR_GPSR(IP16_11_8,	SSI_SDATA6),
 	PINMUX_IPSR_MSEL(IP16_11_8,	SIM0_CLK_D,		SEL_SIMCARD_3),
-	PINMUX_IPSR_GPSR(IP16_11_8,	SATA_DEVSLP_A),
 
 	PINMUX_IPSR_GPSR(IP16_15_12,	SSI_SCK78),
 	PINMUX_IPSR_MSEL(IP16_15_12,	HRX2_B,			SEL_HSCIF2_1),
···
 	/* TX, RX */
 	RCAR_GP_PIN(1, 23),	RCAR_GP_PIN(1, 24),
 };
-
 static const unsigned int can0_data_a_mux[] = {
 	CAN0_TX_A_MARK,		CAN0_RX_A_MARK,
 };
-
 static const unsigned int can0_data_b_pins[] = {
 	/* TX, RX */
 	RCAR_GP_PIN(2, 0),	RCAR_GP_PIN(2, 1),
 };
-
 static const unsigned int can0_data_b_mux[] = {
 	CAN0_TX_B_MARK,		CAN0_RX_B_MARK,
 };
-
 static const unsigned int can1_data_pins[] = {
 	/* TX, RX */
 	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 26),
 };
-
 static const unsigned int can1_data_mux[] = {
 	CAN1_TX_MARK,		CAN1_RX_MARK,
 };
···
 	/* CLK */
 	RCAR_GP_PIN(1, 25),
 };
-
 static const unsigned int can_clk_mux[] = {
 	CAN_CLK_MARK,
 };
···
 	/* TX, RX */
 	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
 };
-
 static const unsigned int canfd0_data_a_mux[] = {
 	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
 };
-
 static const unsigned int canfd0_data_b_pins[] = {
 	/* TX, RX */
 	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
 };
-
 static const unsigned int canfd0_data_b_mux[] = {
 	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
 };
-
 static const unsigned int canfd1_data_pins[] = {
 	/* TX, RX */
 	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
 };
-
 static const unsigned int canfd1_data_mux[] = {
 	CANFD1_TX_MARK,         CANFD1_RX_MARK,
 };
···
 	/* CLK, SYNC */
 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
 };
-
 static const unsigned int drif0_ctrl_a_mux[] = {
 	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
 };
-
 static const unsigned int drif0_data0_a_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(6, 10),
 };
-
 static const unsigned int drif0_data0_a_mux[] = {
 	RIF0_D0_A_MARK,
 };
-
 static const unsigned int drif0_data1_a_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(6, 7),
 };
-
 static const unsigned int drif0_data1_a_mux[] = {
 	RIF0_D1_A_MARK,
 };
-
 static const unsigned int drif0_ctrl_b_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
 };
-
 static const unsigned int drif0_ctrl_b_mux[] = {
 	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
 };
-
 static const unsigned int drif0_data0_b_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(5, 1),
 };
-
 static const unsigned int drif0_data0_b_mux[] = {
 	RIF0_D0_B_MARK,
 };
-
 static const unsigned int drif0_data1_b_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(5, 2),
 };
-
 static const unsigned int drif0_data1_b_mux[] = {
 	RIF0_D1_B_MARK,
 };
-
 static const unsigned int drif0_ctrl_c_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
 };
-
 static const unsigned int drif0_ctrl_c_mux[] = {
 	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
 };
-
 static const unsigned int drif0_data0_c_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(5, 13),
 };
-
 static const unsigned int drif0_data0_c_mux[] = {
 	RIF0_D0_C_MARK,
 };
-
 static const unsigned int drif0_data1_c_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(5, 14),
 };
-
 static const unsigned int drif0_data1_c_mux[] = {
 	RIF0_D1_C_MARK,
 };
-
 /* - DRIF1 --------------------------------------------------------------- */
 static const unsigned int drif1_ctrl_a_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
 };
-
 static const unsigned int drif1_ctrl_a_mux[] = {
 	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
 };
-
 static const unsigned int drif1_data0_a_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(6, 19),
 };
-
 static const unsigned int drif1_data0_a_mux[] = {
 	RIF1_D0_A_MARK,
 };
-
 static const unsigned int drif1_data1_a_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(6, 20),
 };
-
 static const unsigned int drif1_data1_a_mux[] = {
 	RIF1_D1_A_MARK,
 };
-
 static const unsigned int drif1_ctrl_b_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
 };
-
 static const unsigned int drif1_ctrl_b_mux[] = {
 	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
 };
-
 static const unsigned int drif1_data0_b_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(5, 7),
 };
-
 static const unsigned int drif1_data0_b_mux[] = {
 	RIF1_D0_B_MARK,
 };
-
 static const unsigned int drif1_data1_b_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(5, 8),
 };
-
 static const unsigned int drif1_data1_b_mux[] = {
 	RIF1_D1_B_MARK,
 };
-
 static const unsigned int drif1_ctrl_c_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
 };
-
 static const unsigned int drif1_ctrl_c_mux[] = {
 	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
 };
-
 static const unsigned int drif1_data0_c_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(5, 6),
 };
-
 static const unsigned int drif1_data0_c_mux[] = {
 	RIF1_D0_C_MARK,
 };
-
 static const unsigned int drif1_data1_c_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(5, 10),
 };
-
 static const unsigned int drif1_data1_c_mux[] = {
 	RIF1_D1_C_MARK,
 };
-
 /* - DRIF2 --------------------------------------------------------------- */
 static const unsigned int drif2_ctrl_a_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
 };
-
 static const unsigned int drif2_ctrl_a_mux[] = {
 	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
 };
-
 static const unsigned int drif2_data0_a_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(6, 7),
 };
-
 static const unsigned int drif2_data0_a_mux[] = {
 	RIF2_D0_A_MARK,
 };
-
 static const unsigned int drif2_data1_a_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(6, 10),
 };
-
 static const unsigned int drif2_data1_a_mux[] = {
 	RIF2_D1_A_MARK,
 };
-
 static const unsigned int drif2_ctrl_b_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
 };
-
 static const unsigned int drif2_ctrl_b_mux[] = {
 	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
 };
-
 static const unsigned int drif2_data0_b_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(6, 30),
 };
-
 static const unsigned int drif2_data0_b_mux[] = {
 	RIF2_D0_B_MARK,
 };
-
 static const unsigned int drif2_data1_b_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(6, 31),
 };
-
 static const unsigned int drif2_data1_b_mux[] = {
 	RIF2_D1_B_MARK,
 };
-
 /* - DRIF3 --------------------------------------------------------------- */
 static const unsigned int drif3_ctrl_a_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
 };
-
 static const unsigned int drif3_ctrl_a_mux[] = {
 	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
 };
-
 static const unsigned int drif3_data0_a_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(6, 19),
 };
-
 static const unsigned int drif3_data0_a_mux[] = {
 	RIF3_D0_A_MARK,
 };
-
 static const unsigned int drif3_data1_a_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(6, 20),
 };
-
 static const unsigned int drif3_data1_a_mux[] = {
 	RIF3_D1_A_MARK,
 };
-
 static const unsigned int drif3_ctrl_b_pins[] = {
 	/* CLK, SYNC */
 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
 };
-
 static const unsigned int drif3_ctrl_b_mux[] = {
 	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
 };
-
 static const unsigned int drif3_data0_b_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(6, 28),
 };
-
 static const unsigned int drif3_data0_b_mux[] = {
 	RIF3_D0_B_MARK,
 };
-
 static const unsigned int drif3_data1_b_pins[] = {
 	/* D1 */
 	RCAR_GP_PIN(6, 29),
 };
-
 static const unsigned int drif3_data1_b_mux[] = {
 	RIF3_D1_B_MARK,
 };
···
 	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
 	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
 };
-
 static const unsigned int du_rgb666_mux[] = {
 	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
 	DU_DR3_MARK, DU_DR2_MARK,
···
 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
 	DU_DB3_MARK, DU_DB2_MARK,
 };
-
 static const unsigned int du_rgb888_pins[] = {
 	/* R[7:0], G[7:0], B[7:0] */
 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
···
 	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
 	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
 };
-
 static const unsigned int du_rgb888_mux[] = {
 	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
 	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
···
 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
 	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
 };
-
 static const unsigned int du_clk_out_0_pins[] = {
 	/* CLKOUT */
 	RCAR_GP_PIN(1, 27),
 };
-
 static const unsigned int du_clk_out_0_mux[] = {
 	DU_DOTCLKOUT0_MARK
 };
-
 static const unsigned int du_clk_out_1_pins[] = {
 	/* CLKOUT */
 	RCAR_GP_PIN(2, 3),
 };
-
 static const unsigned int du_clk_out_1_mux[] = {
 	DU_DOTCLKOUT1_MARK
 };
-
 static const unsigned int du_sync_pins[] = {
 	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
 };
-
 static const unsigned int du_sync_mux[] = {
 	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
 };
-
 static const unsigned int du_oddf_pins[] = {
 	/* EXDISP/EXODDF/EXCDE */
 	RCAR_GP_PIN(2, 2),
 };
-
 static const unsigned int du_oddf_mux[] = {
 	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
 };
-
 static const unsigned int du_cde_pins[] = {
 	/* CDE */
 	RCAR_GP_PIN(2, 0),
 };
-
 static const unsigned int du_cde_mux[] = {
 	DU_CDE_MARK,
 };
-
 static const unsigned int du_disp_pins[] = {
 	/* DISP */
 	RCAR_GP_PIN(2, 1),
 };
-
 static const unsigned int du_disp_mux[] = {
 	DU_DISP_MARK,
 };
···
 	/* RX, TX */
 	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
 };
-
 static const unsigned int hscif0_data_mux[] = {
 	HRX0_MARK, HTX0_MARK,
 };
-
 static const unsigned int hscif0_clk_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(5, 12),
 };
-
 static const unsigned int hscif0_clk_mux[] = {
 	HSCK0_MARK,
 };
-
 static const unsigned int hscif0_ctrl_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
 };
-
 static const unsigned int hscif0_ctrl_mux[] = {
 	HRTS0_N_MARK, HCTS0_N_MARK,
 };
-
 /* - HSCIF1 ----------------------------------------------------------------- */
 static const unsigned int hscif1_data_a_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
 };
-
 static const unsigned int hscif1_data_a_mux[] = {
 	HRX1_A_MARK, HTX1_A_MARK,
 };
-
 static const unsigned int hscif1_clk_a_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(6, 21),
 };
-
 static const unsigned int hscif1_clk_a_mux[] = {
 	HSCK1_A_MARK,
 };
-
 static const unsigned int hscif1_ctrl_a_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
 };
-
 static const unsigned int hscif1_ctrl_a_mux[] = {
 	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
 };
···
 	/* RX, TX */
 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
 };
-
 static const unsigned int hscif1_data_b_mux[] = {
 	HRX1_B_MARK, HTX1_B_MARK,
 };
-
 static const unsigned int hscif1_clk_b_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(5, 0),
 };
-
 static const unsigned int hscif1_clk_b_mux[] = {
 	HSCK1_B_MARK,
 };
-
 static const unsigned int hscif1_ctrl_b_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
 };
-
 static const unsigned int hscif1_ctrl_b_mux[] = {
 	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
 };
-
 /* - HSCIF2 ----------------------------------------------------------------- */
 static const unsigned int hscif2_data_a_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
 };
-
 static const unsigned int hscif2_data_a_mux[] = {
 	HRX2_A_MARK, HTX2_A_MARK,
 };
-
 static const unsigned int hscif2_clk_a_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(6, 10),
 };
-
 static const unsigned int hscif2_clk_a_mux[] = {
 	HSCK2_A_MARK,
 };
-
 static const unsigned int hscif2_ctrl_a_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
 };
-
 static const unsigned int hscif2_ctrl_a_mux[] = {
 	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
 };
···
 	/* RX, TX */
 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
 };
-
 static const unsigned int hscif2_data_b_mux[] = {
 	HRX2_B_MARK, HTX2_B_MARK,
 };
-
 static const unsigned int hscif2_clk_b_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(6, 21),
 };
-
 static const unsigned int hscif2_clk_b_mux[] = {
 	HSCK2_B_MARK,
 };
-
 static const unsigned int hscif2_ctrl_b_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
 };
-
 static const unsigned int hscif2_ctrl_b_mux[] = {
 	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
 };
···
 	/* RX, TX */
 	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
 };
-
 static const unsigned int hscif2_data_c_mux[] = {
 	HRX2_C_MARK, HTX2_C_MARK,
 };
-
 static const unsigned int hscif2_clk_c_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(6, 24),
 };
-
 static const unsigned int hscif2_clk_c_mux[] = {
 	HSCK2_C_MARK,
 };
-
 static const unsigned int hscif2_ctrl_c_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
 };
-
 static const unsigned int hscif2_ctrl_c_mux[] = {
 	HRTS2_N_C_MARK, HCTS2_N_C_MARK,
 };
-
 /* - HSCIF3 ----------------------------------------------------------------- */
 static const unsigned int hscif3_data_a_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
 };
-
 static const unsigned int hscif3_data_a_mux[] = {
 	HRX3_A_MARK, HTX3_A_MARK,
 };
-
 static const unsigned int hscif3_clk_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(1, 22),
 };
-
 static const unsigned int hscif3_clk_mux[] = {
 	HSCK3_MARK,
 };
-
 static const unsigned int hscif3_ctrl_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
 };
-
 static const unsigned int hscif3_ctrl_mux[] = {
 	HRTS3_N_MARK, HCTS3_N_MARK,
 };
···
 	/* RX, TX */
 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
 };
-
 static const unsigned int hscif3_data_b_mux[] = {
 	HRX3_B_MARK, HTX3_B_MARK,
 };
-
 static const unsigned int hscif3_data_c_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
 };
-
 static const unsigned int hscif3_data_c_mux[] = {
 	HRX3_C_MARK, HTX3_C_MARK,
 };
-
 static const unsigned int hscif3_data_d_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
 };
-
 static const unsigned int hscif3_data_d_mux[] = {
 	HRX3_D_MARK, HTX3_D_MARK,
 };
-
 /* - HSCIF4 ----------------------------------------------------------------- */
 static const unsigned int hscif4_data_a_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
 };
-
 static const unsigned int hscif4_data_a_mux[] = {
 	HRX4_A_MARK, HTX4_A_MARK,
 };
-
 static const unsigned int hscif4_clk_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(1, 11),
 };
-
 static const unsigned int hscif4_clk_mux[] = {
 	HSCK4_MARK,
 };
-
 static const unsigned int hscif4_ctrl_pins[] = {
 	/* RTS, CTS */
 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
 };
-
 static const unsigned int hscif4_ctrl_mux[] = {
 	HRTS4_N_MARK, HCTS4_N_MARK,
 };
···
 	/* RX, TX */
 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
 };
-
 static const unsigned int hscif4_data_b_mux[] = {
 	HRX4_B_MARK, HTX4_B_MARK,
 };
···
 	/* SDA, SCL */
 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
 };
-
 static const unsigned int i2c1_a_mux[] = {
 	SDA1_A_MARK, SCL1_A_MARK,
 };
-
 static const unsigned int i2c1_b_pins[] = {
 	/* SDA, SCL */
 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
 };
-
 static const unsigned int i2c1_b_mux[] = {
 	SDA1_B_MARK, SCL1_B_MARK,
 };
-
 static const unsigned int i2c2_a_pins[] = {
 	/* SDA, SCL */
 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
 };
-
 static const unsigned int i2c2_a_mux[] = {
 	SDA2_A_MARK, SCL2_A_MARK,
 };
-
 static const unsigned int i2c2_b_pins[] = {
 	/* SDA, SCL */
 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
 };
-
 static const unsigned int i2c2_b_mux[] = {
 	SDA2_B_MARK, SCL2_B_MARK,
 };
···
 	/* SDA, SCL */
 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
 };
-
 static const unsigned int i2c6_a_mux[] = {
 	SDA6_A_MARK, SCL6_A_MARK,
 };
-
 static const unsigned int i2c6_b_pins[] = {
 	/* SDA, SCL */
 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
 };
-
 static const unsigned int i2c6_b_mux[] = {
 	SDA6_B_MARK, SCL6_B_MARK,
 };
-
 static const unsigned int i2c6_c_pins[] = {
 	/* SDA, SCL */
 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
 };
-
 static const unsigned int i2c6_c_mux[] = {
 	SDA6_C_MARK, SCL6_C_MARK,
 };
···
 static const unsigned int msiof3_rxd_d_mux[] = {
 	MSIOF3_RXD_D_MARK,
 };
+
 static const unsigned int msiof3_clk_e_pins[] = {
 	/* SCK */
 	RCAR_GP_PIN(2, 3),
···
 	PWM6_B_MARK,
 };
 
-/* - SATA --------------------------------------------------------------------*/
-static const unsigned int sata0_devslp_a_pins[] = {
-	/* DEVSLP */
-	RCAR_GP_PIN(6, 16),
-};
-
-static const unsigned int sata0_devslp_a_mux[] = {
-	SATA_DEVSLP_A_MARK,
-};
-
-static const unsigned int sata0_devslp_b_pins[] = {
-	/* DEVSLP */
-	RCAR_GP_PIN(4, 6),
-};
-
-static const unsigned int sata0_devslp_b_mux[] = {
-	SATA_DEVSLP_B_MARK,
-};
-
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX, TX */
···
 static const unsigned int scif1_ctrl_mux[] = {
 	RTS1_N_MARK, CTS1_N_MARK,
 };
+
 static const unsigned int scif1_data_b_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
···
 static const unsigned int scif5_clk_a_mux[] = {
 	SCK5_A_MARK,
 };
+
 static const unsigned int scif5_data_b_pins[] = {
 	/* RX, TX */
 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
···
 static const unsigned int scif5_clk_b_mux[] = {
 	SCK5_B_MARK,
 };
+
 /* - SCIF Clock ------------------------------------------------------------- */
 static const unsigned int scif_clk_a_pins[] = {
 	/* SCIF_CLK */
···
 	/* D0 */
 	RCAR_GP_PIN(3, 2),
 };
-
 static const unsigned int sdhi0_data1_mux[] = {
 	SD0_DAT0_MARK,
 };
-
 static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
 	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
 };
-
 static const unsigned int sdhi0_data4_mux[] = {
 	SD0_DAT0_MARK, SD0_DAT1_MARK,
 	SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
-
 static const unsigned int sdhi0_ctrl_pins[] = {
 	/* CLK, CMD */
 	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
 };
-
 static const unsigned int sdhi0_ctrl_mux[] = {
 	SD0_CLK_MARK, SD0_CMD_MARK,
 };
-
 static const unsigned int sdhi0_cd_pins[] = {
 	/* CD */
 	RCAR_GP_PIN(3, 12),
 };
-
 static const unsigned int sdhi0_cd_mux[] = {
 	SD0_CD_MARK,
 };
-
 static const unsigned int sdhi0_wp_pins[] = {
 	/* WP */
 	RCAR_GP_PIN(3, 13),
 };
-
 static const unsigned int sdhi0_wp_mux[] = {
 	SD0_WP_MARK,
 };
-
 /* - SDHI1 ------------------------------------------------------------------ */
 static const unsigned int sdhi1_data1_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(3, 8),
 };
-
 static const unsigned int sdhi1_data1_mux[] = {
 	SD1_DAT0_MARK,
 };
-
 static const unsigned int sdhi1_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
-
 static const unsigned int sdhi1_data4_mux[] = {
 	SD1_DAT0_MARK, SD1_DAT1_MARK,
 	SD1_DAT2_MARK, SD1_DAT3_MARK,
 };
-
 static const unsigned int sdhi1_ctrl_pins[] = {
 	/* CLK, CMD */
 	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
 };
-
 static const unsigned int sdhi1_ctrl_mux[] = {
 	SD1_CLK_MARK, SD1_CMD_MARK,
 };
-
 static const unsigned int sdhi1_cd_pins[] = {
 	/* CD */
 	RCAR_GP_PIN(3, 14),
 };
-
 static const unsigned int sdhi1_cd_mux[] = {
 	SD1_CD_MARK,
 };
-
 static const unsigned int sdhi1_wp_pins[] = {
 	/* WP */
 	RCAR_GP_PIN(3, 15),
 };
-
 static const unsigned int sdhi1_wp_mux[] = {
 	SD1_WP_MARK,
 };
-
 /* - SDHI2 ------------------------------------------------------------------ */
 static const unsigned int sdhi2_data1_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(4, 2),
 };
-
 static const unsigned int sdhi2_data1_mux[] = {
 	SD2_DAT0_MARK,
 };
-
 static const unsigned int sdhi2_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
 };
-
 static const unsigned int sdhi2_data4_mux[] = {
 	SD2_DAT0_MARK, SD2_DAT1_MARK,
 	SD2_DAT2_MARK, SD2_DAT3_MARK,
 };
-
 static const unsigned int sdhi2_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
···
 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
-
 static const unsigned int sdhi2_data8_mux[] = {
 	SD2_DAT0_MARK, SD2_DAT1_MARK,
 	SD2_DAT2_MARK, SD2_DAT3_MARK,
 	SD2_DAT4_MARK, SD2_DAT5_MARK,
 	SD2_DAT6_MARK, SD2_DAT7_MARK,
 };
-
 static const unsigned int sdhi2_ctrl_pins[] = {
 	/* CLK, CMD */
 	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
 };
-
 static const unsigned int sdhi2_ctrl_mux[] = {
 	SD2_CLK_MARK, SD2_CMD_MARK,
 };
-
 static const unsigned int sdhi2_cd_a_pins[] = {
 	/* CD */
 	RCAR_GP_PIN(4, 13),
 };
-
 static const unsigned int sdhi2_cd_a_mux[] = {
 	SD2_CD_A_MARK,
 };
-
 static const unsigned int sdhi2_cd_b_pins[] = {
 	/* CD */
 	RCAR_GP_PIN(5, 10),
 };
-
 static const unsigned int sdhi2_cd_b_mux[] = {
 	SD2_CD_B_MARK,
 };
-
 static const unsigned int sdhi2_wp_a_pins[] = {
 	/* WP */
 	RCAR_GP_PIN(4, 14),
 };
-
 static const unsigned int sdhi2_wp_a_mux[] = {
 	SD2_WP_A_MARK,
 };
-
 static const unsigned int sdhi2_wp_b_pins[] = {
 	/* WP */
 	RCAR_GP_PIN(5, 11),
 };
-
 static const unsigned int sdhi2_wp_b_mux[] = {
 	SD2_WP_B_MARK,
 };
-
 static const unsigned int sdhi2_ds_pins[] = {
 	/* DS */
 	RCAR_GP_PIN(4, 6),
 };
-
 static const unsigned int sdhi2_ds_mux[] = {
 	SD2_DS_MARK,
 };
-
 /* - SDHI3 ------------------------------------------------------------------ */
 static const unsigned int sdhi3_data1_pins[] = {
 	/* D0 */
 	RCAR_GP_PIN(4, 9),
 };
-
 static const unsigned int sdhi3_data1_mux[] = {
 	SD3_DAT0_MARK,
 };
-
 static const unsigned int sdhi3_data4_pins[] = {
 	/* D[0:3] */
 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
 };
-
 static const unsigned int sdhi3_data4_mux[] = {
 	SD3_DAT0_MARK, SD3_DAT1_MARK,
 	SD3_DAT2_MARK, SD3_DAT3_MARK,
 };
-
 static const unsigned int sdhi3_data8_pins[] = {
 	/* D[0:7] */
 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
···
 	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
 };
-
 static const unsigned int sdhi3_data8_mux[] = {
 	SD3_DAT0_MARK, SD3_DAT1_MARK,
 	SD3_DAT2_MARK, SD3_DAT3_MARK,
 	SD3_DAT4_MARK, SD3_DAT5_MARK,
 	SD3_DAT6_MARK, SD3_DAT7_MARK,
 };
-
 static const unsigned int sdhi3_ctrl_pins[] = {
 	/* CLK, CMD */
 	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
 };
-
 static const unsigned int sdhi3_ctrl_mux[] = {
 	SD3_CLK_MARK, SD3_CMD_MARK,
 };
-
 static const unsigned int sdhi3_cd_pins[] = {
 	/* CD */
 	RCAR_GP_PIN(4, 15),
 };
-
 static const unsigned int sdhi3_cd_mux[] = {
 	SD3_CD_MARK,
 };
-
 static const unsigned int sdhi3_wp_pins[] = {
 	/* WP */
 	RCAR_GP_PIN(4, 16),
 };
-
 static const unsigned int sdhi3_wp_mux[] = {
 	SD3_WP_MARK,
 };
-
 static const unsigned int sdhi3_ds_pins[] = {
 	/* DS */
 	RCAR_GP_PIN(4, 17),
 };
-
 static const unsigned int sdhi3_ds_mux[] = {
 	SD3_DS_MARK,
 };
···
 	/* TCLK */
 	RCAR_GP_PIN(6, 23),
 };
-
 static const unsigned int tmu_tclk1_a_mux[] = {
 	TCLK1_A_MARK,
 };
-
 static const unsigned int tmu_tclk1_b_pins[] = {
 	/* TCLK */
 	RCAR_GP_PIN(5, 19),
 };
-
 static const unsigned int tmu_tclk1_b_mux[] = {
 	TCLK1_B_MARK,
 };
-
 static const unsigned int tmu_tclk2_a_pins[] = {
 	/* TCLK */
 	RCAR_GP_PIN(6, 19),
 };
-
 static const unsigned int tmu_tclk2_a_mux[] = {
 	TCLK2_A_MARK,
 };
-
 static const unsigned int tmu_tclk2_b_pins[] = {
 	/* TCLK */
 	RCAR_GP_PIN(6, 28),
 };
-
 static const unsigned int tmu_tclk2_b_mux[] = {
 	TCLK2_B_MARK,
 };
···
 	/* PWEN, OVC */
 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
 };
-
 static const unsigned int usb0_mux[] = {
 	USB0_PWEN_MARK, USB0_OVC_MARK,
 };
-
 /* - USB1 ------------------------------------------------------------------- */
 static const unsigned int usb1_pins[] = {
 	/* PWEN, OVC */
 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
 };
-
 static const unsigned int usb1_mux[] = {
 	USB1_PWEN_MARK, USB1_OVC_MARK,
 };
···
 	/* PWEN, OVC */
 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
 };
-
 static const unsigned int usb30_mux[] = {
 	USB30_PWEN_MARK, USB30_OVC_MARK,
 };
···
 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-	RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
-	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
-	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
-	RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
+	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 };
-
 static const unsigned int vin4_data18_a_mux[] = {
 	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
 	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
 	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-	VI4_DATA10_MARK,  VI4_DATA11_MARK,
-	VI4_DATA12_MARK,  VI4_DATA13_MARK,
-	VI4_DATA14_MARK,  VI4_DATA15_MARK,
-	VI4_DATA18_MARK,  VI4_DATA19_MARK,
-	VI4_DATA20_MARK,  VI4_DATA21_MARK,
-	VI4_DATA22_MARK,  VI4_DATA23_MARK,
+	VI4_DATA10_MARK, VI4_DATA11_MARK,
+	VI4_DATA12_MARK, VI4_DATA13_MARK,
+	VI4_DATA14_MARK, VI4_DATA15_MARK,
+	VI4_DATA18_MARK, VI4_DATA19_MARK,
+	VI4_DATA20_MARK, VI4_DATA21_MARK,
+	VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
-
-static const union vin_data vin4_data_a_pins = {
-	.data24 = {
-		RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 9),
-		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-		RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 1),
-		RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
-		RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
-		RCAR_GP_PIN(0, 0),  RCAR_GP_PIN(0, 1),
-		RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
-		RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
-		RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
-	},
-};
-
-static const union vin_data vin4_data_a_mux = {
-	.data24 = {
-		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-		VI4_DATA8_MARK,   VI4_DATA9_MARK,
-		VI4_DATA10_MARK,  VI4_DATA11_MARK,
-		VI4_DATA12_MARK,  VI4_DATA13_MARK,
-		VI4_DATA14_MARK,  VI4_DATA15_MARK,
-		VI4_DATA16_MARK,  VI4_DATA17_MARK,
-		VI4_DATA18_MARK,  VI4_DATA19_MARK,
-		VI4_DATA20_MARK,  VI4_DATA21_MARK,
-		VI4_DATA22_MARK,  VI4_DATA23_MARK,
-	},
-};
-
 static const unsigned int vin4_data18_b_pins[] = {
 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
···
 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 };
-
 static const unsigned int vin4_data18_b_mux[] = {
 	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
 	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
 	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-	VI4_DATA10_MARK,  VI4_DATA11_MARK,
-	VI4_DATA12_MARK,  VI4_DATA13_MARK,
-	VI4_DATA14_MARK,  VI4_DATA15_MARK,
-	VI4_DATA18_MARK,  VI4_DATA19_MARK,
-	VI4_DATA20_MARK,  VI4_DATA21_MARK,
-	VI4_DATA22_MARK,  VI4_DATA23_MARK,
+	VI4_DATA10_MARK, VI4_DATA11_MARK,
+	VI4_DATA12_MARK, VI4_DATA13_MARK,
+	VI4_DATA14_MARK, VI4_DATA15_MARK,
+	VI4_DATA18_MARK, VI4_DATA19_MARK,
+	VI4_DATA20_MARK, VI4_DATA21_MARK,
+	VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
-
+static const union vin_data vin4_data_a_pins = {
+	.data24 = {
+		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+		RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+		RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+	},
+};
+static const union vin_data vin4_data_a_mux = {
+	.data24 = {
+		VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+		VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+		VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+		VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+		VI4_DATA8_MARK,  VI4_DATA9_MARK,
+		VI4_DATA10_MARK, VI4_DATA11_MARK,
+		VI4_DATA12_MARK, VI4_DATA13_MARK,
+		VI4_DATA14_MARK, VI4_DATA15_MARK,
+		VI4_DATA16_MARK, VI4_DATA17_MARK,
+		VI4_DATA18_MARK, VI4_DATA19_MARK,
+		VI4_DATA20_MARK, VI4_DATA21_MARK,
+		VI4_DATA22_MARK, VI4_DATA23_MARK,
+	},
+};
 static const union vin_data vin4_data_b_pins = {
 	.data24 = {
 		RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
···
 		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 	},
 };
-
 static const union vin_data vin4_data_b_mux = {
 	.data24 = {
 		VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
 		VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
 		VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
 		VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-		VI4_DATA8_MARK,   VI4_DATA9_MARK,
-		VI4_DATA10_MARK,  VI4_DATA11_MARK,
-		VI4_DATA12_MARK,  VI4_DATA13_MARK,
-		VI4_DATA14_MARK,  VI4_DATA15_MARK,
-		VI4_DATA16_MARK,  VI4_DATA17_MARK,
-		VI4_DATA18_MARK,  VI4_DATA19_MARK,
-		VI4_DATA20_MARK,  VI4_DATA21_MARK,
-		VI4_DATA22_MARK,  VI4_DATA23_MARK,
+		VI4_DATA8_MARK,  VI4_DATA9_MARK,
+		VI4_DATA10_MARK, VI4_DATA11_MARK,
+		VI4_DATA12_MARK, VI4_DATA13_MARK,
+		VI4_DATA14_MARK, VI4_DATA15_MARK,
+		VI4_DATA16_MARK, VI4_DATA17_MARK,
+		VI4_DATA18_MARK, VI4_DATA19_MARK,
+		VI4_DATA20_MARK, VI4_DATA21_MARK,
+		VI4_DATA22_MARK, VI4_DATA23_MARK,
 	},
 };
-
 static const unsigned int vin4_sync_pins[] = {
-	/* VSYNC_N, HSYNC_N */
-	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
+	/* HSYNC#, VSYNC# */
+	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
 };
-
 static const unsigned int vin4_sync_mux[] = {
 	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
 };
-
 static const unsigned int vin4_field_pins[] = {
+	/* FIELD */
 	RCAR_GP_PIN(1, 16),
 };
-
 static const unsigned int vin4_field_mux[] = {
 	VI4_FIELD_MARK,
 };
-
 static const unsigned int vin4_clkenb_pins[] = {
+	/* CLKENB */
 	RCAR_GP_PIN(1, 19),
 };
-
 static const unsigned int vin4_clkenb_mux[] = {
 	VI4_CLKENB_MARK,
 };
-
 static const unsigned int vin4_clk_pins[] = {
+	/* CLK */
 	RCAR_GP_PIN(1, 27),
 };
-
 static const unsigned int vin4_clk_mux[] = {
 	VI4_CLK_MARK,
 };
···
 		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
 		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
-		RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
-		RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
+		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
 	},
 };
-
 static const union vin_data16 vin5_data_mux = {
 	.data16 = {
 		VI5_DATA0_MARK, VI5_DATA1_MARK,
···
 		VI5_DATA14_MARK, VI5_DATA15_MARK,
 	},
 };
-
 static const unsigned int vin5_sync_pins[] = {
-	/* VSYNC_N, HSYNC_N */
-	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
+	/* HSYNC#, VSYNC# */
+	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
 };
-
 static const unsigned int vin5_sync_mux[] = {
 	VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
 };
-
 static const unsigned int vin5_field_pins[] = {
 	RCAR_GP_PIN(1, 11),
 };
-
 static const unsigned int vin5_field_mux[] = {
+	/* FIELD */
 	VI5_FIELD_MARK,
 };
-
 static const unsigned int vin5_clkenb_pins[] = {
 	RCAR_GP_PIN(1, 20),
 };
-
 static const unsigned int vin5_clkenb_mux[] = {
+	/* CLKENB */
 	VI5_CLKENB_MARK,
 };
-
 static const unsigned int vin5_clk_pins[] = {
 	RCAR_GP_PIN(1, 21),
 };
-
 static const unsigned int vin5_clk_mux[] = {
+	/* CLK */
 	VI5_CLK_MARK,
 };
 
 static const struct {
-	struct sh_pfc_pin_group common[318];
+	struct sh_pfc_pin_group common[316];
 	struct sh_pfc_pin_group automotive[30];
 } pinmux_groups = {
 	.common = {
···
 		SH_PFC_PIN_GROUP(avb_link),
 		SH_PFC_PIN_GROUP(avb_magic),
 		SH_PFC_PIN_GROUP(avb_phy_int),
-		SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),	/* Deprecated */
+		SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
 		SH_PFC_PIN_GROUP(avb_mdio),
 		SH_PFC_PIN_GROUP(avb_mii),
 		SH_PFC_PIN_GROUP(avb_avtp_pps),
···
 		SH_PFC_PIN_GROUP(pwm5_b),
 		SH_PFC_PIN_GROUP(pwm6_a),
 		SH_PFC_PIN_GROUP(pwm6_b),
-		SH_PFC_PIN_GROUP(sata0_devslp_a),
-		SH_PFC_PIN_GROUP(sata0_devslp_b),
 		SH_PFC_PIN_GROUP(scif0_data),
 		SH_PFC_PIN_GROUP(scif0_clk),
 		SH_PFC_PIN_GROUP(scif0_ctrl),
···
 	"pwm6_b",
 };
 
-static const char * const sata0_groups[] = {
-	"sata0_devslp_a",
-	"sata0_devslp_b",
-};
-
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
···
 	"scif1_ctrl",
 	"scif1_data_b",
 };
+
 static const char * const scif2_groups[] = {
 	"scif2_data_a",
 	"scif2_clk",
···
 };
 
 static const struct {
-	struct sh_pfc_function common[51];
+	struct sh_pfc_function common[50];
 	struct sh_pfc_function automotive[4];
 } pinmux_functions = {
 	.common = {
···
 		SH_PFC_FUNCTION(pwm4),
 		SH_PFC_FUNCTION(pwm5),
 		SH_PFC_FUNCTION(pwm6),
-		SH_PFC_FUNCTION(sata0),
 		SH_PFC_FUNCTION(scif0),
 		SH_PFC_FUNCTION(scif1),
 		SH_PFC_FUNCTION(scif2),
···
 		{ PIN_DU_DOTCLKIN1,    0, 2 },	/* DU_DOTCLKIN1 */
 	} },
 	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
-		{ PIN_DU_DOTCLKIN3,   24, 2 },	/* DU_DOTCLKIN3 */
+		{ PIN_DU_DOTCLKIN2,   28, 2 },	/* DU_DOTCLKIN2 */
 		{ PIN_FSCLKST,        20, 2 },	/* FSCLKST */
 		{ PIN_TMS,             4, 2 },	/* TMS */
 	} },
···
 	{ /* sentinel */ },
 };
 
-static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
 {
 	int bit = -EINVAL;
 
···
 		[31] = PIN_DU_DOTCLKIN1,	/* DU_DOTCLKIN1 */
 	} },
 	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
-		[ 0] = SH_PFC_PIN_NONE,
-		[ 1] = PIN_DU_DOTCLKIN3,	/* DU_DOTCLKIN3 */
+		[ 0] = PIN_DU_DOTCLKIN2,	/* DU_DOTCLKIN2 */
+		[ 1] = SH_PFC_PIN_NONE,
 		[ 2] = PIN_FSCLKST,		/* FSCLKST */
 		[ 3] = PIN_EXTALR,		/* EXTALR*/
 		[ 4] = PIN_TRST_N,		/* TRST# */
···
 	{ /* sentinel */ },
 };
 
-static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
+static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
 					    unsigned int pin)
 {
 	const struct pinmux_bias_reg *reg;
···
 		return PIN_CONFIG_BIAS_PULL_DOWN;
 }
 
-static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
 				   unsigned int bias)
 {
 	const struct pinmux_bias_reg *reg;
···
 	sh_pfc_write(pfc, reg->puen, enable);
 }
 
-static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
-	.pin_to_pocctrl = r8a77965_pin_to_pocctrl,
-	.get_bias = r8a77965_pinmux_get_bias,
-	.set_bias = r8a77965_pinmux_set_bias,
+static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
+	.pin_to_pocctrl = r8a7796_pin_to_pocctrl,
+	.get_bias = r8a7796_pinmux_get_bias,
+	.set_bias = r8a7796_pinmux_set_bias,
 };
 
-#ifdef CONFIG_PINCTRL_PFC_R8A774B1
-const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
-	.name = "r8a774b1_pfc",
-	.ops = &r8a77965_pinmux_ops,
+#ifdef CONFIG_PINCTRL_PFC_R8A774A1
+const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
+	.name = "r8a774a1_pfc",
+	.ops = &r8a7796_pinmux_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
···
 };
 #endif
 
-#ifdef CONFIG_PINCTRL_PFC_R8A77965
-const struct sh_pfc_soc_info r8a77965_pinmux_info = {
-	.name = "r8a77965_pfc",
-	.ops = &r8a77965_pinmux_ops,
+#ifdef CONFIG_PINCTRL_PFC_R8A77960
+const struct sh_pfc_soc_info r8a77960_pinmux_info = {
+	.name = "r8a77960_pfc",
+	.ops = &r8a7796_pinmux_ops,
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.pins = pinmux_pins,
+	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.groups = pinmux_groups.common,
+	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
+		ARRAY_SIZE(pinmux_groups.automotive),
+	.functions = pinmux_functions.common,
+	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
+		ARRAY_SIZE(pinmux_functions.automotive),
+
+	.cfg_regs = pinmux_config_regs,
+	.drive_regs = pinmux_drive_regs,
+	.bias_regs = pinmux_bias_regs,
+	.ioctrl_regs = pinmux_ioctrl_regs,
+
+	.pinmux_data = pinmux_data,
+	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
+
+#ifdef CONFIG_PINCTRL_PFC_R8A77961
+const struct sh_pfc_soc_info r8a77961_pinmux_info = {
+	.name = "r8a77961_pfc",
+	.ops = &r8a7796_pinmux_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

drivers/pinctrl/sh-pfc/pfc-r8a77970.c drivers/pinctrl/renesas/pfc-r8a77980.c

···
 // SPDX-License-Identifier: GPL-2.0
 /*
- * R8A77970 processor support - PFC hardware block.
+ * R8A77980 processor support - PFC hardware block.
  *
- * Copyright (C) 2016 Renesas Electronics Corp.
- * Copyright (C) 2017 Cogent Embedded, Inc. <[e-mail]>
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
  *
- * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+ * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
  *
  * R-Car Gen3 processor support - PFC hardware block.
  *
- * Copyright (C) 2015  Renesas Electronics Corporation
+ * Copyright (C) 2015 Renesas Electronics Corporation
  */
 
 #include <linux/errno.h>
···
 #include "core.h"
 #include "sh_pfc.h"
 
-#define CPU_ALL_GP(fn, sfx)						\
-	PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
-	PORT_GP_28(1, fn, sfx),						\
-	PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
-	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
-	PORT_GP_6(4,  fn, sfx),						\
+#define CPU_ALL_GP(fn, sfx)	\
+	PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
+	PORT_GP_28(1, fn, sfx),	\
+	PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
+	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+	PORT_GP_25(4, fn, sfx),	\
 	PORT_GP_15(5, fn, sfx)
+
 /*
  * F_() : just information
  * FM() : macro for FN_xxx / xxx_MARK
···
 #define GPSR0_0		F_(DU_DR2,			IP0_3_0)
 
 /* GPSR1 */
-#define GPSR1_27	F_(DIGRF_CLKOUT,	IP8_27_24)
-#define GPSR1_26	F_(DIGRF_CLKIN,		IP8_23_20)
-#define GPSR1_25	F_(CANFD_CLK_A,		IP8_19_16)
-#define GPSR1_24	F_(CANFD1_RX,		IP8_15_12)
-#define GPSR1_23	F_(CANFD1_TX,		IP8_11_8)
-#define GPSR1_22	F_(CANFD0_RX_A,		IP8_7_4)
-#define GPSR1_21	F_(CANFD0_TX_A,		IP8_3_0)
-#define GPSR1_20	F_(AVB0_AVTP_CAPTURE,	IP7_31_28)
-#define GPSR1_19	FM(AVB0_AVTP_MATCH)
-#define GPSR1_18	FM(AVB0_LINK)
-#define GPSR1_17	FM(AVB0_PHY_INT)
-#define GPSR1_16	FM(AVB0_MAGIC)
-#define GPSR1_15	FM(AVB0_MDC)
-#define GPSR1_14	FM(AVB0_MDIO)
-#define GPSR1_13	FM(AVB0_TXCREFCLK)
-#define GPSR1_12	FM(AVB0_TD3)
-#define GPSR1_11	FM(AVB0_TD2)
-#define GPSR1_10	FM(AVB0_TD1)
-#define GPSR1_9		FM(AVB0_TD0)
-#define GPSR1_8		FM(AVB0_TXC)
-#define GPSR1_7		FM(AVB0_TX_CTL)
-#define GPSR1_6		FM(AVB0_RD3)
-#define GPSR1_5		FM(AVB0_RD2)
-#define GPSR1_4		FM(AVB0_RD1)
-#define GPSR1_3		FM(AVB0_RD0)
-#define GPSR1_2		FM(AVB0_RXC)
-#define GPSR1_1		FM(AVB0_RX_CTL)
+#define GPSR1_27	F_(DIGRF_CLKOUT,	IP8_31_28)
+#define GPSR1_26	F_(DIGRF_CLKIN,		IP8_27_24)
+#define GPSR1_25	F_(CANFD_CLK_A,		IP8_23_20)
+#define GPSR1_24	F_(CANFD1_RX,		IP8_19_16)
+#define GPSR1_23	F_(CANFD1_TX,		IP8_15_12)
+#define GPSR1_22	F_(CANFD0_RX_A,		IP8_11_8)
+#define GPSR1_21	F_(CANFD0_TX_A,		IP8_7_4)
+#define GPSR1_20	F_(AVB_AVTP_CAPTURE,	IP8_3_0)
+#define GPSR1_19	F_(AVB_AVTP_MATCH,	IP7_31_28)
+#define GPSR1_18	FM(AVB_LINK)
+#define GPSR1_17	FM(AVB_PHY_INT)
+#define GPSR1_16	FM(AVB_MAGIC)
+#define GPSR1_15	FM(AVB_MDC)
+#define GPSR1_14	FM(AVB_MDIO)
+#define GPSR1_13	FM(AVB_TXCREFCLK)
+#define GPSR1_12	FM(AVB_TD3)
+#define GPSR1_11	FM(AVB_TD2)
+#define GPSR1_10	FM(AVB_TD1)
+#define GPSR1_9		FM(AVB_TD0)
+#define GPSR1_8		FM(AVB_TXC)
+#define GPSR1_7		FM(AVB_TX_CTL)
+#define GPSR1_6		FM(AVB_RD3)
+#define GPSR1_5		FM(AVB_RD2)
+#define GPSR1_4		FM(AVB_RD1)
+#define GPSR1_3		FM(AVB_RD0)
+#define GPSR1_2		FM(AVB_RXC)
+#define GPSR1_1		FM(AVB_RX_CTL)
 #define GPSR1_0		F_(IRQ0,		IP2_27_24)
 
 /* GPSR2 */
+#define GPSR2_29	F_(FSO_TOE_N,  		IP10_19_16)
+#define GPSR2_28	F_(FSO_CFE_1_N,		IP10_15_12)
+#define GPSR2_27	F_(FSO_CFE_0_N,		IP10_11_8)
+#define GPSR2_26	F_(SDA3,		IP10_7_4)
+#define GPSR2_25	F_(SCL3,		IP10_3_0)
+#define GPSR2_24	F_(MSIOF0_SS2,		IP9_31_28)
+#define GPSR2_23	F_(MSIOF0_SS1,		IP9_27_24)
+#define GPSR2_22	F_(MSIOF0_SYNC,		IP9_23_20)
+#define GPSR2_21	F_(MSIOF0_SCK,		IP9_19_16)
+#define GPSR2_20	F_(MSIOF0_TXD,		IP9_15_12)
+#define GPSR2_19	F_(MSIOF0_RXD,		IP9_11_8)
+#define GPSR2_18	F_(IRQ5,		IP9_7_4)
+#define GPSR2_17	F_(IRQ4,		IP9_3_0)
 #define GPSR2_16	F_(VI0_FIELD,		IP4_31_28)
 #define GPSR2_15	F_(VI0_DATA11,		IP4_27_24)
 #define GPSR2_14	F_(VI0_DATA10,		IP4_23_20)
···
 #define GPSR3_0		F_(VI1_CLK,		IP5_3_0)
 
 /* GPSR4 */
+#define GPSR4_24	FM(GETHER_LINK_A)
+#define GPSR4_23	FM(GETHER_PHY_INT_A)
+#define GPSR4_22	FM(GETHER_MAGIC)
+#define GPSR4_21	FM(GETHER_MDC_A)
+#define GPSR4_20	FM(GETHER_MDIO_A)
+#define GPSR4_19	FM(GETHER_TXCREFCLK_MEGA)
+#define GPSR4_18	FM(GETHER_TXCREFCLK)
+#define GPSR4_17	FM(GETHER_TD3)
+#define GPSR4_16	FM(GETHER_TD2)
+#define GPSR4_15	FM(GETHER_TD1)
+#define GPSR4_14	FM(GETHER_TD0)
+#define GPSR4_13	FM(GETHER_TXC)
+#define GPSR4_12	FM(GETHER_TX_CTL)
+#define GPSR4_11	FM(GETHER_RD3)
+#define GPSR4_10	FM(GETHER_RD2)
+#define GPSR4_9		FM(GETHER_RD1)
+#define GPSR4_8		FM(GETHER_RD0)
+#define GPSR4_7		FM(GETHER_RXC)
+#define GPSR4_6		FM(GETHER_RX_CTL)
 #define GPSR4_5		F_(SDA2,		IP7_27_24)
 #define GPSR4_4		F_(SCL2,		IP7_23_20)
 #define GPSR4_3		F_(SDA1,		IP7_19_16)
···
 #define GPSR5_0		FM(QSPI0_SPCLK)
 
 
-/* IPSRx */		/* 0 */				/* 1 */			/* 2 */		/* 3 */		/* 4 */			/* 5 */		/* 6 - F */
-#define IP0_3_0		FM(DU_DR2)			FM(HSCK0)		F_(0, 0)	FM(A0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_7_4		FM(DU_DR3)			FM(HRTS0_N)		F_(0, 0)	FM(A1)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_11_8	FM(DU_DR4)			FM(HCTS0_N)		F_(0, 0)	FM(A2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)	F_(0, 0) F_(0, 0)
-#define IP0_15_12	FM(DU_DR5)			FM(HTX0)		F_(0, 0)	FM(A3)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_19_16	FM(DU_DR6)			FM(MSIOF3_RXD)		F_(0, 0)	FM(A4)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_23_20	FM(DU_DR7)			FM(MSIOF3_TXD)		F_(0, 0)	FM(A5)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24	FM(DU_DG2)			FM(MSIOF3_SS1)		F_(0, 0)	FM(A6)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28	FM(DU_DG3)			FM(MSIOF3_SS2)		F_(0, 0)	FM(A7)		FM(PWMFSW0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_3_0		FM(DU_DG4)			F_(0, 0)		F_(0, 0)	FM(A8)		FM(FSO_CFE_0_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_7_4		FM(DU_DG5)			F_(0, 0)		F_(0, 0)	FM(A9)		FM(FSO_CFE_1_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8	FM(DU_DG6)			F_(0, 0)		F_(0, 0)	FM(A10)		FM(FSO_TOE_N_A) 	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_15_12	FM(DU_DG7)			F_(0, 0)		F_(0, 0)	FM(A11)		FM(IRQ1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_19_16	FM(DU_DB2)			F_(0, 0)		F_(0, 0)	FM(A12)		FM(IRQ2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_23_20	FM(DU_DB3)			F_(0, 0)		F_(0, 0)	FM(A13)		FM(FXR_CLKOUT1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_27_24	FM(DU_DB4)			F_(0, 0)		F_(0, 0)	FM(A14)		FM(FXR_CLKOUT2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_31_28	FM(DU_DB5)			F_(0, 0)		F_(0, 0)	FM(A15)		FM(FXR_TXENA_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_3_0		FM(DU_DB6)			F_(0, 0)		F_(0, 0)	FM(A16)		FM(FXR_TXENB_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_7_4		FM(DU_DB7)			F_(0, 0)		F_(0, 0)	FM(A17)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_11_8	FM(DU_DOTCLKOUT)		FM(SCIF_CLK_A)		F_(0, 0)	FM(A18)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_15_12	FM(DU_EXHSYNC_DU_HSYNC)		FM(HRX0)		F_(0, 0)	FM(A19)		FM(IRQ3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_19_16	FM(DU_EXVSYNC_DU_VSYNC)		FM(MSIOF3_SCK)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20	FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(MSIOF3_SYNC)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24	FM(IRQ0)			F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_31_28	FM(VI0_CLK)			FM(MSIOF2_SCK)		FM(SCK3)	F_(0, 0)	FM(HSCK3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_3_0		FM(VI0_CLKENB)			FM(MSIOF2_RXD)		FM(RX3)		FM(RD_WR_N)	FM(HCTS3_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_7_4		FM(VI0_HSYNC_N)			FM(MSIOF2_TXD)		FM(TX3)		F_(0, 0)	FM(HRTS3_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_11_8	FM(VI0_VSYNC_N)			FM(MSIOF2_SYNC)		FM(CTS3_N)	F_(0, 0)	FM(HTX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12	FM(VI0_DATA0)			FM(MSIOF2_SS1)		FM(RTS3_N)	F_(0, 0)	FM(HRX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_19_16	FM(VI0_DATA1)			FM(MSIOF2_SS2)		FM(SCK1)	F_(0, 0)	FM(SPEEDIN_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_23_20	FM(VI0_DATA2)			FM(AVB0_AVTP_PPS)	FM(SDA3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_27_24	FM(VI0_DATA3)			FM(HSCK1)		FM(SCL3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_31_28	FM(VI0_DATA4)			FM(HRTS1_N)		FM(RX1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_3_0		FM(VI0_DATA5)			FM(HCTS1_N)		FM(TX1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_7_4		FM(VI0_DATA6)			FM(HTX1)		FM(CTS1_N)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_11_8	FM(VI0_DATA7)			FM(HRX1)		FM(RTS1_N)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_15_12	FM(VI0_DATA8)			FM(HSCK2)		FM(PWM0_A)	FM(A22)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_19_16	FM(VI0_DATA9)			FM(HCTS2_N)		FM(PWM1_A)	FM(A23)		FM(FSO_CFE_0_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_23_20	FM(VI0_DATA10)			FM(HRTS2_N)		FM(PWM2_A)	FM(A24)		FM(FSO_CFE_1_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_27_24	FM(VI0_DATA11)			FM(HTX2)		FM(PWM3_A)	FM(A25)		FM(FSO_TOE_N_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_31_28	FM(VI0_FIELD)			FM(HRX2)		FM(PWM4_A)	FM(CS1_N)	FM(FSCLKST2_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_3_0		FM(VI1_CLK)			FM(MSIOF1_RXD)		F_(0, 0)	FM(CS0_N)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_7_4		FM(VI1_CLKENB)			FM(MSIOF1_TXD)		F_(0, 0)	FM(D0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_11_8	FM(VI1_HSYNC_N)			FM(MSIOF1_SCK)		F_(0, 0)	FM(D1)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_15_12	FM(VI1_VSYNC_N)			FM(MSIOF1_SYNC)		F_(0, 0)	FM(D2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_19_16	FM(VI1_DATA0)			FM(MSIOF1_SS1)		F_(0, 0)	FM(D3)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_23_20	FM(VI1_DATA1)			FM(MSIOF1_SS2)		F_(0, 0)	FM(D4)		FM(MMC_CMD)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24	FM(VI1_DATA2)			FM(CANFD0_TX_B)		F_(0, 0)	FM(D5)		FM(MMC_D0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_31_28	FM(VI1_DATA3)			FM(CANFD0_RX_B)		F_(0, 0)	FM(D6)		FM(MMC_D1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_3_0		FM(VI1_DATA4)			FM(CANFD_CLK_B)		F_(0, 0)	FM(D7)		FM(MMC_D2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4		FM(VI1_DATA5)			F_(0, 0)		FM(SCK4)	FM(D8)		FM(MMC_D3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_11_8	FM(VI1_DATA6)			F_(0, 0)		FM(RX4)		FM(D9)		FM(MMC_CLK)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_15_12	FM(VI1_DATA7)			F_(0, 0)		FM(TX4)		FM(D10)		FM(MMC_D4)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_19_16	FM(VI1_DATA8)			F_(0, 0)		FM(CTS4_N)	FM(D11)		FM(MMC_D5)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_23_20	FM(VI1_DATA9)			F_(0, 0)		FM(RTS4_N)	FM(D12)		FM(MMC_D6)		FM(SCL3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_27_24	FM(VI1_DATA10)			F_(0, 0)		F_(0, 0)	FM(D13)		FM(MMC_D7)		FM(SDA3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_31_28	FM(VI1_DATA11)			FM(SCL4)		FM(IRQ4)	FM(D14)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_3_0		FM(VI1_FIELD)			FM(SDA4)		FM(IRQ5)	FM(D15)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_7_4		FM(SCL0)			FM(DU_DR0)		FM(TPU0TO0)	FM(CLKOUT)	F_(0, 0)		FM(MSIOF0_RXD)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_11_8	FM(SDA0)			FM(DU_DR1)		FM(TPU0TO1)	FM(BS_N)	FM(SCK0)		FM(MSIOF0_TXD)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_15_12	FM(SCL1)			FM(DU_DG0)		FM(TPU0TO2)	FM(RD_N)	FM(CTS0_N)		FM(MSIOF0_SCK)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_19_16	FM(SDA1)			FM(DU_DG1)		FM(TPU0TO3)	FM(WE0_N)	FM(RTS0_N)		FM(MSIOF0_SYNC)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_23_20	FM(SCL2)			FM(DU_DB0)		FM(TCLK1_A)	FM(WE1_N)	FM(RX0)			FM(MSIOF0_SS1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_27_24	FM(SDA2)			FM(DU_DB1)		FM(TCLK2_A)	FM(EX_WAIT0)	FM(TX0)			FM(MSIOF0_SS2)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_31_28	FM(AVB0_AVTP_CAPTURE)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(FSCLKST2_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_3_0		FM(CANFD0_TX_A)			FM(FXR_TXDA)		FM(PWM0_B)	FM(DU_DISP)	FM(FSCLKST2_N_C)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_7_4		FM(CANFD0_RX_A)			FM(RXDA_EXTFXR)		FM(PWM1_B)	FM(DU_CDE)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_11_8	FM(CANFD1_TX)			FM(FXR_TXDB)		FM(PWM2_B)	FM(TCLK1_B)	FM(TX1_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_15_12	FM(CANFD1_RX)			FM(RXDB_EXTFXR)		FM(PWM3_B)	FM(TCLK2_B)	FM(RX1_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_19_16	FM(CANFD_CLK_A)			FM(CLK_EXTFXR)		FM(PWM4_B)	FM(SPEEDIN_B)	FM(SCIF_CLK_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20	FM(DIGRF_CLKIN)			FM(DIGRF_CLKEN_IN)	F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_27_24	FM(DIGRF_CLKOUT)		FM(DIGRF_CLKEN_OUT)	F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_31_28	F_(0, 0)			F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0)
+/* IPSRx */		/* 0 */				/* 1 */			/* 2 */			/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
+#define IP0_3_0		FM(DU_DR2)			FM(SCK4)		FM(GETHER_RMII_CRS_DV)	FM(A0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_7_4		FM(DU_DR3)			FM(RX4)			FM(GETHER_RMII_RX_ER)	FM(A1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_11_8	FM(DU_DR4)			FM(TX4)			FM(GETHER_RMII_RXD0)	FM(A2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_15_12	FM(DU_DR5)			FM(CTS4_N)		FM(GETHER_RMII_RXD1)	FM(A3)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_19_16	FM(DU_DR6)			FM(RTS4_N)		FM(GETHER_RMII_TXD_EN)	FM(A4)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_23_20	FM(DU_DR7)			F_(0, 0)		FM(GETHER_RMII_TXD0)	FM(A5)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24	FM(DU_DG2)			F_(0, 0)		FM(GETHER_RMII_TXD1)	FM(A6)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28	FM(DU_DG3)			FM(CPG_CPCKOUT)		FM(GETHER_RMII_REFCLK)	FM(A7)		FM(PWMFSW0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_3_0		FM(DU_DG4)			FM(SCL5)		F_(0, 0)		FM(A8)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_7_4		FM(DU_DG5)			FM(SDA5)		FM(GETHER_MDC_B)	FM(A9)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8	FM(DU_DG6)			FM(SCIF_CLK_A)		FM(GETHER_MDIO_B)	FM(A10)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_15_12	FM(DU_DG7)			FM(HRX0_A)		F_(0, 0)		FM(A11)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_19_16	FM(DU_DB2)			FM(HSCK0_A)		F_(0, 0)		FM(A12)		FM(IRQ1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_23_20	FM(DU_DB3)			FM(HRTS0_N_A)		F_(0, 0)		FM(A13)		FM(IRQ2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_27_24	FM(DU_DB4)			FM(HCTS0_N_A)		F_(0, 0)		FM(A14)		FM(IRQ3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_31_28	FM(DU_DB5)			FM(HTX0_A)		FM(PWM0_A)		FM(A15)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_3_0		FM(DU_DB6)			FM(MSIOF3_RXD)		F_(0, 0)		FM(A16)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_7_4		FM(DU_DB7)			FM(MSIOF3_TXD)		F_(0, 0)		FM(A17)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_11_8	FM(DU_DOTCLKOUT)		FM(MSIOF3_SS1)		FM(GETHER_LINK_B)	FM(A18)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_15_12	FM(DU_EXHSYNC_DU_HSYNC)		FM(MSIOF3_SS2)		FM(GETHER_PHY_INT_B)	FM(A19)		FM(FXR_TXENA_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_19_16	FM(DU_EXVSYNC_DU_VSYNC)		FM(MSIOF3_SCK)		F_(0, 0)		F_(0, 0)	FM(FXR_TXENB_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20	FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(MSIOF3_SYNC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24	FM(IRQ0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_31_28	FM(VI0_CLK)			FM(MSIOF2_SCK)		FM(SCK3)		F_(0, 0)	FM(HSCK3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_3_0		FM(VI0_CLKENB)			FM(MSIOF2_RXD)		FM(RX3)			FM(RD_WR_N)	FM(HCTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_7_4		FM(VI0_HSYNC_N)			FM(MSIOF2_TXD)		FM(TX3)			F_(0, 0)	FM(HRTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_11_8	FM(VI0_VSYNC_N)			FM(MSIOF2_SYNC)		FM(CTS3_N)		F_(0, 0)	FM(HTX3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12	FM(VI0_DATA0)			FM(MSIOF2_SS1)		FM(RTS3_N)		F_(0, 0)	FM(HRX3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_19_16	FM(VI0_DATA1)			FM(MSIOF2_SS2)		FM(SCK1)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_23_20	FM(VI0_DATA2)			FM(AVB_AVTP_PPS)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_27_24	FM(VI0_DATA3)			FM(HSCK1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_31_28	FM(VI0_DATA4)			FM(HRTS1_N)		FM(RX1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_3_0		FM(VI0_DATA5)			FM(HCTS1_N)		FM(TX1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_7_4		FM(VI0_DATA6)			FM(HTX1)		FM(CTS1_N)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_11_8	FM(VI0_DATA7)			FM(HRX1)		FM(RTS1_N)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_15_12	FM(VI0_DATA8)			FM(HSCK2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_19_16	FM(VI0_DATA9)			FM(HCTS2_N)		FM(PWM1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_23_20	FM(VI0_DATA10)			FM(HRTS2_N)		FM(PWM2_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_27_24	FM(VI0_DATA11)			FM(HTX2)		FM(PWM3_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_31_28	FM(VI0_FIELD)			FM(HRX2)		FM(PWM4_A)		FM(CS1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_3_0		FM(VI1_CLK)			FM(MSIOF1_RXD)		F_(0, 0)		FM(CS0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_7_4		FM(VI1_CLKENB)			FM(MSIOF1_TXD)		F_(0, 0)		FM(D0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_11_8	FM(VI1_HSYNC_N)			FM(MSIOF1_SCK)		F_(0, 0)		FM(D1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_15_12	FM(VI1_VSYNC_N)			FM(MSIOF1_SYNC)		F_(0, 0)		FM(D2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_19_16	FM(VI1_DATA0)			FM(MSIOF1_SS1)		F_(0, 0)		FM(D3)		FM(MMC_WP)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_23_20	FM(VI1_DATA1)			FM(MSIOF1_SS2)		F_(0, 0)		FM(D4)		FM(MMC_CD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24	FM(VI1_DATA2)			FM(CANFD0_TX_B)		F_(0, 0)		FM(D5)		FM(MMC_DS)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_31_28	FM(VI1_DATA3)			FM(CANFD0_RX_B)		F_(0, 0)		FM(D6)		FM(MMC_CMD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_3_0		FM(VI1_DATA4)			FM(CANFD_CLK_B)		F_(0, 0)		FM(D7)		FM(MMC_D0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4		FM(VI1_DATA5)			F_(0, 0)		F_(0, 0)		FM(D8)		FM(MMC_D1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_11_8	FM(VI1_DATA6)			F_(0, 0)		F_(0, 0)		FM(D9)		FM(MMC_D2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_15_12	FM(VI1_DATA7)			F_(0, 0)		F_(0, 0)		FM(D10)		FM(MMC_D3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_19_16	FM(VI1_DATA8)			F_(0, 0)		F_(0, 0)		FM(D11)		FM(MMC_CLK)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_23_20	FM(VI1_DATA9)			FM(TCLK1_A)		F_(0, 0)		FM(D12)		FM(MMC_D4)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_27_24	FM(VI1_DATA10)			FM(TCLK2_A)		F_(0, 0)		FM(D13)		FM(MMC_D5)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_31_28	FM(VI1_DATA11)			FM(SCL4)		F_(0, 0)		FM(D14)		FM(MMC_D6)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_3_0		FM(VI1_FIELD)			FM(SDA4)		F_(0, 0)		FM(D15)		FM(MMC_D7)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_7_4		FM(SCL0)			F_(0, 0)		F_(0, 0)		FM(CLKOUT)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_11_8	FM(SDA0)			F_(0, 0)		F_(0, 0)		FM(BS_N)	FM(SCK0)	FM(HSCK0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_15_12	FM(SCL1)			F_(0, 0)		FM(TPU0TO2)		FM(RD_N)	FM(CTS0_N)	FM(HCTS0_N_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_19_16	FM(SDA1)			F_(0, 0)		FM(TPU0TO3)		FM(WE0_N)	FM(RTS0_N)	FM(HRTS0_N_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_23_20	FM(SCL2)			F_(0, 0)		F_(0, 0)		FM(WE1_N)	FM(RX0)		FM(HRX0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_27_24	FM(SDA2)			F_(0, 0)		F_(0, 0)		FM(EX_WAIT0)	FM(TX0)		FM(HTX0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_31_28	FM(AVB_AVTP_MATCH)		FM(TPU0TO0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_3_0		FM(AVB_AVTP_CAPTURE)		FM(TPU0TO1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_7_4		FM(CANFD0_TX_A)			FM(FXR_TXDA)		FM(PWM0_B)		FM(DU_DISP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_11_8	FM(CANFD0_RX_A)			FM(RXDA_EXTFXR)		FM(PWM1_B)		FM(DU_CDE)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_15_12	FM(CANFD1_TX)			FM(FXR_TXDB)		FM(PWM2_B)		FM(TCLK1_B)	FM(TX1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_19_16	FM(CANFD1_RX)			FM(RXDB_EXTFXR)		FM(PWM3_B)		FM(TCLK2_B)	FM(RX1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20	FM(CANFD_CLK_A) 		FM(CLK_EXTFXR)		FM(PWM4_B)		FM(SPEEDIN_B)	FM(SCIF_CLK_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_27_24	FM(DIGRF_CLKIN)			FM(DIGRF_CLKEN_IN)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_31_28	FM(DIGRF_CLKOUT)		FM(DIGRF_CLKEN_OUT)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_3_0		FM(IRQ4)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA12)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_7_4 	FM(IRQ5)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA13)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_11_8	FM(MSIOF0_RXD)			FM(DU_DR0)		F_(0, 0)		FM(VI0_DATA14)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_15_12	FM(MSIOF0_TXD)			FM(DU_DR1)		F_(0, 0)		FM(VI0_DATA15)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_19_16	FM(MSIOF0_SCK)			FM(DU_DG0)		F_(0, 0)		FM(VI0_DATA16)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_23_20	FM(MSIOF0_SYNC)			FM(DU_DG1)		F_(0, 0)		FM(VI0_DATA17)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_27_24	FM(MSIOF0_SS1)			FM(DU_DB0)		FM(TCLK3)		FM(VI0_DATA18)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_31_28	FM(MSIOF0_SS2)			FM(DU_DB1)		FM(TCLK4)		FM(VI0_DATA19)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_3_0	FM(SCL3)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA20)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_7_4	FM(SDA3)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA21)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_11_8	FM(FSO_CFE_0_N)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA22)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_15_12	FM(FSO_CFE_1_N)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA23)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_19_16	FM(FSO_TOE_N)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_23_20	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_27_24	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_31_28	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 #define PINMUX_GPSR	\
 \
-		GPSR1_27 \
-		GPSR1_26 \
-		GPSR1_25 \
-		GPSR1_24 \
-		GPSR1_23 \
-		GPSR1_22 \
-GPSR0_21	GPSR1_21 \
-GPSR0_20	GPSR1_20 \
-GPSR0_19	GPSR1_19 \
-GPSR0_18	GPSR1_18 \
-GPSR0_17	GPSR1_17 \
-GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16 \
-GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15 \
-GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14			GPSR5_14 \
-GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13			GPSR5_13 \
-GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12			GPSR5_12 \
-GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11			GPSR5_11 \
-GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10			GPSR5_10 \
-GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9				GPSR5_9 \
-GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8				GPSR5_8 \
-GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7				GPSR5_7 \
-GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6				GPSR5_6 \
+				GPSR2_29 \
+				GPSR2_28 \
+		GPSR1_27	GPSR2_27 \
+		GPSR1_26	GPSR2_26 \
+		GPSR1_25	GPSR2_25 \
+		GPSR1_24	GPSR2_24			GPSR4_24 \
+		GPSR1_23	GPSR2_23			GPSR4_23 \
+		GPSR1_22	GPSR2_22			GPSR4_22 \
+GPSR0_21	GPSR1_21	GPSR2_21			GPSR4_21 \
+GPSR0_20	GPSR1_20	GPSR2_20			GPSR4_20 \
+GPSR0_19	GPSR1_19	GPSR2_19			GPSR4_19 \
+GPSR0_18	GPSR1_18	GPSR2_18			GPSR4_18 \
+GPSR0_17	GPSR1_17	GPSR2_17			GPSR4_17 \
+GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16	GPSR4_16 \
+GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15	GPSR4_15 \
+GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14 \
+GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13 \
+GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12 \
+GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11 \
+GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10 \
+GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9 \
+GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8 \
+GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7 \
+GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6 \
 GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5 \
 GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4 \
 GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3 \
···
 FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
 FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
 \
-FM(IP8_3_0)	IP8_3_0 \
-FM(IP8_7_4)	IP8_7_4 \
-FM(IP8_11_8)	IP8_11_8 \
-FM(IP8_15_12)	IP8_15_12 \
-FM(IP8_19_16)	IP8_19_16 \
-FM(IP8_23_20)	IP8_23_20 \
-FM(IP8_27_24)	IP8_27_24 \
-FM(IP8_31_28)	IP8_31_28
+FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0 \
+FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4 \
+FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8 \
+FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12 \
+FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16 \
+FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20 \
+FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24 \
+FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28
 
 /* MOD_SEL0 */		/* 0 */			/* 1 */
-#define MOD_SEL0_11	FM(SEL_I2C3_0)		FM(SEL_I2C3_1)
-#define MOD_SEL0_10	FM(SEL_HSCIF0_0)	FM(SEL_HSCIF0_1)
-#define MOD_SEL0_9	FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
-#define MOD_SEL0_8	FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
-#define MOD_SEL0_7	FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
-#define MOD_SEL0_6	FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
-#define MOD_SEL0_5	FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
-#define MOD_SEL0_4	FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
-#define MOD_SEL0_3	FM(SEL_PWM0_0)		FM(SEL_PWM0_1)
-#define MOD_SEL0_2	FM(SEL_RFSO_0)		FM(SEL_RFSO_1)
-#define MOD_SEL0_1	FM(SEL_RSP_0)		FM(SEL_RSP_1)
+#define MOD_SEL0_11	FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
+#define MOD_SEL0_10	FM(SEL_GETHER_0)	FM(SEL_GETHER_1)
+#define MOD_SEL0_9	FM(SEL_HSCIF0_0)	FM(SEL_HSCIF0_1)
+#define MOD_SEL0_8	FM(SEL_PWM0_0)		FM(SEL_PWM0_1)
+#define MOD_SEL0_7	FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
+#define MOD_SEL0_6	FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
+#define MOD_SEL0_5	FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
+#define MOD_SEL0_4	FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
+#define MOD_SEL0_2	FM(SEL_RSP_0)		FM(SEL_RSP_1)
+#define MOD_SEL0_1	FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
 #define MOD_SEL0_0	FM(SEL_TMU_0)		FM(SEL_TMU_1)
 
 #define PINMUX_MOD_SELS \
···
 MOD_SEL0_6 \
 MOD_SEL0_5 \
 MOD_SEL0_4 \
-MOD_SEL0_3 \
 MOD_SEL0_2 \
 MOD_SEL0_1 \
 MOD_SEL0_0
···
 static const u16 pinmux_data[] = {
 	PINMUX_DATA_GP_ALL(),
 
-	PINMUX_SINGLE(AVB0_RX_CTL),
-	PINMUX_SINGLE(AVB0_RXC),
-	PINMUX_SINGLE(AVB0_RD0),
-	PINMUX_SINGLE(AVB0_RD1),
-	PINMUX_SINGLE(AVB0_RD2),
-	PINMUX_SINGLE(AVB0_RD3),
-	PINMUX_SINGLE(AVB0_TX_CTL),
-	PINMUX_SINGLE(AVB0_TXC),
-	PINMUX_SINGLE(AVB0_TD0),
-	PINMUX_SINGLE(AVB0_TD1),
-	PINMUX_SINGLE(AVB0_TD2),
-	PINMUX_SINGLE(AVB0_TD3),
-	PINMUX_SINGLE(AVB0_TXCREFCLK),
-	PINMUX_SINGLE(AVB0_MDIO),
-	PINMUX_SINGLE(AVB0_MDC),
-	PINMUX_SINGLE(AVB0_MAGIC),
-	PINMUX_SINGLE(AVB0_PHY_INT),
-	PINMUX_SINGLE(AVB0_LINK),
-	PINMUX_SINGLE(AVB0_AVTP_MATCH),
+	PINMUX_SINGLE(AVB_RX_CTL),
+	PINMUX_SINGLE(AVB_RXC),
+	PINMUX_SINGLE(AVB_RD0),
+	PINMUX_SINGLE(AVB_RD1),
+	PINMUX_SINGLE(AVB_RD2),
+	PINMUX_SINGLE(AVB_RD3),
+	PINMUX_SINGLE(AVB_TX_CTL),
+	PINMUX_SINGLE(AVB_TXC),
+	PINMUX_SINGLE(AVB_TD0),
+	PINMUX_SINGLE(AVB_TD1),
+	PINMUX_SINGLE(AVB_TD2),
+	PINMUX_SINGLE(AVB_TD3),
+	PINMUX_SINGLE(AVB_TXCREFCLK),
+	PINMUX_SINGLE(AVB_MDIO),
+	PINMUX_SINGLE(AVB_MDC),
+	PINMUX_SINGLE(AVB_MAGIC),
+	PINMUX_SINGLE(AVB_PHY_INT),
+	PINMUX_SINGLE(AVB_LINK),
+
+	PINMUX_SINGLE(GETHER_RX_CTL),
+	PINMUX_SINGLE(GETHER_RXC),
+	PINMUX_SINGLE(GETHER_RD0),
+	PINMUX_SINGLE(GETHER_RD1),
+	PINMUX_SINGLE(GETHER_RD2),
+	PINMUX_SINGLE(GETHER_RD3),
+	PINMUX_SINGLE(GETHER_TX_CTL),
+	PINMUX_SINGLE(GETHER_TXC),
+	PINMUX_SINGLE(GETHER_TD0),
+	PINMUX_SINGLE(GETHER_TD1),
+	PINMUX_SINGLE(GETHER_TD2),
+	PINMUX_SINGLE(GETHER_TD3),
+	PINMUX_SINGLE(GETHER_TXCREFCLK),
+	PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
+	PINMUX_SINGLE(GETHER_MDIO_A),
+	PINMUX_SINGLE(GETHER_MDC_A),
+	PINMUX_SINGLE(GETHER_MAGIC),
+	PINMUX_SINGLE(GETHER_PHY_INT_A),
+	PINMUX_SINGLE(GETHER_LINK_A),
 
 	PINMUX_SINGLE(QSPI0_SPCLK),
 	PINMUX_SINGLE(QSPI0_MOSI_IO0),
···
 
 	/* IPSR0 */
 	PINMUX_IPSR_GPSR(IP0_3_0,	DU_DR2),
-	PINMUX_IPSR_GPSR(IP0_3_0,	HSCK0),
+	PINMUX_IPSR_GPSR(IP0_3_0,	SCK4),
+	PINMUX_IPSR_GPSR(IP0_3_0,	GETHER_RMII_CRS_DV),
 	PINMUX_IPSR_GPSR(IP0_3_0,	A0),
 
 	PINMUX_IPSR_GPSR(IP0_7_4,	DU_DR3),
-	PINMUX_IPSR_GPSR(IP0_7_4,	HRTS0_N),
+	PINMUX_IPSR_GPSR(IP0_7_4,	RX4),
+	PINMUX_IPSR_GPSR(IP0_7_4,	GETHER_RMII_RX_ER),
 	PINMUX_IPSR_GPSR(IP0_7_4,	A1),
 
 	PINMUX_IPSR_GPSR(IP0_11_8,	DU_DR4),
-	PINMUX_IPSR_GPSR(IP0_11_8,	HCTS0_N),
+	PINMUX_IPSR_GPSR(IP0_11_8,	TX4),
+	PINMUX_IPSR_GPSR(IP0_11_8,	GETHER_RMII_RXD0),
 	PINMUX_IPSR_GPSR(IP0_11_8,	A2),
 
 	PINMUX_IPSR_GPSR(IP0_15_12,	DU_DR5),
-	PINMUX_IPSR_GPSR(IP0_15_12,	HTX0),
+	PINMUX_IPSR_GPSR(IP0_15_12,	CTS4_N),
+	PINMUX_IPSR_GPSR(IP0_15_12,	GETHER_RMII_RXD1),
 	PINMUX_IPSR_GPSR(IP0_15_12,	A3),
 
 	PINMUX_IPSR_GPSR(IP0_19_16,	DU_DR6),
-	PINMUX_IPSR_GPSR(IP0_19_16,	MSIOF3_RXD),
+	PINMUX_IPSR_GPSR(IP0_19_16,	RTS4_N),
+	PINMUX_IPSR_GPSR(IP0_19_16,	GETHER_RMII_TXD_EN),
 	PINMUX_IPSR_GPSR(IP0_19_16,	A4),
 
 	PINMUX_IPSR_GPSR(IP0_23_20,	DU_DR7),
-	PINMUX_IPSR_GPSR(IP0_23_20,	MSIOF3_TXD),
+	PINMUX_IPSR_GPSR(IP0_23_20,	GETHER_RMII_TXD0),
 	PINMUX_IPSR_GPSR(IP0_23_20,	A5),
 
 	PINMUX_IPSR_GPSR(IP0_27_24,	DU_DG2),
-	PINMUX_IPSR_GPSR(IP0_27_24,	MSIOF3_SS1),
+	PINMUX_IPSR_GPSR(IP0_27_24,	GETHER_RMII_TXD1),
 	PINMUX_IPSR_GPSR(IP0_27_24,	A6),
 
 	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DG3),
-	PINMUX_IPSR_GPSR(IP0_31_28,	MSIOF3_SS2),
+	PINMUX_IPSR_GPSR(IP0_31_28,	CPG_CPCKOUT),
+	PINMUX_IPSR_GPSR(IP0_31_28,	GETHER_RMII_REFCLK),
 	PINMUX_IPSR_GPSR(IP0_31_28,	A7),
 	PINMUX_IPSR_GPSR(IP0_31_28,	PWMFSW0),
 
 	/* IPSR1 */
 	PINMUX_IPSR_GPSR(IP1_3_0,	DU_DG4),
+	PINMUX_IPSR_GPSR(IP1_3_0,	SCL5),
 	PINMUX_IPSR_GPSR(IP1_3_0,	A8),
-	PINMUX_IPSR_MSEL(IP1_3_0,	FSO_CFE_0_N_A,	SEL_RFSO_0),
 
 	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DG5),
+	PINMUX_IPSR_GPSR(IP1_7_4,	SDA5),
+	PINMUX_IPSR_MSEL(IP1_7_4,	GETHER_MDC_B, SEL_GETHER_1),
 	PINMUX_IPSR_GPSR(IP1_7_4,	A9),
-	PINMUX_IPSR_MSEL(IP1_7_4,	FSO_CFE_1_N_A,	SEL_RFSO_0),
 
 	PINMUX_IPSR_GPSR(IP1_11_8,	DU_DG6),
+	PINMUX_IPSR_MSEL(IP1_11_8,	SCIF_CLK_A, SEL_HSCIF0_0),
+	PINMUX_IPSR_MSEL(IP1_11_8,	GETHER_MDIO_B, SEL_GETHER_1),
 	PINMUX_IPSR_GPSR(IP1_11_8,	A10),
-	PINMUX_IPSR_MSEL(IP1_11_8,	FSO_TOE_N_A,	SEL_RFSO_0),
 
 	PINMUX_IPSR_GPSR(IP1_15_12,	DU_DG7),
+	PINMUX_IPSR_MSEL(IP1_15_12,	HRX0_A, SEL_HSCIF0_0),
 	PINMUX_IPSR_GPSR(IP1_15_12,	A11),
-	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ1),
 
 	PINMUX_IPSR_GPSR(IP1_19_16,	DU_DB2),
+	PINMUX_IPSR_MSEL(IP1_19_16,	HSCK0_A, SEL_HSCIF0_0),
 	PINMUX_IPSR_GPSR(IP1_19_16,	A12),
-	PINMUX_IPSR_GPSR(IP1_19_16,	IRQ2),
+	PINMUX_IPSR_GPSR(IP1_19_16,	IRQ1),
 
 	PINMUX_IPSR_GPSR(IP1_23_20,	DU_DB3),
+	PINMUX_IPSR_MSEL(IP1_23_20,	HRTS0_N_A, SEL_HSCIF0_0),
 	PINMUX_IPSR_GPSR(IP1_23_20,	A13),
-	PINMUX_IPSR_GPSR(IP1_23_20,	FXR_CLKOUT1),
+	PINMUX_IPSR_GPSR(IP1_23_20,	IRQ2),
 
 	PINMUX_IPSR_GPSR(IP1_27_24,	DU_DB4),
+	PINMUX_IPSR_MSEL(IP1_27_24,	HCTS0_N_A, SEL_HSCIF0_0),
 	PINMUX_IPSR_GPSR(IP1_27_24,	A14),
-	PINMUX_IPSR_GPSR(IP1_27_24,	FXR_CLKOUT2),
+	PINMUX_IPSR_GPSR(IP1_27_24,	IRQ3),
 
 	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB5),
+	PINMUX_IPSR_MSEL(IP1_31_28,	HTX0_A, SEL_HSCIF0_0),
+	PINMUX_IPSR_MSEL(IP1_31_28,	PWM0_A, SEL_PWM0_0),
 	PINMUX_IPSR_GPSR(IP1_31_28,	A15),
-	PINMUX_IPSR_GPSR(IP1_31_28,	FXR_TXENA_N),
 
 	/* IPSR2 */
 	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB6),
+	PINMUX_IPSR_GPSR(IP2_3_0,	MSIOF3_RXD),
 	PINMUX_IPSR_GPSR(IP2_3_0,	A16),
-	PINMUX_IPSR_GPSR(IP2_3_0,	FXR_TXENB_N),
 
 	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB7),
+	PINMUX_IPSR_GPSR(IP2_7_4,	MSIOF3_TXD),
 	PINMUX_IPSR_GPSR(IP2_7_4,	A17),
 
 	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DOTCLKOUT),
-	PINMUX_IPSR_MSEL(IP2_11_8,	SCIF_CLK_A,	SEL_HSCIF0_0),
+	PINMUX_IPSR_GPSR(IP2_11_8,	MSIOF3_SS1),
+	PINMUX_IPSR_MSEL(IP2_11_8,	GETHER_LINK_B, SEL_GETHER_1),
 	PINMUX_IPSR_GPSR(IP2_11_8,	A18),
 
 	PINMUX_IPSR_GPSR(IP2_15_12,	DU_EXHSYNC_DU_HSYNC),
-	PINMUX_IPSR_GPSR(IP2_15_12,	HRX0),
+	PINMUX_IPSR_GPSR(IP2_15_12,	MSIOF3_SS2),
+	PINMUX_IPSR_MSEL(IP2_15_12,	GETHER_PHY_INT_B, SEL_GETHER_1),
 	PINMUX_IPSR_GPSR(IP2_15_12,	A19),
-	PINMUX_IPSR_GPSR(IP2_15_12,	IRQ3),
+	PINMUX_IPSR_GPSR(IP2_15_12,	FXR_TXENA_N),
 
 	PINMUX_IPSR_GPSR(IP2_19_16,	DU_EXVSYNC_DU_VSYNC),
 	PINMUX_IPSR_GPSR(IP2_19_16,	MSIOF3_SCK),
+	PINMUX_IPSR_GPSR(IP2_19_16,	FXR_TXENB_N),
 
 	PINMUX_IPSR_GPSR(IP2_23_20,	DU_EXODDF_DU_ODDF_DISP_CDE),
 	PINMUX_IPSR_GPSR(IP2_23_20,	MSIOF3_SYNC),
···
 	PINMUX_IPSR_GPSR(IP3_19_16,	VI0_DATA1),
 	PINMUX_IPSR_GPSR(IP3_19_16,	MSIOF2_SS2),
 	PINMUX_IPSR_GPSR(IP3_19_16,	SCK1),
-	PINMUX_IPSR_MSEL(IP3_19_16,	SPEEDIN_A,	SEL_RSP_0),
+	PINMUX_IPSR_MSEL(IP3_19_16,	SPEEDIN_A, SEL_RSP_0),
 
 	PINMUX_IPSR_GPSR(IP3_23_20,	VI0_DATA2),
-	PINMUX_IPSR_GPSR(IP3_23_20,	AVB0_AVTP_PPS),
-	PINMUX_IPSR_MSEL(IP3_23_20,	SDA3_A,		SEL_I2C3_0),
+	PINMUX_IPSR_GPSR(IP3_23_20,	AVB_AVTP_PPS),
 
 	PINMUX_IPSR_GPSR(IP3_27_24,	VI0_DATA3),
 	PINMUX_IPSR_GPSR(IP3_27_24,	HSCK1),
-	PINMUX_IPSR_MSEL(IP3_27_24,	SCL3_A,		SEL_I2C3_0),
 
 	PINMUX_IPSR_GPSR(IP3_31_28,	VI0_DATA4),
 	PINMUX_IPSR_GPSR(IP3_31_28,	HRTS1_N),
-	PINMUX_IPSR_MSEL(IP3_31_28,	RX1_A,	SEL_SCIF1_0),
+	PINMUX_IPSR_MSEL(IP3_31_28,	RX1_A, SEL_SCIF1_0),
 
 	/* IPSR4 */
 	PINMUX_IPSR_GPSR(IP4_3_0,	VI0_DATA5),
 	PINMUX_IPSR_GPSR(IP4_3_0,	HCTS1_N),
-	PINMUX_IPSR_MSEL(IP4_3_0,	TX1_A,	SEL_SCIF1_0),
+	PINMUX_IPSR_MSEL(IP4_3_0,	TX1_A, SEL_SCIF1_0),
 
 	PINMUX_IPSR_GPSR(IP4_7_4,	VI0_DATA6),
 	PINMUX_IPSR_GPSR(IP4_7_4,	HTX1),
···
 
 	PINMUX_IPSR_GPSR(IP4_15_12,	VI0_DATA8),
 	PINMUX_IPSR_GPSR(IP4_15_12,	HSCK2),
-	PINMUX_IPSR_MSEL(IP4_15_12,	PWM0_A,	SEL_PWM0_0),
 
 	PINMUX_IPSR_GPSR(IP4_19_16,	VI0_DATA9),
 	PINMUX_IPSR_GPSR(IP4_19_16,	HCTS2_N),
-	PINMUX_IPSR_MSEL(IP4_19_16,	PWM1_A,	SEL_PWM1_0),
-	PINMUX_IPSR_MSEL(IP4_19_16,	FSO_CFE_0_N_B,	SEL_RFSO_1),
+	PINMUX_IPSR_MSEL(IP4_19_16,	PWM1_A, SEL_PWM1_0),
 
 	PINMUX_IPSR_GPSR(IP4_23_20,	VI0_DATA10),
 	PINMUX_IPSR_GPSR(IP4_23_20,	HRTS2_N),
-	PINMUX_IPSR_MSEL(IP4_23_20,	PWM2_A,	SEL_PWM2_0),
-	PINMUX_IPSR_MSEL(IP4_23_20,	FSO_CFE_1_N_B,	SEL_RFSO_1),
+	PINMUX_IPSR_MSEL(IP4_23_20,	PWM2_A, SEL_PWM2_0),
 
 	PINMUX_IPSR_GPSR(IP4_27_24,	VI0_DATA11),
 	PINMUX_IPSR_GPSR(IP4_27_24,	HTX2),
-	PINMUX_IPSR_MSEL(IP4_27_24,	PWM3_A,	SEL_PWM3_0),
-	PINMUX_IPSR_MSEL(IP4_27_24,	FSO_TOE_N_B,	SEL_RFSO_1),
+	PINMUX_IPSR_MSEL(IP4_27_24,	PWM3_A, SEL_PWM3_0),
 
 	PINMUX_IPSR_GPSR(IP4_31_28,	VI0_FIELD),
 	PINMUX_IPSR_GPSR(IP4_31_28,	HRX2),
-	PINMUX_IPSR_MSEL(IP4_31_28,	PWM4_A,	SEL_PWM4_0),
+	PINMUX_IPSR_MSEL(IP4_31_28,	PWM4_A, SEL_PWM4_0),
 	PINMUX_IPSR_GPSR(IP4_31_28,	CS1_N),
-	PINMUX_IPSR_GPSR(IP4_31_28,	FSCLKST2_N_A),
 
 	/* IPSR5 */
 	PINMUX_IPSR_GPSR(IP5_3_0,	VI1_CLK),
···
 	PINMUX_IPSR_GPSR(IP5_19_16,	VI1_DATA0),
 	PINMUX_IPSR_GPSR(IP5_19_16,	MSIOF1_SS1),
 	PINMUX_IPSR_GPSR(IP5_19_16,	D3),
+	PINMUX_IPSR_GPSR(IP5_19_16,	MMC_WP),
 
 	PINMUX_IPSR_GPSR(IP5_23_20,	VI1_DATA1),
 	PINMUX_IPSR_GPSR(IP5_23_20,	MSIOF1_SS2),
 	PINMUX_IPSR_GPSR(IP5_23_20,	D4),
-	PINMUX_IPSR_GPSR(IP5_23_20,	MMC_CMD),
+	PINMUX_IPSR_GPSR(IP5_23_20,	MMC_CD),
 
 	PINMUX_IPSR_GPSR(IP5_27_24,	VI1_DATA2),
-	PINMUX_IPSR_MSEL(IP5_27_24,	CANFD0_TX_B,	SEL_CANFD0_1),
+	PINMUX_IPSR_MSEL(IP5_27_24,	CANFD0_TX_B, SEL_CANFD0_1),
 	PINMUX_IPSR_GPSR(IP5_27_24,	D5),
-	PINMUX_IPSR_GPSR(IP5_27_24,	MMC_D0),
+	PINMUX_IPSR_GPSR(IP5_27_24,	MMC_DS),
 
 	PINMUX_IPSR_GPSR(IP5_31_28,	VI1_DATA3),
-	PINMUX_IPSR_MSEL(IP5_31_28,	CANFD0_RX_B,	SEL_CANFD0_1),
+	PINMUX_IPSR_MSEL(IP5_31_28,	CANFD0_RX_B, SEL_CANFD0_1),
 	PINMUX_IPSR_GPSR(IP5_31_28,	D6),
-	PINMUX_IPSR_GPSR(IP5_31_28,	MMC_D1),
+	PINMUX_IPSR_GPSR(IP5_31_28,	MMC_CMD),
 
 	/* IPSR6 */
 	PINMUX_IPSR_GPSR(IP6_3_0,	VI1_DATA4),
-	PINMUX_IPSR_MSEL(IP6_3_0,	CANFD_CLK_B,	SEL_CANFD0_1),
+	PINMUX_IPSR_MSEL(IP6_3_0,	CANFD_CLK_B, SEL_CANFD0_1),
 	PINMUX_IPSR_GPSR(IP6_3_0,	D7),
-	PINMUX_IPSR_GPSR(IP6_3_0,	MMC_D2),
+	PINMUX_IPSR_GPSR(IP6_3_0,	MMC_D0),
 
 	PINMUX_IPSR_GPSR(IP6_7_4,	VI1_DATA5),
-	PINMUX_IPSR_GPSR(IP6_7_4,	SCK4),
 	PINMUX_IPSR_GPSR(IP6_7_4,	D8),
-	PINMUX_IPSR_GPSR(IP6_7_4,	MMC_D3),
+	PINMUX_IPSR_GPSR(IP6_7_4,	MMC_D1),
 
 	PINMUX_IPSR_GPSR(IP6_11_8,	VI1_DATA6),
-	PINMUX_IPSR_GPSR(IP6_11_8,	RX4),
 	PINMUX_IPSR_GPSR(IP6_11_8,	D9),
-	PINMUX_IPSR_GPSR(IP6_11_8,	MMC_CLK),
+	PINMUX_IPSR_GPSR(IP6_11_8,	MMC_D2),
 
 	PINMUX_IPSR_GPSR(IP6_15_12,	VI1_DATA7),
-	PINMUX_IPSR_GPSR(IP6_15_12,	TX4),
 	PINMUX_IPSR_GPSR(IP6_15_12,	D10),
-	PINMUX_IPSR_GPSR(IP6_15_12,	MMC_D4),
+	PINMUX_IPSR_GPSR(IP6_15_12,	MMC_D3),
 
 	PINMUX_IPSR_GPSR(IP6_19_16,	VI1_DATA8),
-	PINMUX_IPSR_GPSR(IP6_19_16,	CTS4_N),
 	PINMUX_IPSR_GPSR(IP6_19_16,	D11),
-	PINMUX_IPSR_GPSR(IP6_19_16,	MMC_D5),
+	PINMUX_IPSR_GPSR(IP6_19_16,	MMC_CLK),
 
 	PINMUX_IPSR_GPSR(IP6_23_20,	VI1_DATA9),
-	PINMUX_IPSR_GPSR(IP6_23_20,	RTS4_N),
+	PINMUX_IPSR_MSEL(IP6_23_20,	TCLK1_A, SEL_TMU_0),
 	PINMUX_IPSR_GPSR(IP6_23_20,	D12),
-	PINMUX_IPSR_GPSR(IP6_23_20,	MMC_D6),
-	PINMUX_IPSR_MSEL(IP6_23_20,	SCL3_B,	SEL_I2C3_1),
+	PINMUX_IPSR_GPSR(IP6_23_20,	MMC_D4),
 
 	PINMUX_IPSR_GPSR(IP6_27_24,	VI1_DATA10),
+	PINMUX_IPSR_MSEL(IP6_27_24,	TCLK2_A, SEL_TMU_0),
 	PINMUX_IPSR_GPSR(IP6_27_24,	D13),
-	PINMUX_IPSR_GPSR(IP6_27_24,	MMC_D7),
-	PINMUX_IPSR_MSEL(IP6_27_24,	SDA3_B,	SEL_I2C3_1),
+	PINMUX_IPSR_GPSR(IP6_27_24,	MMC_D5),
 
 	PINMUX_IPSR_GPSR(IP6_31_28,	VI1_DATA11),
 	PINMUX_IPSR_GPSR(IP6_31_28,	SCL4),
-	PINMUX_IPSR_GPSR(IP6_31_28,	IRQ4),
 	PINMUX_IPSR_GPSR(IP6_31_28,	D14),
+	PINMUX_IPSR_GPSR(IP6_31_28,	MMC_D6),
 
 	/* IPSR7 */
 	PINMUX_IPSR_GPSR(IP7_3_0,	VI1_FIELD),
 	PINMUX_IPSR_GPSR(IP7_3_0,	SDA4),
-	PINMUX_IPSR_GPSR(IP7_3_0,	IRQ5),
 	PINMUX_IPSR_GPSR(IP7_3_0,	D15),
+	PINMUX_IPSR_GPSR(IP7_3_0,	MMC_D7),
 
 	PINMUX_IPSR_GPSR(IP7_7_4,	SCL0),
-	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR0),
-	PINMUX_IPSR_GPSR(IP7_7_4,	TPU0TO0),
 	PINMUX_IPSR_GPSR(IP7_7_4,	CLKOUT),
-	PINMUX_IPSR_GPSR(IP7_7_4,	MSIOF0_RXD),
 
 	PINMUX_IPSR_GPSR(IP7_11_8,	SDA0),
-	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR1),
-	PINMUX_IPSR_GPSR(IP7_11_8,	TPU0TO1),
 	PINMUX_IPSR_GPSR(IP7_11_8,	BS_N),
 	PINMUX_IPSR_GPSR(IP7_11_8,	SCK0),
-	PINMUX_IPSR_GPSR(IP7_11_8,	MSIOF0_TXD),
+	PINMUX_IPSR_MSEL(IP7_11_8,	HSCK0_B, SEL_HSCIF0_1),
 
 	PINMUX_IPSR_GPSR(IP7_15_12,	SCL1),
-	PINMUX_IPSR_GPSR(IP7_15_12,	DU_DG0),
 	PINMUX_IPSR_GPSR(IP7_15_12,	TPU0TO2),
 	PINMUX_IPSR_GPSR(IP7_15_12,	RD_N),
 	PINMUX_IPSR_GPSR(IP7_15_12,	CTS0_N),
-	PINMUX_IPSR_GPSR(IP7_15_12,	MSIOF0_SCK),
+	PINMUX_IPSR_GPSR(IP7_15_12,	HCTS0_N_B),
 
 	PINMUX_IPSR_GPSR(IP7_19_16,	SDA1),
-	PINMUX_IPSR_GPSR(IP7_19_16,	DU_DG1),
 	PINMUX_IPSR_GPSR(IP7_19_16,	TPU0TO3),
 	PINMUX_IPSR_GPSR(IP7_19_16,	WE0_N),
 	PINMUX_IPSR_GPSR(IP7_19_16,	RTS0_N),
-	PINMUX_IPSR_GPSR(IP7_19_16,	MSIOF0_SYNC),
+	PINMUX_IPSR_MSEL(IP1_23_20,	HRTS0_N_B, SEL_HSCIF0_1),
 
 	PINMUX_IPSR_GPSR(IP7_23_20,	SCL2),
-	PINMUX_IPSR_GPSR(IP7_23_20,	DU_DB0),
-	PINMUX_IPSR_MSEL(IP7_23_20,	TCLK1_A,	SEL_TMU_0),
 	PINMUX_IPSR_GPSR(IP7_23_20,	WE1_N),
 	PINMUX_IPSR_GPSR(IP7_23_20,	RX0),
-	PINMUX_IPSR_GPSR(IP7_23_20,	MSIOF0_SS1),
+	PINMUX_IPSR_MSEL(IP7_23_20,	HRX0_B, SEL_HSCIF0_1),
 
 	PINMUX_IPSR_GPSR(IP7_27_24,	SDA2),
-	PINMUX_IPSR_GPSR(IP7_27_24,	DU_DB1),
-	PINMUX_IPSR_MSEL(IP7_27_24,	TCLK2_A,	SEL_TMU_0),
 	PINMUX_IPSR_GPSR(IP7_27_24,	EX_WAIT0),
 	PINMUX_IPSR_GPSR(IP7_27_24,	TX0),
-	PINMUX_IPSR_GPSR(IP7_27_24,	MSIOF0_SS2),
+	PINMUX_IPSR_MSEL(IP7_27_24,	HTX0_B, SEL_HSCIF0_1),
 
-	PINMUX_IPSR_GPSR(IP7_31_28,	AVB0_AVTP_CAPTURE),
-	PINMUX_IPSR_GPSR(IP7_31_28,	FSCLKST2_N_B),
+	PINMUX_IPSR_GPSR(IP7_31_28,	AVB_AVTP_MATCH),
+	PINMUX_IPSR_GPSR(IP7_31_28,	TPU0TO0),
 
 	/* IPSR8 */
-	PINMUX_IPSR_MSEL(IP8_3_0,	CANFD0_TX_A,	SEL_CANFD0_0),
-	PINMUX_IPSR_GPSR(IP8_3_0,	FXR_TXDA),
-	PINMUX_IPSR_MSEL(IP8_3_0,	PWM0_B,		SEL_PWM0_1),
-	PINMUX_IPSR_GPSR(IP8_3_0,	DU_DISP),
-	PINMUX_IPSR_GPSR(IP8_3_0,	FSCLKST2_N_C),
+	PINMUX_IPSR_GPSR(IP8_3_0,	AVB_AVTP_CAPTURE),
+	PINMUX_IPSR_GPSR(IP8_3_0,	TPU0TO1),
 
-	PINMUX_IPSR_MSEL(IP8_7_4,	CANFD0_RX_A,	SEL_CANFD0_0),
-	PINMUX_IPSR_GPSR(IP8_7_4,	RXDA_EXTFXR),
-	PINMUX_IPSR_MSEL(IP8_7_4,	PWM1_B,		SEL_PWM1_1),
-	PINMUX_IPSR_GPSR(IP8_7_4,	DU_CDE),
+	PINMUX_IPSR_MSEL(IP8_7_4,	CANFD0_TX_A, SEL_CANFD0_0),
+	PINMUX_IPSR_GPSR(IP8_7_4,	FXR_TXDA),
+	PINMUX_IPSR_MSEL(IP8_7_4,	PWM0_B, SEL_PWM0_1),
+	PINMUX_IPSR_GPSR(IP8_7_4,	DU_DISP),
 
-	PINMUX_IPSR_GPSR(IP8_11_8,	CANFD1_TX),
-	PINMUX_IPSR_GPSR(IP8_11_8,	FXR_TXDB),
-	PINMUX_IPSR_MSEL(IP8_11_8,	PWM2_B,		SEL_PWM2_1),
-	PINMUX_IPSR_MSEL(IP8_11_8,	TCLK1_B,	SEL_TMU_1),
-	PINMUX_IPSR_MSEL(IP8_11_8,	TX1_B,		SEL_SCIF1_1),
+	PINMUX_IPSR_MSEL(IP8_11_8,	CANFD0_RX_A, SEL_CANFD0_0),
+	PINMUX_IPSR_GPSR(IP8_11_8,	RXDA_EXTFXR),
+	PINMUX_IPSR_MSEL(IP8_11_8,	PWM1_B, SEL_PWM1_1),
+	PINMUX_IPSR_GPSR(IP8_11_8,	DU_CDE),
 
-	PINMUX_IPSR_GPSR(IP8_15_12,	CANFD1_RX),
-	PINMUX_IPSR_GPSR(IP8_15_12,	RXDB_EXTFXR),
-	PINMUX_IPSR_MSEL(IP8_15_12,	PWM3_B,		SEL_PWM3_1),
-	PINMUX_IPSR_MSEL(IP8_15_12,	TCLK2_B,	SEL_TMU_1),
-	PINMUX_IPSR_MSEL(IP8_15_12,	RX1_B,		SEL_SCIF1_1),
+	PINMUX_IPSR_GPSR(IP8_15_12,	CANFD1_TX),
+	PINMUX_IPSR_GPSR(IP8_15_12,	FXR_TXDB),
+	PINMUX_IPSR_MSEL(IP8_15_12,	PWM2_B, SEL_PWM2_1),
+	PINMUX_IPSR_MSEL(IP8_15_12,	TCLK1_B, SEL_TMU_1),
+	PINMUX_IPSR_MSEL(IP8_15_12,	TX1_B, SEL_SCIF1_1),
 
-	PINMUX_IPSR_MSEL(IP8_19_16,	CANFD_CLK_A,	SEL_CANFD0_0),
-	PINMUX_IPSR_GPSR(IP8_19_16,	CLK_EXTFXR),
-	PINMUX_IPSR_MSEL(IP8_19_16,	PWM4_B,		SEL_PWM4_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	SPEEDIN_B,	SEL_RSP_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	SCIF_CLK_B,	SEL_HSCIF0_1),
+	PINMUX_IPSR_GPSR(IP8_19_16,	CANFD1_RX),
+	PINMUX_IPSR_GPSR(IP8_19_16,	RXDB_EXTFXR),
+	PINMUX_IPSR_MSEL(IP8_19_16,	PWM3_B, SEL_PWM3_1),
+	PINMUX_IPSR_MSEL(IP8_19_16,	TCLK2_B, SEL_TMU_1),
+	PINMUX_IPSR_MSEL(IP8_19_16,	RX1_B, SEL_SCIF1_1),
 
-	PINMUX_IPSR_GPSR(IP8_23_20,	DIGRF_CLKIN),
-	PINMUX_IPSR_GPSR(IP8_23_20,	DIGRF_CLKEN_IN),
+	PINMUX_IPSR_MSEL(IP8_23_20,	CANFD_CLK_A, SEL_CANFD0_0),
+	PINMUX_IPSR_GPSR(IP8_23_20,	CLK_EXTFXR),
+	PINMUX_IPSR_MSEL(IP8_23_20,	PWM4_B, SEL_PWM4_1),
+	PINMUX_IPSR_MSEL(IP8_23_20,	SPEEDIN_B, SEL_RSP_1),
+	PINMUX_IPSR_MSEL(IP8_23_20,	SCIF_CLK_B, SEL_HSCIF0_1),
 
-	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKOUT),
-	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKEN_OUT),
+	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKIN),
+	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKEN_IN),
+
+	PINMUX_IPSR_GPSR(IP8_31_28,	DIGRF_CLKOUT),
+	PINMUX_IPSR_GPSR(IP8_31_28,	DIGRF_CLKEN_OUT),
+
+	/* IPSR9 */
+	PINMUX_IPSR_GPSR(IP9_3_0,	IRQ4),
+	PINMUX_IPSR_GPSR(IP9_3_0,	VI0_DATA12),
+
+	PINMUX_IPSR_GPSR(IP9_7_4,	IRQ5),
+	PINMUX_IPSR_GPSR(IP9_7_4,	VI0_DATA13),
+
+	PINMUX_IPSR_GPSR(IP9_11_8,	MSIOF0_RXD),
+	PINMUX_IPSR_GPSR(IP9_11_8,	DU_DR0),
+	PINMUX_IPSR_GPSR(IP9_11_8,	VI0_DATA14),
+
+	PINMUX_IPSR_GPSR(IP9_15_12,	MSIOF0_TXD),
+	PINMUX_IPSR_GPSR(IP9_15_12,	DU_DR1),
+	PINMUX_IPSR_GPSR(IP9_15_12,	VI0_DATA15),
+
+	PINMUX_IPSR_GPSR(IP9_19_16,	MSIOF0_SCK),
+	PINMUX_IPSR_GPSR(IP9_19_16,	DU_DG0),
+	PINMUX_IPSR_GPSR(IP9_19_16,	VI0_DATA16),
+
+	PINMUX_IPSR_GPSR(IP9_23_20,	MSIOF0_SYNC),
+	PINMUX_IPSR_GPSR(IP9_23_20,	DU_DG1),
+	PINMUX_IPSR_GPSR(IP9_23_20,	VI0_DATA17),
+
+	PINMUX_IPSR_GPSR(IP9_27_24,	MSIOF0_SS1),
+	PINMUX_IPSR_GPSR(IP9_27_24,	DU_DB0),
+	PINMUX_IPSR_GPSR(IP9_27_24,	TCLK3),
+	PINMUX_IPSR_GPSR(IP9_27_24,	VI0_DATA18),
+
+	PINMUX_IPSR_GPSR(IP9_31_28,	MSIOF0_SS2),
+	PINMUX_IPSR_GPSR(IP9_31_28,	DU_DB1),
+	PINMUX_IPSR_GPSR(IP9_31_28,	TCLK4),
+	PINMUX_IPSR_GPSR(IP9_31_28,	VI0_DATA19),
+
+	/* IPSR10 */
+	PINMUX_IPSR_GPSR(IP10_3_0,	SCL3),
+	PINMUX_IPSR_GPSR(IP10_3_0,	VI0_DATA20),
+
+	PINMUX_IPSR_GPSR(IP10_7_4,	SDA3),
+	PINMUX_IPSR_GPSR(IP10_7_4,	VI0_DATA21),
+
+	PINMUX_IPSR_GPSR(IP10_11_8,	FSO_CFE_0_N),
+	PINMUX_IPSR_GPSR(IP10_11_8,	VI0_DATA22),
+
+	PINMUX_IPSR_GPSR(IP10_15_12,	FSO_CFE_1_N),
+	PINMUX_IPSR_GPSR(IP10_15_12,	VI0_DATA23),
+
+	PINMUX_IPSR_GPSR(IP10_19_16,	FSO_TOE_N),
 };
 
 static const struct sh_pfc_pin pinmux_pins[] = {
 	PINMUX_GPIO_GP_ALL(),
 };
 
-/* - AVB0 ------------------------------------------------------------------- */
-static const unsigned int avb0_link_pins[] = {
-	/* AVB0_LINK */
+/* - AVB -------------------------------------------------------------------- */
+static const unsigned int avb_link_pins[] = {
+	/* AVB_LINK */
 	RCAR_GP_PIN(1, 18),
 };
-static const unsigned int avb0_link_mux[] = {
-	AVB0_LINK_MARK,
+static const unsigned int avb_link_mux[] = {
+	AVB_LINK_MARK,
 };
-static const unsigned int avb0_magic_pins[] = {
-	/* AVB0_MAGIC */
+static const unsigned int avb_magic_pins[] = {
+	/* AVB_MAGIC */
 	RCAR_GP_PIN(1, 16),
 };
-static const unsigned int avb0_magic_mux[] = {
-	AVB0_MAGIC_MARK,
+static const unsigned int avb_magic_mux[] = {
+	AVB_MAGIC_MARK,
 };
-static const unsigned int avb0_phy_int_pins[] = {
-	/* AVB0_PHY_INT */
+static const unsigned int avb_phy_int_pins[] = {
+	/* AVB_PHY_INT */
 	RCAR_GP_PIN(1, 17),
 };
-static const unsigned int avb0_phy_int_mux[] = {
-	AVB0_PHY_INT_MARK,
+static const unsigned int avb_phy_int_mux[] = {
+	AVB_PHY_INT_MARK,
 };
-static const unsigned int avb0_mdio_pins[] = {
-	/* AVB0_MDC, AVB0_MDIO */
+static const unsigned int avb_mdio_pins[] = {
+	/* AVB_MDC, AVB_MDIO */
 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
 };
-static const unsigned int avb0_mdio_mux[] = {
-	AVB0_MDC_MARK, AVB0_MDIO_MARK,
+static const unsigned int avb_mdio_mux[] = {
+	AVB_MDC_MARK, AVB_MDIO_MARK,
 };
-static const unsigned int avb0_rgmii_pins[] = {
+static const unsigned int avb_rgmii_pins[] = {
 	/*
-	 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
-	 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
+	 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
+	 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
 	 */
 	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
 	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
···
 	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
 	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
 };
-static const unsigned int avb0_rgmii_mux[] = {
-	AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
-	AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
-	AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
-	AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
+static const unsigned int avb_rgmii_mux[] = {
+	AVB_TX_CTL_MARK, AVB_TXC_MARK,
+	AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
+	AVB_RX_CTL_MARK, AVB_RXC_MARK,
+	AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
 };
-static const unsigned int avb0_txcrefclk_pins[] = {
-	/* AVB0_TXCREFCLK */
+static const unsigned int avb_txcrefclk_pins[] = {
+	/* AVB_TXCREFCLK */
 	RCAR_GP_PIN(1, 13),
 };
-static const unsigned int avb0_txcrefclk_mux[] = {
-	AVB0_TXCREFCLK_MARK,
+static const unsigned int avb_txcrefclk_mux[] = {
+	AVB_TXCREFCLK_MARK,
 };
-static const unsigned int avb0_avtp_pps_pins[] = {
-	/* AVB0_AVTP_PPS */
+static const unsigned int avb_avtp_pps_pins[] = {
+	/* AVB_AVTP_PPS */
 	RCAR_GP_PIN(2, 6),
 };
-static const unsigned int avb0_avtp_pps_mux[] = {
-	AVB0_AVTP_PPS_MARK,
+static const unsigned int avb_avtp_pps_mux[] = {
+	AVB_AVTP_PPS_MARK,
 };
-static const unsigned int avb0_avtp_capture_pins[] = {
-	/* AVB0_AVTP_CAPTURE */
+static const unsigned int avb_avtp_capture_pins[] = {
+	/* AVB_AVTP_CAPTURE */
 	RCAR_GP_PIN(1, 20),
 };
-static const unsigned int avb0_avtp_capture_mux[] = {
-	AVB0_AVTP_CAPTURE_MARK,
+static const unsigned int avb_avtp_capture_mux[] = {
+	AVB_AVTP_CAPTURE_MARK,
 };
-static const unsigned int avb0_avtp_match_pins[] = {
-	/* AVB0_AVTP_MATCH */
+static const unsigned int avb_avtp_match_pins[] = {
+	/* AVB_AVTP_MATCH */
 	RCAR_GP_PIN(1, 19),
 };
-static const unsigned int avb0_avtp_match_mux[] = {
-	AVB0_AVTP_MATCH_MARK,
+static const unsigned int avb_avtp_match_mux[] = {
+	AVB_AVTP_MATCH_MARK,
+};
+
+/* - CANFD0 ----------------------------------------------------------------- */
+static const unsigned int canfd0_data_a_pins[] = {
+	/* CANFD0_TX, CANFD0_RX */
+	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int canfd0_data_a_mux[] = {
+	CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
+};
+static const unsigned int canfd0_data_b_pins[] = {
+	/* CANFD0_TX, CANFD0_RX */
+	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int canfd0_data_b_mux[] = {
+	CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
+};
+
+/* - CANFD1 ----------------------------------------------------------------- */
+static const unsigned int canfd1_data_pins[] = {
+	/* CANFD1_TX, CANFD1_RX */
+	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
+};
+static const unsigned int canfd1_data_mux[] = {
+	CANFD1_TX_MARK, CANFD1_RX_MARK,
 };
 
 /* - CANFD Clock ------------------------------------------------------------ */
···
 	CANFD_CLK_B_MARK,
 };
 
-/* - CANFD0 ----------------------------------------------------------------- */
-static const unsigned int canfd0_data_a_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
-};
-static const unsigned int canfd0_data_a_mux[] = {
-	CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
-};
-static const unsigned int canfd0_data_b_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-};
-static const unsigned int canfd0_data_b_mux[] = {
-	CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
-};
-
-/* - CANFD1 ----------------------------------------------------------------- */
-static const unsigned int canfd1_data_pins[] = {
-	/* TX, RX */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
-};
-static const unsigned int canfd1_data_mux[] = {
-	CANFD1_TX_MARK, CANFD1_RX_MARK,
-};
-
 /* - DU --------------------------------------------------------------------- */
 static const unsigned int du_rgb666_pins[] = {
-	/* R[7:2], G[7:2], B[7:2] */
+	/* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
 	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
···
 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
 	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
 };
+static const unsigned int du_rgb888_pins[] = {
+	/* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
+	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
+	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
+	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
+	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
+	RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
+	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
+	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
+	RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
+};
+static const unsigned int du_rgb888_mux[] = {
+	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
+	DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
+	DU_DR1_MARK, DU_DR0_MARK,
+	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
+	DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
+	DU_DG1_MARK, DU_DG0_MARK,
+	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
+	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
+	DU_DB1_MARK, DU_DB0_MARK,
+};
 static const unsigned int du_clk_out_pins[] = {
-	/* DOTCLKOUT */
+	/* DU_DOTCLKOUT */
 	RCAR_GP_PIN(0, 18),
 };
 static const unsigned int du_clk_out_mux[] = {
 	DU_DOTCLKOUT_MARK,
 };
 static const unsigned int du_sync_pins[] = {
-	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
+	/* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
 	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 };
 static const unsigned int du_sync_mux[] = {
-	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
+	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
 };
 static const unsigned int du_oddf_pins[] = {
-	/* EXODDF/ODDF/DISP/CDE */
+	/* DU_EXODDF/DU_ODDF/DISP/CDE */
 	RCAR_GP_PIN(0, 21),
 };
 static const unsigned int du_oddf_mux[] = {
 	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
 };
 static const unsigned int du_cde_pins[] = {
-	/* CDE */
+	/* DU_CDE */
 	RCAR_GP_PIN(1, 22),
 };
 static const unsigned int du_cde_mux[] = {
 	DU_CDE_MARK,
 };
 static const unsigned int du_disp_pins[] = {
-	/* DISP */
+	/* DU_DISP */
 	RCAR_GP_PIN(1, 21),
 };
 static const unsigned int du_disp_mux[] = {
 	DU_DISP_MARK,
 };
 
+/* - GETHER ----------------------------------------------------------------- */
+static const unsigned int gether_link_a_pins[] = {
+	/* GETHER_LINK */
+	RCAR_GP_PIN(4, 24),
+};
+static const unsigned int gether_link_a_mux[] = {
+	GETHER_LINK_A_MARK,
+};
+static const unsigned int gether_phy_int_a_pins[] = {
+	/* GETHER_PHY_INT */
+	RCAR_GP_PIN(4, 23),
+};
+static const unsigned int gether_phy_int_a_mux[] = {
+	GETHER_PHY_INT_A_MARK,
+};
+static const unsigned int gether_mdio_a_pins[] = {
+	/* GETHER_MDC, GETHER_MDIO */
+	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
+};
+static const unsigned int gether_mdio_a_mux[] = {
+	GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
+};
+static const unsigned int gether_link_b_pins[] = {
+	/* GETHER_LINK */
+	RCAR_GP_PIN(0, 18),
+};
+static const unsigned int gether_link_b_mux[] = {
+	GETHER_LINK_B_MARK,
+};
+static const unsigned int gether_phy_int_b_pins[] = {
+	/* GETHER_PHY_INT */
+	RCAR_GP_PIN(0, 19),
+};
+static const unsigned int gether_phy_int_b_mux[] = {
+	GETHER_PHY_INT_B_MARK,
+};
+static const unsigned int gether_mdio_b_mux[] = {
+	GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
+};
+static const unsigned int gether_mdio_b_pins[] = {
+	/* GETHER_MDC, GETHER_MDIO */
+	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int gether_magic_pins[] = {
+	/* GETHER_MAGIC */
+	RCAR_GP_PIN(4, 22),
+};
+static const unsigned int gether_magic_mux[] = {
+	GETHER_MAGIC_MARK,
+};
+static const unsigned int gether_rgmii_pins[] = {
+	/*
+	 * GETHER_TX_CTL, GETHER_TXC,
+	 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
+	 * GETHER_RX_CTL, GETHER_RXC,
+	 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
+	 */
+	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
+	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
+	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
+	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
+	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
+	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int gether_rgmii_mux[] = {
+	GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
+	GETHER_TD0_MARK, GETHER_TD1_MARK,
+	GETHER_TD2_MARK, GETHER_TD3_MARK,
+	GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
+	GETHER_RD0_MARK, AVB_RD1_MARK,
+	GETHER_RD2_MARK, AVB_RD3_MARK,
+};
+static const unsigned int gether_txcrefclk_pins[] = {
+	/* GETHER_TXCREFCLK */
+	RCAR_GP_PIN(4, 18),
+};
+static const unsigned int gether_txcrefclk_mux[] = {
+	GETHER_TXCREFCLK_MARK,
+};
+static const unsigned int gether_txcrefclk_mega_pins[] = {
+	/* GETHER_TXCREFCLK_MEGA */
+	RCAR_GP_PIN(4, 19),
+};
+static const unsigned int gether_txcrefclk_mega_mux[] = {
+	GETHER_TXCREFCLK_MEGA_MARK,
+};
+static const unsigned int gether_rmii_pins[] = {
+	/*
+	 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
+	 * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
+	 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
+	 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
+	 */
+	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int gether_rmii_mux[] = {
+	GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
+	GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
+	GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
+	GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
+};
+
 /* - HSCIF0 ----------------------------------------------------------------- */
-static const unsigned int hscif0_data_pins[] = {
-	/* HRX, HTX */
-	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
+static const unsigned int hscif0_data_a_pins[] = {
+	/* HRX0, HTX0 */
+	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
 };
-static const unsigned int hscif0_data_mux[] = {
-	HRX0_MARK, HTX0_MARK,
+static const unsigned int hscif0_data_a_mux[] = {
+	HRX0_A_MARK, HTX0_A_MARK,
 };
-static const unsigned int hscif0_clk_pins[] = {
-	/* HSCK */
-	RCAR_GP_PIN(0, 0),
+static const unsigned int hscif0_clk_a_pins[] = {
+	/* HSCK0 */
+	RCAR_GP_PIN(0, 12),
 };
-static const unsigned int hscif0_clk_mux[] = {
-	HSCK0_MARK,
+static const unsigned int hscif0_clk_a_mux[] = {
+	HSCK0_A_MARK,
 };
-static const unsigned int hscif0_ctrl_pins[] = {
-	/* HRTS#, HCTS# */
-	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
+static const unsigned int hscif0_ctrl_a_pins[] = {
+	/* HRTS0#, HCTS0# */
+	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
 };
-static const unsigned int hscif0_ctrl_mux[] = {
-	HRTS0_N_MARK, HCTS0_N_MARK,
+static const unsigned int hscif0_ctrl_a_mux[] = {
+	HRTS0_N_A_MARK, HCTS0_N_A_MARK,
+};
+static const unsigned int hscif0_data_b_pins[] = {
+	/* HRX0, HTX0 */
+	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int hscif0_data_b_mux[] = {
+	HRX0_B_MARK, HTX0_B_MARK,
+};
+static const unsigned int hscif0_clk_b_pins[] = {
+	/* HSCK0 */
+	RCAR_GP_PIN(4, 1),
+};
+static const unsigned int hscif0_clk_b_mux[] = {
+	HSCK0_B_MARK,
+};
+static const unsigned int hscif0_ctrl_b_pins[] = {
+	/* HRTS0#, HCTS0# */
+	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int hscif0_ctrl_b_mux[] = {
+	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
 };
 
 /* - HSCIF1 ----------------------------------------------------------------- */
 static const unsigned int hscif1_data_pins[] = {
-	/* HRX, HTX */
+	/* HRX1, HTX1 */
 	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
 };
 static const unsigned int hscif1_data_mux[] = {
 	HRX1_MARK, HTX1_MARK,
 };
 static const unsigned int hscif1_clk_pins[] = {
-	/* HSCK */
+	/* HSCK1 */
 	RCAR_GP_PIN(2, 7),
 };
 static const unsigned int hscif1_clk_mux[] = {
 	HSCK1_MARK,
 };
 static const unsigned int hscif1_ctrl_pins[] = {
-	/* HRTS#, HCTS# */
+	/* HRTS1#, HCTS1# */
 	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
 };
 static const unsigned int hscif1_ctrl_mux[] = {
···
 
 /* - HSCIF2 ----------------------------------------------------------------- */
 static const unsigned int hscif2_data_pins[] = {
-	/* HRX, HTX */
+	/* HRX2, HTX2 */
 	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
 };
 static const unsigned int hscif2_data_mux[] = {
 	HRX2_MARK, HTX2_MARK,
 };
 static const unsigned int hscif2_clk_pins[] = {
-	/* HSCK */
+	/* HSCK2 */
 	RCAR_GP_PIN(2, 12),
 };
 static const unsigned int hscif2_clk_mux[] = {
 	HSCK2_MARK,
 };
 static const unsigned int hscif2_ctrl_pins[] = {
-	/* HRTS#, HCTS# */
+	/* HRTS2#, HCTS2# */
 	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
 };
 static const unsigned int hscif2_ctrl_mux[] = {
···
 
 /* - HSCIF3 ----------------------------------------------------------------- */
 static const unsigned int hscif3_data_pins[] = {
-	/* HRX, HTX */
+	/* HRX3, HTX3 */
 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
 };
 static const unsigned int hscif3_data_mux[] = {
 	HRX3_MARK, HTX3_MARK,
 };
 static const unsigned int hscif3_clk_pins[] = {
-	/* HSCK */
+	/* HSCK3 */
 	RCAR_GP_PIN(2, 0),
 };
 static const unsigned int hscif3_clk_mux[] = {
 	HSCK3_MARK,
 };
 static const unsigned int hscif3_ctrl_pins[] = {
-	/* HRTS#, HCTS# */
+	/* HRTS3#, HCTS3# */
 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
 };
 static const unsigned int hscif3_ctrl_mux[] = {
···
 
 /* - I2C0 ------------------------------------------------------------------- */
 static const unsigned int i2c0_pins[] = {
-	/* SDA, SCL */
+	/* SDA0, SCL0 */
 	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
 };
 static const unsigned int i2c0_mux[] = {
···
 
 /* - I2C1 ------------------------------------------------------------------- */
 static const unsigned int i2c1_pins[] = {
-	/* SDA, SCL */
+	/* SDA1, SCL1 */
 	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
 };
 static const unsigned int i2c1_mux[] = {
···
 
 /* - I2C2 ------------------------------------------------------------------- */
 static const unsigned int i2c2_pins[] = {
-	/* SDA, SCL */
+	/* SDA2, SCL2 */
 	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
 };
 static const unsigned int i2c2_mux[] = {
···
 };
 
 /* - I2C3 ------------------------------------------------------------------- */
-static const unsigned int i2c3_a_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+static const unsigned int i2c3_pins[] = {
+	/* SDA3, SCL3 */
+	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
 };
-static const unsigned int i2c3_a_mux[] = {
-	SDA3_A_MARK, SCL3_A_MARK,
-};
-static const unsigned int i2c3_b_pins[] = {
-	/* SDA, SCL */
-	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
-};
-static const unsigned int i2c3_b_mux[] = {
-	SDA3_B_MARK, SCL3_B_MARK,
+static const unsigned int i2c3_mux[] = {
+	SDA3_MARK, SCL3_MARK,
 };
 
 /* - I2C4 ------------------------------------------------------------------- */
 static const unsigned int i2c4_pins[] = {
-	/* SDA, SCL */
+	/* SDA4, SCL4 */
 	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
 };
 static const unsigned int i2c4_mux[] = {
 	SDA4_MARK, SCL4_MARK,
+};
+
+/* - I2C5 ------------------------------------------------------------------- */
+static const unsigned int i2c5_pins[] = {
+	/* SDA5, SCL5 */
+	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
+};
+static const unsigned int i2c5_mux[] = {
+	SDA5_MARK, SCL5_MARK,
 };
 
 /* - INTC-EX ---------------------------------------------------------------- */
···
 };
 static const unsigned int intc_ex_irq1_pins[] = {
 	/* IRQ1 */
-	RCAR_GP_PIN(0, 11),
+	RCAR_GP_PIN(0, 12),
 };
 static const unsigned int intc_ex_irq1_mux[] = {
 	IRQ1_MARK,
 };
 static const unsigned int intc_ex_irq2_pins[] = {
 	/* IRQ2 */
-	RCAR_GP_PIN(0, 12),
+	RCAR_GP_PIN(0, 13),
 };
 static const unsigned int intc_ex_irq2_mux[] = {
 	IRQ2_MARK,
 };
 static const unsigned int intc_ex_irq3_pins[] = {
 	/* IRQ3 */
-	RCAR_GP_PIN(0, 19),
+	RCAR_GP_PIN(0, 14),
 };
 static const unsigned int intc_ex_irq3_mux[] = {
 	IRQ3_MARK,
 };
 static const unsigned int intc_ex_irq4_pins[] = {
 	/* IRQ4 */
-	RCAR_GP_PIN(3, 15),
+	RCAR_GP_PIN(2, 17),
 };
 static const unsigned int intc_ex_irq4_mux[] = {
 	IRQ4_MARK,
 };
 static const unsigned int intc_ex_irq5_pins[] = {
 	/* IRQ5 */
-	RCAR_GP_PIN(3, 16),
+	RCAR_GP_PIN(2, 18),
 };
 static const unsigned int intc_ex_irq5_mux[] = {
 	IRQ5_MARK,
···
 
 /* - MMC -------------------------------------------------------------------- */
 static const unsigned int mmc_data1_pins[] = {
-	/* D0 */
-	RCAR_GP_PIN(3, 6),
+	/* MMC_D0 */
+	RCAR_GP_PIN(3, 8),
 };
 static const unsigned int mmc_data1_mux[] = {
 	MMC_D0_MARK,
 };
 static const unsigned int mmc_data4_pins[] = {
-	/* D[0:3] */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+	/* MMC_D[0:3] */
 	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
 static const unsigned int mmc_data4_mux[] = {
 	MMC_D0_MARK, MMC_D1_MARK,
 	MMC_D2_MARK, MMC_D3_MARK,
 };
 static const unsigned int mmc_data8_pins[] = {
-	/* D[0:7] */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+	/* MMC_D[0:7] */
 	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
+	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
 };
 static const unsigned int mmc_data8_mux[] = {
 	MMC_D0_MARK, MMC_D1_MARK,
···
 	MMC_D6_MARK, MMC_D7_MARK,
 };
 static const unsigned int mmc_ctrl_pins[] = {
-	/* CLK, CMD */
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
+	/* MMC_CLK, MMC_CMD */
+	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
 };
 static const unsigned int mmc_ctrl_mux[] = {
 	MMC_CLK_MARK, MMC_CMD_MARK,
 };
+static const unsigned int mmc_cd_pins[] = {
+	/* MMC_CD */
+	RCAR_GP_PIN(3, 5),
+};
+static const unsigned int mmc_cd_mux[] = {
+	MMC_CD_MARK,
+};
+static const unsigned int mmc_wp_pins[] = {
+	/* MMC_WP */
+	RCAR_GP_PIN(3, 4),
+};
+static const unsigned int mmc_wp_mux[] = {
+	MMC_WP_MARK,
+};
+static const unsigned int mmc_ds_pins[] = {
+	/* MMC_DS */
+	RCAR_GP_PIN(3, 6),
+};
+static const unsigned int mmc_ds_mux[] = {
+	MMC_DS_MARK,
+};
 
 /* - MSIOF0 ----------------------------------------------------------------- */
 static const unsigned int msiof0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 2),
+	/* MSIOF0_SCK */
+	RCAR_GP_PIN(2, 21),
 };
 static const unsigned int msiof0_clk_mux[] = {
 	MSIOF0_SCK_MARK,
 };
 static const unsigned int msiof0_sync_pins[] = {
-	/* SYNC */
-	RCAR_GP_PIN(4, 3),
+	/* MSIOF0_SYNC */
+	RCAR_GP_PIN(2, 22),
 };
 static const unsigned int msiof0_sync_mux[] = {
 	MSIOF0_SYNC_MARK,
 };
 static const unsigned int msiof0_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(4, 4),
+	/* MSIOF0_SS1 */
+	RCAR_GP_PIN(2, 23),
 };
 static const unsigned int msiof0_ss1_mux[] = {
 	MSIOF0_SS1_MARK,
 };
 static const unsigned int msiof0_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(4, 5),
+	/* MSIOF0_SS2 */
+	RCAR_GP_PIN(2, 24),
 };
 static const unsigned int msiof0_ss2_mux[] = {
 	MSIOF0_SS2_MARK,
 };
 static const unsigned int msiof0_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(4, 1),
+	/* MSIOF0_TXD */
+	RCAR_GP_PIN(2, 20),
 };
 static const unsigned int msiof0_txd_mux[] = {
 	MSIOF0_TXD_MARK,
 };
 static const unsigned int msiof0_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(4, 0),
+	/* MSIOF0_RXD */
+	RCAR_GP_PIN(2, 19),
 };
 static const unsigned int msiof0_rxd_mux[] = {
 	MSIOF0_RXD_MARK,
···
 
 /* - MSIOF1 ----------------------------------------------------------------- */
 static const unsigned int msiof1_clk_pins[] = {
-	/* SCK */
+	/* MSIOF1_SCK */
 	RCAR_GP_PIN(3, 2),
 };
 static const unsigned int msiof1_clk_mux[] = {
 	MSIOF1_SCK_MARK,
 };
 static const unsigned int msiof1_sync_pins[] = {
-	/* SYNC */
+	/* MSIOF1_SYNC */
 	RCAR_GP_PIN(3, 3),
 };
 static const unsigned int msiof1_sync_mux[] = {
 	MSIOF1_SYNC_MARK,
 };
 static const unsigned int msiof1_ss1_pins[] = {
-	/* SS1 */
+	/* MSIOF1_SS1 */
 	RCAR_GP_PIN(3, 4),
 };
 static const unsigned int msiof1_ss1_mux[] = {
 	MSIOF1_SS1_MARK,
 };
 static const unsigned int msiof1_ss2_pins[] = {
-	/* SS2 */
+	/* MSIOF1_SS2 */
 	RCAR_GP_PIN(3, 5),
 };
 static const unsigned int msiof1_ss2_mux[] = {
 	MSIOF1_SS2_MARK,
 };
 static const unsigned int msiof1_txd_pins[] = {
-	/* TXD */
+	/* MSIOF1_TXD */
 	RCAR_GP_PIN(3, 1),
 };
 static const unsigned int msiof1_txd_mux[] = {
 	MSIOF1_TXD_MARK,
 };
 static const unsigned int msiof1_rxd_pins[] = {
-	/* RXD */
+	/* MSIOF1_RXD */
 	RCAR_GP_PIN(3, 0),
 };
 static const unsigned int msiof1_rxd_mux[] = {
···
 
 /* - MSIOF2 ----------------------------------------------------------------- */
 static const unsigned int msiof2_clk_pins[] = {
-	/* SCK */
+	/* MSIOF2_SCK */
 	RCAR_GP_PIN(2, 0),
 };
 static const unsigned int msiof2_clk_mux[] = {
 	MSIOF2_SCK_MARK,
 };
 static const unsigned int msiof2_sync_pins[] = {
-	/* SYNC */
+	/* MSIOF2_SYNC */
 	RCAR_GP_PIN(2, 3),
 };
 static const unsigned int msiof2_sync_mux[] = {
 	MSIOF2_SYNC_MARK,
 };
 static const unsigned int msiof2_ss1_pins[] = {
-	/* SS1 */
+	/* MSIOF2_SS1 */
 	RCAR_GP_PIN(2, 4),
 };
 static const unsigned int msiof2_ss1_mux[] = {
 	MSIOF2_SS1_MARK,
 };
 static const unsigned int msiof2_ss2_pins[] = {
-	/* SS2 */
+	/* MSIOF2_SS2 */
 	RCAR_GP_PIN(2, 5),
 };
 static const unsigned int msiof2_ss2_mux[] = {
 	MSIOF2_SS2_MARK,
 };
 static const unsigned int msiof2_txd_pins[] = {
-	/* TXD */
+	/* MSIOF2_TXD */
 	RCAR_GP_PIN(2, 2),
 };
 static const unsigned int msiof2_txd_mux[] = {
 	MSIOF2_TXD_MARK,
 };
 static const unsigned int msiof2_rxd_pins[] = {
-	/* RXD */
+	/* MSIOF2_RXD */
 	RCAR_GP_PIN(2, 1),
 };
 static const unsigned int msiof2_rxd_mux[] = {
···
 
 /* - MSIOF3 ----------------------------------------------------------------- */
 static const unsigned int msiof3_clk_pins[] = {
-	/* SCK */
+	/* MSIOF3_SCK */
 	RCAR_GP_PIN(0, 20),
 };
 static const unsigned int msiof3_clk_mux[] = {
 	MSIOF3_SCK_MARK,
 };
 static const unsigned int msiof3_sync_pins[] = {
-	/* SYNC */
+	/* MSIOF3_SYNC */
 	RCAR_GP_PIN(0, 21),
 };
 static const unsigned int msiof3_sync_mux[] = {
 	MSIOF3_SYNC_MARK,
 };
 static const unsigned int msiof3_ss1_pins[] = {
-	/* SS1 */
-	RCAR_GP_PIN(0, 6),
+	/* MSIOF3_SS1 */
+	RCAR_GP_PIN(0, 18),
 };
 static const unsigned int msiof3_ss1_mux[] = {
 	MSIOF3_SS1_MARK,
 };
 static const unsigned int msiof3_ss2_pins[] = {
-	/* SS2 */
-	RCAR_GP_PIN(0, 7),
+	/* MSIOF3_SS2 */
+	RCAR_GP_PIN(0, 19),
 };
 static const unsigned int msiof3_ss2_mux[] = {
 	MSIOF3_SS2_MARK,
 };
 static const unsigned int msiof3_txd_pins[] = {
-	/* TXD */
-	RCAR_GP_PIN(0, 5),
+	/* MSIOF3_TXD */
+	RCAR_GP_PIN(0, 17),
 };
 static const unsigned int msiof3_txd_mux[] = {
 	MSIOF3_TXD_MARK,
 };
 static const unsigned int msiof3_rxd_pins[] = {
-	/* RXD */
-	RCAR_GP_PIN(0, 4),
+	/* MSIOF3_RXD */
+	RCAR_GP_PIN(0, 16),
 };
 static const unsigned int msiof3_rxd_mux[] = {
 	MSIOF3_RXD_MARK,
···
 
 /* - PWM0 ------------------------------------------------------------------- */
 static const unsigned int pwm0_a_pins[] = {
-	RCAR_GP_PIN(2, 12),
+	/* PWM0 */
+	RCAR_GP_PIN(0, 15),
 };
 static const unsigned int pwm0_a_mux[] = {
 	PWM0_A_MARK,
 };
 static const unsigned int pwm0_b_pins[] = {
+	/* PWM0 */
 	RCAR_GP_PIN(1, 21),
 };
 static const unsigned int pwm0_b_mux[] = {
···
 
 /* - PWM1 ------------------------------------------------------------------- */
 static const unsigned int pwm1_a_pins[] = {
+	/* PWM1 */
 	RCAR_GP_PIN(2, 13),
 };
 static const unsigned int pwm1_a_mux[] = {
 	PWM1_A_MARK,
 };
 static const unsigned int pwm1_b_pins[] = {
+	/* PWM1 */
 	RCAR_GP_PIN(1, 22),
 };
 static const unsigned int pwm1_b_mux[] = {
···
 
 /* - PWM2 ------------------------------------------------------------------- */
 static const unsigned int pwm2_a_pins[] = {
+	/* PWM2 */
 	RCAR_GP_PIN(2, 14),
 };
 static const unsigned int pwm2_a_mux[] = {
 	PWM2_A_MARK,
 };
 static const unsigned int pwm2_b_pins[] = {
+	/* PWM2 */
 	RCAR_GP_PIN(1, 23),
 };
 static const unsigned int pwm2_b_mux[] = {
···
 
 /* - PWM3 ------------------------------------------------------------------- */
 static const unsigned int pwm3_a_pins[] = {
+	/* PWM3 */
 	RCAR_GP_PIN(2, 15),
 };
 static const unsigned int pwm3_a_mux[] = {
 	PWM3_A_MARK,
 };
 static const unsigned int pwm3_b_pins[] = {
+	/* PWM3 */
 	RCAR_GP_PIN(1, 24),
 };
 static const unsigned int pwm3_b_mux[] = {
···
 
 /* - PWM4 ------------------------------------------------------------------- */
 static const unsigned int pwm4_a_pins[] = {
+	/* PWM4 */
 	RCAR_GP_PIN(2, 16),
 };
 static const unsigned int pwm4_a_mux[] = {
 	PWM4_A_MARK,
 };
 static const unsigned int pwm4_b_pins[] = {
+	/* PWM4 */
 	RCAR_GP_PIN(1, 25),
 };
 static const unsigned int pwm4_b_mux[] = {
···
 	RPC_WP_N_MARK,
 };
 
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+	/* RX0, TX0 */
+	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int scif0_data_mux[] = {
+	RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+	/* SCK0 */
+	RCAR_GP_PIN(4, 1),
+};
+static const unsigned int scif0_clk_mux[] = {
+	SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+	/* RTS0#, CTS0# */
+	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+	RTS0_N_MARK, CTS0_N_MARK,
+};
+
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_a_pins[] = {
+	/* RX1, TX1 */
+	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int scif1_data_a_mux[] = {
+	RX1_A_MARK, TX1_A_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+	/* SCK1 */
+	RCAR_GP_PIN(2, 5),
+};
+static const unsigned int scif1_clk_mux[] = {
+	SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+	/* RTS1#, CTS1# */
+	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+	RTS1_N_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+	/* RX1, TX1 */
+	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
+};
+static const unsigned int scif1_data_b_mux[] = {
+	RX1_B_MARK, TX1_B_MARK,
+};
+
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+	/* RX3, TX3 */
+	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int scif3_data_mux[] = {
+	RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+	/* SCK3 */
+	RCAR_GP_PIN(2, 0),
+};
+static const unsigned int scif3_clk_mux[] = {
+	SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+	/* RTS3#, CTS3# */
+	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+	RTS3_N_MARK, CTS3_N_MARK,
+};
+
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+	/* RX4, TX4 */
+	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
+};
+static const unsigned int scif4_data_mux[] = {
+	RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+	/* SCK4 */
+	RCAR_GP_PIN(0, 0),
+};
+static const unsigned int scif4_clk_mux[] = {
+	SCK4_MARK,
+};
+static const unsigned int scif4_ctrl_pins[] = {
+	/* RTS4#, CTS4# */
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
+};
+static const unsigned int scif4_ctrl_mux[] = {
+	RTS4_N_MARK, CTS4_N_MARK,
+};
+
 /* - SCIF Clock ------------------------------------------------------------- */
 static const unsigned int scif_clk_a_pins[] = {
 	/* SCIF_CLK */
-	RCAR_GP_PIN(0, 18),
+	RCAR_GP_PIN(0, 10),
 };
 static const unsigned int scif_clk_a_mux[] = {
 	SCIF_CLK_A_MARK,
···
 	SCIF_CLK_B_MARK,
 };
 
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int scif0_data_mux[] = {
-	RX0_MARK, TX0_MARK,
-};
-static const unsigned int scif0_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(4, 1),
-};
-static const unsigned int scif0_clk_mux[] = {
-	SCK0_MARK,
-};
-static const unsigned int scif0_ctrl_pins[] = {
-	/* RTS#, CTS# */
-	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
-};
-static const unsigned int scif0_ctrl_mux[] = {
-	RTS0_N_MARK, CTS0_N_MARK,
-};
-
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_a_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-};
-static const unsigned int scif1_data_a_mux[] = {
-	RX1_A_MARK, TX1_A_MARK,
-};
-static const unsigned int scif1_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int scif1_clk_mux[] = {
-	SCK1_MARK,
-};
-static const unsigned int scif1_ctrl_pins[] = {
-	/* RTS#, CTS# */
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
-};
-static const unsigned int scif1_ctrl_mux[] = {
-	RTS1_N_MARK, CTS1_N_MARK,
-};
-static const unsigned int scif1_data_b_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	RX1_B_MARK, TX1_B_MARK,
-};
-
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-};
-static const unsigned int scif3_data_mux[] = {
-	RX3_MARK, TX3_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int scif3_clk_mux[] = {
-	SCK3_MARK,
-};
-static const unsigned int scif3_ctrl_pins[] = {
-	/* RTS#, CTS# */
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
-};
-static const unsigned int scif3_ctrl_mux[] = {
-	RTS3_N_MARK, CTS3_N_MARK,
-};
-
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_pins[] = {
-	/* RX, TX */
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
-};
-static const unsigned int scif4_data_mux[] = {
-	RX4_MARK, TX4_MARK,
-};
-static const unsigned int scif4_clk_pins[] = {
-	/* SCK */
-	RCAR_GP_PIN(3, 9),
-};
-static const unsigned int scif4_clk_mux[] = {
-	SCK4_MARK,
-};
-static const unsigned int scif4_ctrl_pins[] = {
-	/* RTS#, CTS# */
-	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
-};
-static const unsigned int scif4_ctrl_mux[] = {
-	RTS4_N_MARK, CTS4_N_MARK,
-};
-
 /* - TMU -------------------------------------------------------------------- */
 static const unsigned int tmu_tclk1_a_pins[] = {
 	/* TCLK1 */
-	RCAR_GP_PIN(4, 4),
+	RCAR_GP_PIN(3, 13),
 };
 static const unsigned int tmu_tclk1_a_mux[] = {
 	TCLK1_A_MARK,
···
 };
 static const unsigned int tmu_tclk2_a_pins[] = {
 	/* TCLK2 */
-	RCAR_GP_PIN(4, 5),
+	RCAR_GP_PIN(3, 14),
 };
 static const unsigned int tmu_tclk2_a_mux[] = {
 	TCLK2_A_MARK,
···
 	TCLK2_B_MARK,
 };
 
+/* - TPU ------------------------------------------------------------------- */
+static const unsigned int tpu_to0_pins[] = {
+	/* TPU0TO0 */
+	RCAR_GP_PIN(1, 19),
+};
+static const unsigned int tpu_to0_mux[] = {
+	TPU0TO0_MARK,
+};
+static const unsigned int tpu_to1_pins[] = {
+	/* TPU0TO1 */
+	RCAR_GP_PIN(1, 20),
+};
+static const unsigned int tpu_to1_mux[] = {
+	TPU0TO1_MARK,
+};
+static const unsigned int tpu_to2_pins[] = {
+	/* TPU0TO2 */
+	RCAR_GP_PIN(4, 2),
+};
+static const unsigned int tpu_to2_mux[] = {
+	TPU0TO2_MARK,
+};
+static const unsigned int tpu_to3_pins[] = {
+	/* TPU0TO3 */
+	RCAR_GP_PIN(4, 3),
+};
+static const unsigned int tpu_to3_mux[] = {
+	TPU0TO3_MARK,
+};
+
 /* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data12 vin0_data_pins = {
-	.data12 = {
+static const union vin_data vin0_data_pins = {
+	.data24 = {
 		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
 		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
 		RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
 		RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
 		RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
 		RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+		RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+		RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+		RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+		RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
+		RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
+		RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
 	},
 };
-static const union vin_data12 vin0_data_mux = {
-	.data12 = {
+static const union vin_data vin0_data_mux = {
+	.data24 = {
 		VI0_DATA0_MARK, VI0_DATA1_MARK,
 		VI0_DATA2_MARK, VI0_DATA3_MARK,
 		VI0_DATA4_MARK, VI0_DATA5_MARK,
 		VI0_DATA6_MARK, VI0_DATA7_MARK,
-		VI0_DATA8_MARK,  VI0_DATA9_MARK,
+		VI0_DATA8_MARK, VI0_DATA9_MARK,
 		VI0_DATA10_MARK, VI0_DATA11_MARK,
+		VI0_DATA12_MARK, VI0_DATA13_MARK,
+		VI0_DATA14_MARK, VI0_DATA15_MARK,
+		VI0_DATA16_MARK, VI0_DATA17_MARK,
+		VI0_DATA18_MARK, VI0_DATA19_MARK,
+		VI0_DATA20_MARK, VI0_DATA21_MARK,
+		VI0_DATA22_MARK, VI0_DATA23_MARK,
 	},
 };
+static const unsigned int vin0_data18_pins[] = {
+	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
+	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
+	RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
+};
+static const unsigned int vin0_data18_mux[] = {
+	VI0_DATA2_MARK, VI0_DATA3_MARK,
+	VI0_DATA4_MARK, VI0_DATA5_MARK,
+	VI0_DATA6_MARK, VI0_DATA7_MARK,
+	VI0_DATA10_MARK, VI0_DATA11_MARK,
+	VI0_DATA12_MARK, VI0_DATA13_MARK,
+	VI0_DATA14_MARK, VI0_DATA15_MARK,
+	VI0_DATA18_MARK, VI0_DATA19_MARK,
+	VI0_DATA20_MARK, VI0_DATA21_MARK,
+	VI0_DATA22_MARK, VI0_DATA23_MARK,
+};
 static const unsigned int vin0_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+	/* VI0_VSYNC#, VI0_HSYNC# */
+	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
 };
 static const unsigned int vin0_sync_mux[] = {
-	VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
+	VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
 };
 static const unsigned int vin0_field_pins[] = {
-	/* FIELD */
+	/* VI0_FIELD */
 	RCAR_GP_PIN(2, 16),
 };
 static const unsigned int vin0_field_mux[] = {
 	VI0_FIELD_MARK,
 };
 static const unsigned int vin0_clkenb_pins[] = {
-	/* CLKENB */
+	/* VI0_CLKENB */
 	RCAR_GP_PIN(2, 1),
 };
 static const unsigned int vin0_clkenb_mux[] = {
 	VI0_CLKENB_MARK,
 };
 static const unsigned int vin0_clk_pins[] = {
-	/* CLK */
+	/* VI0_CLK */
 	RCAR_GP_PIN(2, 0),
 };
 static const unsigned int vin0_clk_mux[] = {
···
 	},
 };
 static const unsigned int vin1_sync_pins[] = {
-	/* HSYNC#, VSYNC# */
-	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+	/* VI1_VSYNC#, VI1_HSYNC# */
+	 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
 };
 static const unsigned int vin1_sync_mux[] = {
-	VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
+	VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
 };
 static const unsigned int vin1_field_pins[] = {
+	/* VI1_FIELD */
 	RCAR_GP_PIN(3, 16),
 };
 static const unsigned int vin1_field_mux[] = {
-	/* FIELD */
 	VI1_FIELD_MARK,
 };
 static const unsigned int vin1_clkenb_pins[] = {
+	/* VI1_CLKENB */
 	RCAR_GP_PIN(3, 1),
 };
 static const unsigned int vin1_clkenb_mux[] = {
-	/* CLKENB */
 	VI1_CLKENB_MARK,
 };
 static const unsigned int vin1_clk_pins[] = {
+	/* VI1_CLK */
 	RCAR_GP_PIN(3, 0),
 };
 static const unsigned int vin1_clk_mux[] = {
-	/* CLK */
 	VI1_CLK_MARK,
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(avb0_link),
-	SH_PFC_PIN_GROUP(avb0_magic),
-	SH_PFC_PIN_GROUP(avb0_phy_int),
-	SH_PFC_PIN_GROUP(avb0_mdio),
-	SH_PFC_PIN_GROUP(avb0_rgmii),
-	SH_PFC_PIN_GROUP(avb0_txcrefclk),
-	SH_PFC_PIN_GROUP(avb0_avtp_pps),
-	SH_PFC_PIN_GROUP(avb0_avtp_capture),
-	SH_PFC_PIN_GROUP(avb0_avtp_match),
-	SH_PFC_PIN_GROUP(canfd_clk_a),
-	SH_PFC_PIN_GROUP(canfd_clk_b),
+	SH_PFC_PIN_GROUP(avb_link),
+	SH_PFC_PIN_GROUP(avb_magic),
+	SH_PFC_PIN_GROUP(avb_phy_int),
+	SH_PFC_PIN_GROUP(avb_mdio),
+	SH_PFC_PIN_GROUP(avb_rgmii),
+	SH_PFC_PIN_GROUP(avb_txcrefclk),
+	SH_PFC_PIN_GROUP(avb_avtp_pps),
+	SH_PFC_PIN_GROUP(avb_avtp_capture),
+	SH_PFC_PIN_GROUP(avb_avtp_match),
 	SH_PFC_PIN_GROUP(canfd0_data_a),
 	SH_PFC_PIN_GROUP(canfd0_data_b),
 	SH_PFC_PIN_GROUP(canfd1_data),
+	SH_PFC_PIN_GROUP(canfd_clk_a),
+	SH_PFC_PIN_GROUP(canfd_clk_b),
 	SH_PFC_PIN_GROUP(du_rgb666),
+	SH_PFC_PIN_GROUP(du_rgb888),
 	SH_PFC_PIN_GROUP(du_clk_out),
 	SH_PFC_PIN_GROUP(du_sync),
 	SH_PFC_PIN_GROUP(du_oddf),
 	SH_PFC_PIN_GROUP(du_cde),
 	SH_PFC_PIN_GROUP(du_disp),
-	SH_PFC_PIN_GROUP(hscif0_data),
-	SH_PFC_PIN_GROUP(hscif0_clk),
-	SH_PFC_PIN_GROUP(hscif0_ctrl),
+	SH_PFC_PIN_GROUP(gether_link_a),
+	SH_PFC_PIN_GROUP(gether_phy_int_a),
+	SH_PFC_PIN_GROUP(gether_mdio_a),
+	SH_PFC_PIN_GROUP(gether_link_b),
+	SH_PFC_PIN_GROUP(gether_phy_int_b),
+	SH_PFC_PIN_GROUP(gether_mdio_b),
+	SH_PFC_PIN_GROUP(gether_magic),
+	SH_PFC_PIN_GROUP(gether_rgmii),
+	SH_PFC_PIN_GROUP(gether_txcrefclk),
+	SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
+	SH_PFC_PIN_GROUP(gether_rmii),
+	SH_PFC_PIN_GROUP(hscif0_data_a),
+	SH_PFC_PIN_GROUP(hscif0_clk_a),
+	SH_PFC_PIN_GROUP(hscif0_ctrl_a),
+	SH_PFC_PIN_GROUP(hscif0_data_b),
+	SH_PFC_PIN_GROUP(hscif0_clk_b),
+	SH_PFC_PIN_GROUP(hscif0_ctrl_b),
 	SH_PFC_PIN_GROUP(hscif1_data),
 	SH_PFC_PIN_GROUP(hscif1_clk),
 	SH_PFC_PIN_GROUP(hscif1_ctrl),
···
 	SH_PFC_PIN_GROUP(i2c0),
 	SH_PFC_PIN_GROUP(i2c1),
 	SH_PFC_PIN_GROUP(i2c2),
-	SH_PFC_PIN_GROUP(i2c3_a),
-	SH_PFC_PIN_GROUP(i2c3_b),
+	SH_PFC_PIN_GROUP(i2c3),
 	SH_PFC_PIN_GROUP(i2c4),
+	SH_PFC_PIN_GROUP(i2c5),
 	SH_PFC_PIN_GROUP(intc_ex_irq0),
 	SH_PFC_PIN_GROUP(intc_ex_irq1),
 	SH_PFC_PIN_GROUP(intc_ex_irq2),
···
 	SH_PFC_PIN_GROUP(mmc_data4),
 	SH_PFC_PIN_GROUP(mmc_data8),
 	SH_PFC_PIN_GROUP(mmc_ctrl),
+	SH_PFC_PIN_GROUP(mmc_cd),
+	SH_PFC_PIN_GROUP(mmc_wp),
+	SH_PFC_PIN_GROUP(mmc_ds),
 	SH_PFC_PIN_GROUP(msiof0_clk),
 	SH_PFC_PIN_GROUP(msiof0_sync),
 	SH_PFC_PIN_GROUP(msiof0_ss1),
···
 	SH_PFC_PIN_GROUP(rpc_reset),
 	SH_PFC_PIN_GROUP(rpc_int),
 	SH_PFC_PIN_GROUP(rpc_wp),
-	SH_PFC_PIN_GROUP(scif_clk_a),
-	SH_PFC_PIN_GROUP(scif_clk_b),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
···
 	SH_PFC_PIN_GROUP(scif4_data),
 	SH_PFC_PIN_GROUP(scif4_clk),
 	SH_PFC_PIN_GROUP(scif4_ctrl),
+	SH_PFC_PIN_GROUP(scif_clk_a),
+	SH_PFC_PIN_GROUP(scif_clk_b),
 	SH_PFC_PIN_GROUP(tmu_tclk1_a),
 	SH_PFC_PIN_GROUP(tmu_tclk1_b),
 	SH_PFC_PIN_GROUP(tmu_tclk2_a),
 	SH_PFC_PIN_GROUP(tmu_tclk2_b),
+	SH_PFC_PIN_GROUP(tpu_to0),
+	SH_PFC_PIN_GROUP(tpu_to1),
+	SH_PFC_PIN_GROUP(tpu_to2),
+	SH_PFC_PIN_GROUP(tpu_to3),
 	VIN_DATA_PIN_GROUP(vin0_data, 8),
 	VIN_DATA_PIN_GROUP(vin0_data, 10),
 	VIN_DATA_PIN_GROUP(vin0_data, 12),
+	VIN_DATA_PIN_GROUP(vin0_data, 16),
+	SH_PFC_PIN_GROUP(vin0_data18),
+	VIN_DATA_PIN_GROUP(vin0_data, 20),
+	VIN_DATA_PIN_GROUP(vin0_data, 24),
 	SH_PFC_PIN_GROUP(vin0_sync),
 	SH_PFC_PIN_GROUP(vin0_field),
 	SH_PFC_PIN_GROUP(vin0_clkenb),
···
 	SH_PFC_PIN_GROUP(vin1_clk),
 };
 
-static const char * const avb0_groups[] = {
-	"avb0_link",
-	"avb0_magic",
-	"avb0_phy_int",
-	"avb0_mdio",
-	"avb0_rgmii",
-	"avb0_txcrefclk",
-	"avb0_avtp_pps",
-	"avb0_avtp_capture",
-	"avb0_avtp_match",
-};
-
-static const char * const canfd_clk_groups[] = {
-	"canfd_clk_a",
-	"canfd_clk_b",
+static const char * const avb_groups[] = {
+	"avb_link",
+	"avb_magic",
+	"avb_phy_int",
+	"avb_mdio",
+	"avb_rgmii",
+	"avb_txcrefclk",
+	"avb_avtp_pps",
+	"avb_avtp_capture",
+	"avb_avtp_match",
 };
 
 static const char * const canfd0_groups[] = {
···
 	"canfd1_data",
 };
 
+static const char * const canfd_clk_groups[] = {
+	"canfd_clk_a",
+	"canfd_clk_b",
+};
+
 static const char * const du_groups[] = {
 	"du_rgb666",
+	"du_rgb888",
 	"du_clk_out",
 	"du_sync",
 	"du_oddf",
···
 	"du_disp",
 };
 
+static const char * const gether_groups[] = {
+	"gether_link_a",
+	"gether_phy_int_a",
+	"gether_mdio_a",
+	"gether_link_b",
+	"gether_phy_int_b",
+	"gether_mdio_b",
+	"gether_magic",
+	"gether_rgmii",
+	"gether_txcrefclk",
+	"gether_txcrefclk_mega",
+	"gether_rmii",
+};
+
 static const char * const hscif0_groups[] = {
-	"hscif0_data",
-	"hscif0_clk",
-	"hscif0_ctrl",
+	"hscif0_data_a",
+	"hscif0_clk_a",
+	"hscif0_ctrl_a",
+	"hscif0_data_b",
+	"hscif0_clk_b",
+	"hscif0_ctrl_b",
 };
 
 static const char * const hscif1_groups[] = {
···
 };
 
 static const char * const i2c3_groups[] = {
-	"i2c3_a",
-	"i2c3_b",
+	"i2c3",
 };
 
 static const char * const i2c4_groups[] = {
 	"i2c4",
+};
+
+static const char * const i2c5_groups[] = {
+	"i2c5",
 };
 
 static const char * const intc_ex_groups[] = {
···
 	"mmc_data4",
 	"mmc_data8",
 	"mmc_ctrl",
+	"mmc_cd",
+	"mmc_wp",
+	"mmc_ds",
 };
 
 static const char * const msiof0_groups[] = {
···
 	"rpc_wp",
 };
 
-static const char * const scif_clk_groups[] = {
-	"scif_clk_a",
-	"scif_clk_b",
-};
-
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
···
 	"scif4_ctrl",
 };
 
+static const char * const scif_clk_groups[] = {
+	"scif_clk_a",
+	"scif_clk_b",
+};
+
 static const char * const tmu_groups[] = {
 	"tmu_tclk1_a",
 	"tmu_tclk1_b",
···
 	"tmu_tclk2_b",
 };
 
+static const char * const tpu_groups[] = {
+	"tpu_to0",
+	"tpu_to1",
+	"tpu_to2",
+	"tpu_to3",
+};
+
 static const char * const vin0_groups[] = {
 	"vin0_data8",
 	"vin0_data10",
 	"vin0_data12",
+	"vin0_data16",
+	"vin0_data18",
+	"vin0_data20",
+	"vin0_data24",
 	"vin0_sync",
 	"vin0_field",
 	"vin0_clkenb",
···
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(avb0),
-	SH_PFC_FUNCTION(canfd_clk),
+	SH_PFC_FUNCTION(avb),
 	SH_PFC_FUNCTION(canfd0),
 	SH_PFC_FUNCTION(canfd1),
+	SH_PFC_FUNCTION(canfd_clk),
 	SH_PFC_FUNCTION(du),
+	SH_PFC_FUNCTION(gether),
 	SH_PFC_FUNCTION(hscif0),
 	SH_PFC_FUNCTION(hscif1),
 	SH_PFC_FUNCTION(hscif2),
···
 	SH_PFC_FUNCTION(i2c2),
 	SH_PFC_FUNCTION(i2c3),
 	SH_PFC_FUNCTION(i2c4),
+	SH_PFC_FUNCTION(i2c5),
 	SH_PFC_FUNCTION(intc_ex),
 	SH_PFC_FUNCTION(mmc),
 	SH_PFC_FUNCTION(msiof0),
···
 	SH_PFC_FUNCTION(qspi0),
 	SH_PFC_FUNCTION(qspi1),
 	SH_PFC_FUNCTION(rpc),
-	SH_PFC_FUNCTION(scif_clk),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif3),
 	SH_PFC_FUNCTION(scif4),
+	SH_PFC_FUNCTION(scif_clk),
 	SH_PFC_FUNCTION(tmu),
+	SH_PFC_FUNCTION(tpu),
 	SH_PFC_FUNCTION(vin0),
 	SH_PFC_FUNCTION(vin1),
 };
···
 	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
 		0, 0,
 		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
+		GP_2_29_FN,	GPSR2_29,
+		GP_2_28_FN,	GPSR2_28,
+		GP_2_27_FN,	GPSR2_27,
+		GP_2_26_FN,	GPSR2_26,
+		GP_2_25_FN,	GPSR2_25,
+		GP_2_24_FN,	GPSR2_24,
+		GP_2_23_FN,	GPSR2_23,
+		GP_2_22_FN,	GPSR2_22,
+		GP_2_21_FN,	GPSR2_21,
+		GP_2_20_FN,	GPSR2_20,
+		GP_2_19_FN,	GPSR2_19,
+		GP_2_18_FN,	GPSR2_18,
+		GP_2_17_FN,	GPSR2_17,
 		GP_2_16_FN,	GPSR2_16,
 		GP_2_15_FN,	GPSR2_15,
 		GP_2_14_FN,	GPSR2_14,
···
 		0, 0,
 		0, 0,
 		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
-		0, 0,
+		GP_4_24_FN,	GPSR4_24,
+		GP_4_23_FN,	GPSR4_23,
+		GP_4_22_FN,	GPSR4_22,
+		GP_4_21_FN,	GPSR4_21,
+		GP_4_20_FN,	GPSR4_20,
+		GP_4_19_FN,	GPSR4_19,
+		GP_4_18_FN,	GPSR4_18,
+		GP_4_17_FN,	GPSR4_17,
+		GP_4_16_FN,	GPSR4_16,
+		GP_4_15_FN,	GPSR4_15,
+		GP_4_14_FN,	GPSR4_14,
+		GP_4_13_FN,	GPSR4_13,
+		GP_4_12_FN,	GPSR4_12,
+		GP_4_11_FN,	GPSR4_11,
+		GP_4_10_FN,	GPSR4_10,
+		GP_4_9_FN,	GPSR4_9,
+		GP_4_8_FN,	GPSR4_8,
+		GP_4_7_FN,	GPSR4_7,
+		GP_4_6_FN,	GPSR4_6,
 		GP_4_5_FN,	GPSR4_5,
 		GP_4_4_FN,	GPSR4_4,
 		GP_4_3_FN,	GPSR4_3,
···
 		IP8_7_4
 		IP8_3_0 ))
 	},
+	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
+		IP9_31_28
+		IP9_27_24
+		IP9_23_20
+		IP9_19_16
+		IP9_15_12
+		IP9_11_8
+		IP9_7_4
+		IP9_3_0 ))
+	},
+	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
+		IP10_31_28
+		IP10_27_24
+		IP10_23_20
+		IP10_19_16
+		IP10_15_12
+		IP10_11_8
+		IP10_7_4
+		IP10_3_0 ))
+	},
 #undef F_
 #undef FM
 
···
 		MOD_SEL0_6
 		MOD_SEL0_5
 		MOD_SEL0_4
-		MOD_SEL0_3
+		0, 0,
 		MOD_SEL0_2
 		MOD_SEL0_1
 		MOD_SEL0_0 ))
···
 	POCCTRL0,
 	POCCTRL1,
 	POCCTRL2,
+	POCCTRL3,
 	TDSELCTRL,
 };
 
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
-	[POCCTRL0] = { 0xe6060380 },
-	[POCCTRL1] = { 0xe6060384 },
-	[POCCTRL2] = { 0xe6060388 },
+	[POCCTRL0] = { 0xe6060380, },
+	[POCCTRL1] = { 0xe6060384, },
+	[POCCTRL2] = { 0xe6060388, },
+	[POCCTRL3] = { 0xe606038c, },
 	[TDSELCTRL] = { 0xe60603c0, },
 	{ /* sentinel */ },
 };
 
-static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
+static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
 				   u32 *pocctrl)
 {
 	int bit = pin & 0x1f;
···
 	*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
 	if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
 		return bit;
-	if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+	else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
 		return bit + 22;
 
 	*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
 	if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
 		return bit - 10;
-	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
+	if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
+	    (pin >= RCAR_GP_PIN(3,  0) && pin <= RCAR_GP_PIN(3, 16)))
 		return bit + 7;
+
+	*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+	if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
+		return pin - 25;
 
 	return -EINVAL;
 }
 
 static const struct sh_pfc_soc_operations pinmux_ops = {
-	.pin_to_pocctrl = r8a77970_pin_to_pocctrl,
+	.pin_to_pocctrl = r8a77980_pin_to_pocctrl,
 };
 
-const struct sh_pfc_soc_info r8a77970_pinmux_info = {
-	.name = "r8a77970_pfc",
+const struct sh_pfc_soc_info r8a77980_pinmux_info = {
+	.name = "r8a77980_pfc",
 	.ops = &pinmux_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 

drivers/pinctrl/sh-pfc/pfc-r8a77980.c drivers/pinctrl/renesas/pfc-r8a77970.c

···
 // SPDX-License-Identifier: GPL-2.0
 /*
- * R8A77980 processor support - PFC hardware block.
+ * R8A77970 processor support - PFC hardware block.
  *
- * Copyright (C) 2018 Renesas Electronics Corp.
- * Copyright (C) 2018 Cogent Embedded, Inc.
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc. <[e-mail]>
  *
- * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+ * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
  *
  * R-Car Gen3 processor support - PFC hardware block.
  *
- * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015  Renesas Electronics Corporation
  */
 
 #include <linux/errno.h>
···
 #include "core.h"
 #include "sh_pfc.h"
 
-#define CPU_ALL_GP(fn, sfx)	\
-	PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_28(1, fn, sfx),	\
-	PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),	\
-	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
-	PORT_GP_25(4, fn, sfx),	\
+#define CPU_ALL_GP(fn, sfx)						\
+	PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
+	PORT_GP_28(1, fn, sfx),						\
+	PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
+	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
+	PORT_GP_6(4,  fn, sfx),						\
 	PORT_GP_15(5, fn, sfx)
-
 /*
  * F_() : just information
  * FM() : macro for FN_xxx / xxx_MARK
···
 #define GPSR0_0		F_(DU_DR2,			IP0_3_0)
 
 /* GPSR1 */
-#define GPSR1_27	F_(DIGRF_CLKOUT,	IP8_31_28)
-#define GPSR1_26	F_(DIGRF_CLKIN,		IP8_27_24)
-#define GPSR1_25	F_(CANFD_CLK_A,		IP8_23_20)
-#define GPSR1_24	F_(CANFD1_RX,		IP8_19_16)
-#define GPSR1_23	F_(CANFD1_TX,		IP8_15_12)
-#define GPSR1_22	F_(CANFD0_RX_A,		IP8_11_8)
-#define GPSR1_21	F_(CANFD0_TX_A,		IP8_7_4)
-#define GPSR1_20	F_(AVB_AVTP_CAPTURE,	IP8_3_0)
-#define GPSR1_19	F_(AVB_AVTP_MATCH,	IP7_31_28)
-#define GPSR1_18	FM(AVB_LINK)
-#define GPSR1_17	FM(AVB_PHY_INT)
-#define GPSR1_16	FM(AVB_MAGIC)
-#define GPSR1_15	FM(AVB_MDC)
-#define GPSR1_14	FM(AVB_MDIO)
-#define GPSR1_13	FM(AVB_TXCREFCLK)
-#define GPSR1_12	FM(AVB_TD3)
-#define GPSR1_11	FM(AVB_TD2)
-#define GPSR1_10	FM(AVB_TD1)
-#define GPSR1_9		FM(AVB_TD0)
-#define GPSR1_8		FM(AVB_TXC)
-#define GPSR1_7		FM(AVB_TX_CTL)
-#define GPSR1_6		FM(AVB_RD3)
-#define GPSR1_5		FM(AVB_RD2)
-#define GPSR1_4		FM(AVB_RD1)
-#define GPSR1_3		FM(AVB_RD0)
-#define GPSR1_2		FM(AVB_RXC)
-#define GPSR1_1		FM(AVB_RX_CTL)
+#define GPSR1_27	F_(DIGRF_CLKOUT,	IP8_27_24)
+#define GPSR1_26	F_(DIGRF_CLKIN,		IP8_23_20)
+#define GPSR1_25	F_(CANFD_CLK_A,		IP8_19_16)
+#define GPSR1_24	F_(CANFD1_RX,		IP8_15_12)
+#define GPSR1_23	F_(CANFD1_TX,		IP8_11_8)
+#define GPSR1_22	F_(CANFD0_RX_A,		IP8_7_4)
+#define GPSR1_21	F_(CANFD0_TX_A,		IP8_3_0)
+#define GPSR1_20	F_(AVB0_AVTP_CAPTURE,	IP7_31_28)
+#define GPSR1_19	FM(AVB0_AVTP_MATCH)
+#define GPSR1_18	FM(AVB0_LINK)
+#define GPSR1_17	FM(AVB0_PHY_INT)
+#define GPSR1_16	FM(AVB0_MAGIC)
+#define GPSR1_15	FM(AVB0_MDC)
+#define GPSR1_14	FM(AVB0_MDIO)
+#define GPSR1_13	FM(AVB0_TXCREFCLK)
+#define GPSR1_12	FM(AVB0_TD3)
+#define GPSR1_11	FM(AVB0_TD2)
+#define GPSR1_10	FM(AVB0_TD1)
+#define GPSR1_9		FM(AVB0_TD0)
+#define GPSR1_8		FM(AVB0_TXC)
+#define GPSR1_7		FM(AVB0_TX_CTL)
+#define GPSR1_6		FM(AVB0_RD3)
+#define GPSR1_5		FM(AVB0_RD2)
+#define GPSR1_4		FM(AVB0_RD1)
+#define GPSR1_3		FM(AVB0_RD0)
+#define GPSR1_2		FM(AVB0_RXC)
+#define GPSR1_1		FM(AVB0_RX_CTL)
 #define GPSR1_0		F_(IRQ0,		IP2_27_24)
 
 /* GPSR2 */
-#define GPSR2_29	F_(FSO_TOE_N,  		IP10_19_16)
-#define GPSR2_28	F_(FSO_CFE_1_N,		IP10_15_12)
-#define GPSR2_27	F_(FSO_CFE_0_N,		IP10_11_8)
-#define GPSR2_26	F_(SDA3,		IP10_7_4)
-#define GPSR2_25	F_(SCL3,		IP10_3_0)
-#define GPSR2_24	F_(MSIOF0_SS2,		IP9_31_28)
-#define GPSR2_23	F_(MSIOF0_SS1,		IP9_27_24)
-#define GPSR2_22	F_(MSIOF0_SYNC,		IP9_23_20)
-#define GPSR2_21	F_(MSIOF0_SCK,		IP9_19_16)
-#define GPSR2_20	F_(MSIOF0_TXD,		IP9_15_12)
-#define GPSR2_19	F_(MSIOF0_RXD,		IP9_11_8)
-#define GPSR2_18	F_(IRQ5,		IP9_7_4)
-#define GPSR2_17	F_(IRQ4,		IP9_3_0)
 #define GPSR2_16	F_(VI0_FIELD,		IP4_31_28)
 #define GPSR2_15	F_(VI0_DATA11,		IP4_27_24)
 #define GPSR2_14	F_(VI0_DATA10,		IP4_23_20)
···
 #define GPSR3_0		F_(VI1_CLK,		IP5_3_0)
 
 /* GPSR4 */
-#define GPSR4_24	FM(GETHER_LINK_A)
-#define GPSR4_23	FM(GETHER_PHY_INT_A)
-#define GPSR4_22	FM(GETHER_MAGIC)
-#define GPSR4_21	FM(GETHER_MDC_A)
-#define GPSR4_20	FM(GETHER_MDIO_A)
-#define GPSR4_19	FM(GETHER_TXCREFCLK_MEGA)
-#define GPSR4_18	FM(GETHER_TXCREFCLK)
-#define GPSR4_17	FM(GETHER_TD3)
-#define GPSR4_16	FM(GETHER_TD2)
-#define GPSR4_15	FM(GETHER_TD1)
-#define GPSR4_14	FM(GETHER_TD0)
-#define GPSR4_13	FM(GETHER_TXC)
-#define GPSR4_12	FM(GETHER_TX_CTL)
-#define GPSR4_11	FM(GETHER_RD3)
-#define GPSR4_10	FM(GETHER_RD2)
-#define GPSR4_9		FM(GETHER_RD1)
-#define GPSR4_8		FM(GETHER_RD0)
-#define GPSR4_7		FM(GETHER_RXC)
-#define GPSR4_6		FM(GETHER_RX_CTL)
 #define GPSR4_5		F_(SDA2,		IP7_27_24)
 #define GPSR4_4		F_(SCL2,		IP7_23_20)
 #define GPSR4_3		F_(SDA1,		IP7_19_16)
···
 #define GPSR5_0		FM(QSPI0_SPCLK)
 
 
-/* IPSRx */		/* 0 */				/* 1 */			/* 2 */			/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
-#define IP0_3_0		FM(DU_DR2)			FM(SCK4)		FM(GETHER_RMII_CRS_DV)	FM(A0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_7_4		FM(DU_DR3)			FM(RX4)			FM(GETHER_RMII_RX_ER)	FM(A1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_11_8	FM(DU_DR4)			FM(TX4)			FM(GETHER_RMII_RXD0)	FM(A2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_15_12	FM(DU_DR5)			FM(CTS4_N)		FM(GETHER_RMII_RXD1)	FM(A3)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_19_16	FM(DU_DR6)			FM(RTS4_N)		FM(GETHER_RMII_TXD_EN)	FM(A4)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_23_20	FM(DU_DR7)			F_(0, 0)		FM(GETHER_RMII_TXD0)	FM(A5)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24	FM(DU_DG2)			F_(0, 0)		FM(GETHER_RMII_TXD1)	FM(A6)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28	FM(DU_DG3)			FM(CPG_CPCKOUT)		FM(GETHER_RMII_REFCLK)	FM(A7)		FM(PWMFSW0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_3_0		FM(DU_DG4)			FM(SCL5)		F_(0, 0)		FM(A8)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_7_4		FM(DU_DG5)			FM(SDA5)		FM(GETHER_MDC_B)	FM(A9)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8	FM(DU_DG6)			FM(SCIF_CLK_A)		FM(GETHER_MDIO_B)	FM(A10)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_15_12	FM(DU_DG7)			FM(HRX0_A)		F_(0, 0)		FM(A11)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_19_16	FM(DU_DB2)			FM(HSCK0_A)		F_(0, 0)		FM(A12)		FM(IRQ1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_23_20	FM(DU_DB3)			FM(HRTS0_N_A)		F_(0, 0)		FM(A13)		FM(IRQ2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_27_24	FM(DU_DB4)			FM(HCTS0_N_A)		F_(0, 0)		FM(A14)		FM(IRQ3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_31_28	FM(DU_DB5)			FM(HTX0_A)		FM(PWM0_A)		FM(A15)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_3_0		FM(DU_DB6)			FM(MSIOF3_RXD)		F_(0, 0)		FM(A16)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_7_4		FM(DU_DB7)			FM(MSIOF3_TXD)		F_(0, 0)		FM(A17)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_11_8	FM(DU_DOTCLKOUT)		FM(MSIOF3_SS1)		FM(GETHER_LINK_B)	FM(A18)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_15_12	FM(DU_EXHSYNC_DU_HSYNC)		FM(MSIOF3_SS2)		FM(GETHER_PHY_INT_B)	FM(A19)		FM(FXR_TXENA_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_19_16	FM(DU_EXVSYNC_DU_VSYNC)		FM(MSIOF3_SCK)		F_(0, 0)		F_(0, 0)	FM(FXR_TXENB_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20	FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(MSIOF3_SYNC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24	FM(IRQ0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_31_28	FM(VI0_CLK)			FM(MSIOF2_SCK)		FM(SCK3)		F_(0, 0)	FM(HSCK3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_3_0		FM(VI0_CLKENB)			FM(MSIOF2_RXD)		FM(RX3)			FM(RD_WR_N)	FM(HCTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_7_4		FM(VI0_HSYNC_N)			FM(MSIOF2_TXD)		FM(TX3)			F_(0, 0)	FM(HRTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_11_8	FM(VI0_VSYNC_N)			FM(MSIOF2_SYNC)		FM(CTS3_N)		F_(0, 0)	FM(HTX3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12	FM(VI0_DATA0)			FM(MSIOF2_SS1)		FM(RTS3_N)		F_(0, 0)	FM(HRX3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_19_16	FM(VI0_DATA1)			FM(MSIOF2_SS2)		FM(SCK1)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_23_20	FM(VI0_DATA2)			FM(AVB_AVTP_PPS)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_27_24	FM(VI0_DATA3)			FM(HSCK1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_31_28	FM(VI0_DATA4)			FM(HRTS1_N)		FM(RX1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_3_0		FM(VI0_DATA5)			FM(HCTS1_N)		FM(TX1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_7_4		FM(VI0_DATA6)			FM(HTX1)		FM(CTS1_N)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_11_8	FM(VI0_DATA7)			FM(HRX1)		FM(RTS1_N)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_15_12	FM(VI0_DATA8)			FM(HSCK2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_19_16	FM(VI0_DATA9)			FM(HCTS2_N)		FM(PWM1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_23_20	FM(VI0_DATA10)			FM(HRTS2_N)		FM(PWM2_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_27_24	FM(VI0_DATA11)			FM(HTX2)		FM(PWM3_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_31_28	FM(VI0_FIELD)			FM(HRX2)		FM(PWM4_A)		FM(CS1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_3_0		FM(VI1_CLK)			FM(MSIOF1_RXD)		F_(0, 0)		FM(CS0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_7_4		FM(VI1_CLKENB)			FM(MSIOF1_TXD)		F_(0, 0)		FM(D0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_11_8	FM(VI1_HSYNC_N)			FM(MSIOF1_SCK)		F_(0, 0)		FM(D1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_15_12	FM(VI1_VSYNC_N)			FM(MSIOF1_SYNC)		F_(0, 0)		FM(D2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_19_16	FM(VI1_DATA0)			FM(MSIOF1_SS1)		F_(0, 0)		FM(D3)		FM(MMC_WP)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_23_20	FM(VI1_DATA1)			FM(MSIOF1_SS2)		F_(0, 0)		FM(D4)		FM(MMC_CD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24	FM(VI1_DATA2)			FM(CANFD0_TX_B)		F_(0, 0)		FM(D5)		FM(MMC_DS)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_31_28	FM(VI1_DATA3)			FM(CANFD0_RX_B)		F_(0, 0)		FM(D6)		FM(MMC_CMD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_3_0		FM(VI1_DATA4)			FM(CANFD_CLK_B)		F_(0, 0)		FM(D7)		FM(MMC_D0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4		FM(VI1_DATA5)			F_(0, 0)		F_(0, 0)		FM(D8)		FM(MMC_D1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_11_8	FM(VI1_DATA6)			F_(0, 0)		F_(0, 0)		FM(D9)		FM(MMC_D2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_15_12	FM(VI1_DATA7)			F_(0, 0)		F_(0, 0)		FM(D10)		FM(MMC_D3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_19_16	FM(VI1_DATA8)			F_(0, 0)		F_(0, 0)		FM(D11)		FM(MMC_CLK)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_23_20	FM(VI1_DATA9)			FM(TCLK1_A)		F_(0, 0)		FM(D12)		FM(MMC_D4)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_27_24	FM(VI1_DATA10)			FM(TCLK2_A)		F_(0, 0)		FM(D13)		FM(MMC_D5)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_31_28	FM(VI1_DATA11)			FM(SCL4)		F_(0, 0)		FM(D14)		FM(MMC_D6)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_3_0		FM(VI1_FIELD)			FM(SDA4)		F_(0, 0)		FM(D15)		FM(MMC_D7)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_7_4		FM(SCL0)			F_(0, 0)		F_(0, 0)		FM(CLKOUT)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_11_8	FM(SDA0)			F_(0, 0)		F_(0, 0)		FM(BS_N)	FM(SCK0)	FM(HSCK0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_15_12	FM(SCL1)			F_(0, 0)		FM(TPU0TO2)		FM(RD_N)	FM(CTS0_N)	FM(HCTS0_N_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_19_16	FM(SDA1)			F_(0, 0)		FM(TPU0TO3)		FM(WE0_N)	FM(RTS0_N)	FM(HRTS0_N_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_23_20	FM(SCL2)			F_(0, 0)		F_(0, 0)		FM(WE1_N)	FM(RX0)		FM(HRX0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_27_24	FM(SDA2)			F_(0, 0)		F_(0, 0)		FM(EX_WAIT0)	FM(TX0)		FM(HTX0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_31_28	FM(AVB_AVTP_MATCH)		FM(TPU0TO0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_3_0		FM(AVB_AVTP_CAPTURE)		FM(TPU0TO1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_7_4		FM(CANFD0_TX_A)			FM(FXR_TXDA)		FM(PWM0_B)		FM(DU_DISP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_11_8	FM(CANFD0_RX_A)			FM(RXDA_EXTFXR)		FM(PWM1_B)		FM(DU_CDE)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_15_12	FM(CANFD1_TX)			FM(FXR_TXDB)		FM(PWM2_B)		FM(TCLK1_B)	FM(TX1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_19_16	FM(CANFD1_RX)			FM(RXDB_EXTFXR)		FM(PWM3_B)		FM(TCLK2_B)	FM(RX1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20	FM(CANFD_CLK_A) 		FM(CLK_EXTFXR)		FM(PWM4_B)		FM(SPEEDIN_B)	FM(SCIF_CLK_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_27_24	FM(DIGRF_CLKIN)			FM(DIGRF_CLKEN_IN)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_31_28	FM(DIGRF_CLKOUT)		FM(DIGRF_CLKEN_OUT)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_3_0		FM(IRQ4)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA12)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4 	FM(IRQ5)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA13)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_11_8	FM(MSIOF0_RXD)			FM(DU_DR0)		F_(0, 0)		FM(VI0_DATA14)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_15_12	FM(MSIOF0_TXD)			FM(DU_DR1)		F_(0, 0)		FM(VI0_DATA15)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_19_16	FM(MSIOF0_SCK)			FM(DU_DG0)		F_(0, 0)		FM(VI0_DATA16)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_23_20	FM(MSIOF0_SYNC)			FM(DU_DG1)		F_(0, 0)		FM(VI0_DATA17)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_27_24	FM(MSIOF0_SS1)			FM(DU_DB0)		FM(TCLK3)		FM(VI0_DATA18)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_31_28	FM(MSIOF0_SS2)			FM(DU_DB1)		FM(TCLK4)		FM(VI0_DATA19)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_3_0	FM(SCL3)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA20)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_7_4	FM(SDA3)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA21)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_11_8	FM(FSO_CFE_0_N)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA22)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_15_12	FM(FSO_CFE_1_N)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA23)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_19_16	FM(FSO_TOE_N)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_23_20	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_27_24	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_31_28	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+/* IPSRx */		/* 0 */				/* 1 */			/* 2 */		/* 3 */		/* 4 */			/* 5 */		/* 6 - F */
+#define IP0_3_0		FM(DU_DR2)			FM(HSCK0)		F_(0, 0)	FM(A0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_7_4		FM(DU_DR3)			FM(HRTS0_N)		F_(0, 0)	FM(A1)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_11_8	FM(DU_DR4)			FM(HCTS0_N)		F_(0, 0)	FM(A2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)	F_(0, 0) F_(0, 0)
+#define IP0_15_12	FM(DU_DR5)			FM(HTX0)		F_(0, 0)	FM(A3)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_19_16	FM(DU_DR6)			FM(MSIOF3_RXD)		F_(0, 0)	FM(A4)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_23_20	FM(DU_DR7)			FM(MSIOF3_TXD)		F_(0, 0)	FM(A5)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24	FM(DU_DG2)			FM(MSIOF3_SS1)		F_(0, 0)	FM(A6)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28	FM(DU_DG3)			FM(MSIOF3_SS2)		F_(0, 0)	FM(A7)		FM(PWMFSW0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_3_0		FM(DU_DG4)			F_(0, 0)		F_(0, 0)	FM(A8)		FM(FSO_CFE_0_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_7_4		FM(DU_DG5)			F_(0, 0)		F_(0, 0)	FM(A9)		FM(FSO_CFE_1_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8	FM(DU_DG6)			F_(0, 0)		F_(0, 0)	FM(A10)		FM(FSO_TOE_N_A) 	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_15_12	FM(DU_DG7)			F_(0, 0)		F_(0, 0)	FM(A11)		FM(IRQ1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_19_16	FM(DU_DB2)			F_(0, 0)		F_(0, 0)	FM(A12)		FM(IRQ2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_23_20	FM(DU_DB3)			F_(0, 0)		F_(0, 0)	FM(A13)		FM(FXR_CLKOUT1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_27_24	FM(DU_DB4)			F_(0, 0)		F_(0, 0)	FM(A14)		FM(FXR_CLKOUT2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_31_28	FM(DU_DB5)			F_(0, 0)		F_(0, 0)	FM(A15)		FM(FXR_TXENA_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_3_0		FM(DU_DB6)			F_(0, 0)		F_(0, 0)	FM(A16)		FM(FXR_TXENB_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_7_4		FM(DU_DB7)			F_(0, 0)		F_(0, 0)	FM(A17)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_11_8	FM(DU_DOTCLKOUT)		FM(SCIF_CLK_A)		F_(0, 0)	FM(A18)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_15_12	FM(DU_EXHSYNC_DU_HSYNC)		FM(HRX0)		F_(0, 0)	FM(A19)		FM(IRQ3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_19_16	FM(DU_EXVSYNC_DU_VSYNC)		FM(MSIOF3_SCK)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20	FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(MSIOF3_SYNC)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24	FM(IRQ0)			F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_31_28	FM(VI0_CLK)			FM(MSIOF2_SCK)		FM(SCK3)	F_(0, 0)	FM(HSCK3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_3_0		FM(VI0_CLKENB)			FM(MSIOF2_RXD)		FM(RX3)		FM(RD_WR_N)	FM(HCTS3_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_7_4		FM(VI0_HSYNC_N)			FM(MSIOF2_TXD)		FM(TX3)		F_(0, 0)	FM(HRTS3_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_11_8	FM(VI0_VSYNC_N)			FM(MSIOF2_SYNC)		FM(CTS3_N)	F_(0, 0)	FM(HTX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12	FM(VI0_DATA0)			FM(MSIOF2_SS1)		FM(RTS3_N)	F_(0, 0)	FM(HRX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_19_16	FM(VI0_DATA1)			FM(MSIOF2_SS2)		FM(SCK1)	F_(0, 0)	FM(SPEEDIN_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_23_20	FM(VI0_DATA2)			FM(AVB0_AVTP_PPS)	FM(SDA3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_27_24	FM(VI0_DATA3)			FM(HSCK1)		FM(SCL3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_31_28	FM(VI0_DATA4)			FM(HRTS1_N)		FM(RX1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_3_0		FM(VI0_DATA5)			FM(HCTS1_N)		FM(TX1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_7_4		FM(VI0_DATA6)			FM(HTX1)		FM(CTS1_N)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_11_8	FM(VI0_DATA7)			FM(HRX1)		FM(RTS1_N)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_15_12	FM(VI0_DATA8)			FM(HSCK2)		FM(PWM0_A)	FM(A22)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_19_16	FM(VI0_DATA9)			FM(HCTS2_N)		FM(PWM1_A)	FM(A23)		FM(FSO_CFE_0_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_23_20	FM(VI0_DATA10)			FM(HRTS2_N)		FM(PWM2_A)	FM(A24)		FM(FSO_CFE_1_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_27_24	FM(VI0_DATA11)			FM(HTX2)		FM(PWM3_A)	FM(A25)		FM(FSO_TOE_N_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_31_28	FM(VI0_FIELD)			FM(HRX2)		FM(PWM4_A)	FM(CS1_N)	FM(FSCLKST2_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_3_0		FM(VI1_CLK)			FM(MSIOF1_RXD)		F_(0, 0)	FM(CS0_N)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_7_4		FM(VI1_CLKENB)			FM(MSIOF1_TXD)		F_(0, 0)	FM(D0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_11_8	FM(VI1_HSYNC_N)			FM(MSIOF1_SCK)		F_(0, 0)	FM(D1)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_15_12	FM(VI1_VSYNC_N)			FM(MSIOF1_SYNC)		F_(0, 0)	FM(D2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_19_16	FM(VI1_DATA0)			FM(MSIOF1_SS1)		F_(0, 0)	FM(D3)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_23_20	FM(VI1_DATA1)			FM(MSIOF1_SS2)		F_(0, 0)	FM(D4)		FM(MMC_CMD)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24	FM(VI1_DATA2)			FM(CANFD0_TX_B)		F_(0, 0)	FM(D5)		FM(MMC_D0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_31_28	FM(VI1_DATA3)			FM(CANFD0_RX_B)		F_(0, 0)	FM(D6)		FM(MMC_D1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_3_0		FM(VI1_DATA4)			FM(CANFD_CLK_B)		F_(0, 0)	FM(D7)		FM(MMC_D2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4		FM(VI1_DATA5)			F_(0, 0)		FM(SCK4)	FM(D8)		FM(MMC_D3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_11_8	FM(VI1_DATA6)			F_(0, 0)		FM(RX4)		FM(D9)		FM(MMC_CLK)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_15_12	FM(VI1_DATA7)			F_(0, 0)		FM(TX4)		FM(D10)		FM(MMC_D4)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_19_16	FM(VI1_DATA8)			F_(0, 0)		FM(CTS4_N)	FM(D11)		FM(MMC_D5)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_23_20	FM(VI1_DATA9)			F_(0, 0)		FM(RTS4_N)	FM(D12)		FM(MMC_D6)		FM(SCL3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_27_24	FM(VI1_DATA10)			F_(0, 0)		F_(0, 0)	FM(D13)		FM(MMC_D7)		FM(SDA3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_31_28	FM(VI1_DATA11)			FM(SCL4)		FM(IRQ4)	FM(D14)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_3_0		FM(VI1_FIELD)			FM(SDA4)		FM(IRQ5)	FM(D15)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_7_4		FM(SCL0)			FM(DU_DR0)		FM(TPU0TO0)	FM(CLKOUT)	F_(0, 0)		FM(MSIOF0_RXD)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_11_8	FM(SDA0)			FM(DU_DR1)		FM(TPU0TO1)	FM(BS_N)	FM(SCK0)		FM(MSIOF0_TXD)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_15_12	FM(SCL1)			FM(DU_DG0)		FM(TPU0TO2)	FM(RD_N)	FM(CTS0_N)		FM(MSIOF0_SCK)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_19_16	FM(SDA1)			FM(DU_DG1)		FM(TPU0TO3)	FM(WE0_N)	FM(RTS0_N)		FM(MSIOF0_SYNC)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_23_20	FM(SCL2)			FM(DU_DB0)		FM(TCLK1_A)	FM(WE1_N)	FM(RX0)			FM(MSIOF0_SS1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_27_24	FM(SDA2)			FM(DU_DB1)		FM(TCLK2_A)	FM(EX_WAIT0)	FM(TX0)			FM(MSIOF0_SS2)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_31_28	FM(AVB0_AVTP_CAPTURE)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(FSCLKST2_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_3_0		FM(CANFD0_TX_A)			FM(FXR_TXDA)		FM(PWM0_B)	FM(DU_DISP)	FM(FSCLKST2_N_C)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_7_4		FM(CANFD0_RX_A)			FM(RXDA_EXTFXR)		FM(PWM1_B)	FM(DU_CDE)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_11_8	FM(CANFD1_TX)			FM(FXR_TXDB)		FM(PWM2_B)	FM(TCLK1_B)	FM(TX1_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_15_12	FM(CANFD1_RX)			FM(RXDB_EXTFXR)		FM(PWM3_B)	FM(TCLK2_B)	FM(RX1_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_19_16	FM(CANFD_CLK_A)			FM(CLK_EXTFXR)		FM(PWM4_B)	FM(SPEEDIN_B)	FM(SCIF_CLK_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20	FM(DIGRF_CLKIN)			FM(DIGRF_CLKEN_IN)	F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_27_24	FM(DIGRF_CLKOUT)		FM(DIGRF_CLKEN_OUT)	F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_31_28	F_(0, 0)			F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0)
 
 #define PINMUX_GPSR	\
 \
-				GPSR2_29 \
-				GPSR2_28 \
-		GPSR1_27	GPSR2_27 \
-		GPSR1_26	GPSR2_26 \
-		GPSR1_25	GPSR2_25 \
-		GPSR1_24	GPSR2_24			GPSR4_24 \
-		GPSR1_23	GPSR2_23			GPSR4_23 \
-		GPSR1_22	GPSR2_22			GPSR4_22 \
-GPSR0_21	GPSR1_21	GPSR2_21			GPSR4_21 \
-GPSR0_20	GPSR1_20	GPSR2_20			GPSR4_20 \
-GPSR0_19	GPSR1_19	GPSR2_19			GPSR4_19 \
-GPSR0_18	GPSR1_18	GPSR2_18			GPSR4_18 \
-GPSR0_17	GPSR1_17	GPSR2_17			GPSR4_17 \
-GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16	GPSR4_16 \
-GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15	GPSR4_15 \
-GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14 \
-GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13 \
-GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12 \
-GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11 \
-GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10 \
-GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9 \
-GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8 \
-GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7 \
-GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6 \
+		GPSR1_27 \
+		GPSR1_26 \
+		GPSR1_25 \
+		GPSR1_24 \
+		GPSR1_23 \
+		GPSR1_22 \
+GPSR0_21	GPSR1_21 \
+GPSR0_20	GPSR1_20 \
+GPSR0_19	GPSR1_19 \
+GPSR0_18	GPSR1_18 \
+GPSR0_17	GPSR1_17 \
+GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16 \
+GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15 \
+GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14			GPSR5_14 \
+GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13			GPSR5_13 \
+GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12			GPSR5_12 \
+GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11			GPSR5_11 \
+GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10			GPSR5_10 \
+GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9				GPSR5_9 \
+GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8				GPSR5_8 \
+GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7				GPSR5_7 \
+GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6				GPSR5_6 \
 GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5 \
 GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4 \
 GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3 \
···
 FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
 FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
 \
-FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0 \
-FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4 \
-FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8 \
-FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12 \
-FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16 \
-FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20 \
-FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24 \
-FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28
+FM(IP8_3_0)	IP8_3_0 \
+FM(IP8_7_4)	IP8_7_4 \
+FM(IP8_11_8)	IP8_11_8 \
+FM(IP8_15_12)	IP8_15_12 \
+FM(IP8_19_16)	IP8_19_16 \
+FM(IP8_23_20)	IP8_23_20 \
+FM(IP8_27_24)	IP8_27_24 \
+FM(IP8_31_28)	IP8_31_28
 
 /* MOD_SEL0 */		/* 0 */			/* 1 */
-#define MOD_SEL0_11	FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
-#define MOD_SEL0_10	FM(SEL_GETHER_0)	FM(SEL_GETHER_1)
-#define MOD_SEL0_9	FM(SEL_HSCIF0_0)	FM(SEL_HSCIF0_1)
-#define MOD_SEL0_8	FM(SEL_PWM0_0)		FM(SEL_PWM0_1)
-#define MOD_SEL0_7	FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
-#define MOD_SEL0_6	FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
-#define MOD_SEL0_5	FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
-#define MOD_SEL0_4	FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
-#define MOD_SEL0_2	FM(SEL_RSP_0)		FM(SEL_RSP_1)
-#define MOD_SEL0_1	FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
+#define MOD_SEL0_11	FM(SEL_I2C3_0)		FM(SEL_I2C3_1)
+#define MOD_SEL0_10	FM(SEL_HSCIF0_0)	FM(SEL_HSCIF0_1)
+#define MOD_SEL0_9	FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
+#define MOD_SEL0_8	FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
+#define MOD_SEL0_7	FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
+#define MOD_SEL0_6	FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
+#define MOD_SEL0_5	FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
+#define MOD_SEL0_4	FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
+#define MOD_SEL0_3	FM(SEL_PWM0_0)		FM(SEL_PWM0_1)
+#define MOD_SEL0_2	FM(SEL_RFSO_0)		FM(SEL_RFSO_1)
+#define MOD_SEL0_1	FM(SEL_RSP_0)		FM(SEL_RSP_1)
 #define MOD_SEL0_0	FM(SEL_TMU_0)		FM(SEL_TMU_1)
 
 #define PINMUX_MOD_SELS \
···
 MOD_SEL0_6 \
 MOD_SEL0_5 \
 MOD_SEL0_4 \
+MOD_SEL0_3 \
 MOD_SEL0_2 \
 MOD_SEL0_1 \
 MOD_SEL0_0
···
 static const u16 pinmux_data[] = {
 	PINMUX_DATA_GP_ALL(),
 
-	PINMUX_SINGLE(AVB_RX_CTL),
-	PINMUX_SINGLE(AVB_RXC),
-	PINMUX_SINGLE(AVB_RD0),
-	PINMUX_SINGLE(AVB_RD1),
-	PINMUX_SINGLE(AVB_RD2),
-	PINMUX_SINGLE(AVB_RD3),
-	PINMUX_SINGLE(AVB_TX_CTL),
-	PINMUX_SINGLE(AVB_TXC),
-	PINMUX_SINGLE(AVB_TD0),
-	PINMUX_SINGLE(AVB_TD1),
-	PINMUX_SINGLE(AVB_TD2),
-	PINMUX_SINGLE(AVB_TD3),
-	PINMUX_SINGLE(AVB_TXCREFCLK),
-	PINMUX_SINGLE(AVB_MDIO),
-	PINMUX_SINGLE(AVB_MDC),
-	PINMUX_SINGLE(AVB_MAGIC),
-	PINMUX_SINGLE(AVB_PHY_INT),
-	PINMUX_SINGLE(AVB_LINK),
-
-	PINMUX_SINGLE(GETHER_RX_CTL),
-	PINMUX_SINGLE(GETHER_RXC),
-	PINMUX_SINGLE(GETHER_RD0),
-	PINMUX_SINGLE(GETHER_RD1),
-	PINMUX_SINGLE(GETHER_RD2),
-	PINMUX_SINGLE(GETHER_RD3),
-	PINMUX_SINGLE(GETHER_TX_CTL),
-	PINMUX_SINGLE(GETHER_TXC),
-	PINMUX_SINGLE(GETHER_TD0),
-	PINMUX_SINGLE(GETHER_TD1),
-	PINMUX_SINGLE(GETHER_TD2),
-	PINMUX_SINGLE(GETHER_TD3),
-	PINMUX_SINGLE(GETHER_TXCREFCLK),
-	PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
-	PINMUX_SINGLE(GETHER_MDIO_A),
-	PINMUX_SINGLE(GETHER_MDC_A),
-	PINMUX_SINGLE(GETHER_MAGIC),
-	PINMUX_SINGLE(GETHER_PHY_INT_A),
-	PINMUX_SINGLE(GETHER_LINK_A),
+	PINMUX_SINGLE(AVB0_RX_CTL),
+	PINMUX_SINGLE(AVB0_RXC),
+	PINMUX_SINGLE(AVB0_RD0),
+	PINMUX_SINGLE(AVB0_RD1),
+	PINMUX_SINGLE(AVB0_RD2),
+	PINMUX_SINGLE(AVB0_RD3),
+	PINMUX_SINGLE(AVB0_TX_CTL),
+	PINMUX_SINGLE(AVB0_TXC),
+	PINMUX_SINGLE(AVB0_TD0),
+	PINMUX_SINGLE(AVB0_TD1),
+	PINMUX_SINGLE(AVB0_TD2),
+	PINMUX_SINGLE(AVB0_TD3),
+	PINMUX_SINGLE(AVB0_TXCREFCLK),
+	PINMUX_SINGLE(AVB0_MDIO),
+	PINMUX_SINGLE(AVB0_MDC),
+	PINMUX_SINGLE(AVB0_MAGIC),
+	PINMUX_SINGLE(AVB0_PHY_INT),
+	PINMUX_SINGLE(AVB0_LINK),
+	PINMUX_SINGLE(AVB0_AVTP_MATCH),
 
 	PINMUX_SINGLE(QSPI0_SPCLK),
 	PINMUX_SINGLE(QSPI0_MOSI_IO0),
···
 
 	/* IPSR0 */
 	PINMUX_IPSR_GPSR(IP0_3_0,	DU_DR2),
-	PINMUX_IPSR_GPSR(IP0_3_0,	SCK4),
-	PINMUX_IPSR_GPSR(IP0_3_0,	GETHER_RMII_CRS_DV),
+	PINMUX_IPSR_GPSR(IP0_3_0,	HSCK0),
 	PINMUX_IPSR_GPSR(IP0_3_0,	A0),
 
 	PINMUX_IPSR_GPSR(IP0_7_4,	DU_DR3),
-	PINMUX_IPSR_GPSR(IP0_7_4,	RX4),
-	PINMUX_IPSR_GPSR(IP0_7_4,	GETHER_RMII_RX_ER),
+	PINMUX_IPSR_GPSR(IP0_7_4,	HRTS0_N),
 	PINMUX_IPSR_GPSR(IP0_7_4,	A1),
 
 	PINMUX_IPSR_GPSR(IP0_11_8,	DU_DR4),
-	PINMUX_IPSR_GPSR(IP0_11_8,	TX4),
-	PINMUX_IPSR_GPSR(IP0_11_8,	GETHER_RMII_RXD0),
+	PINMUX_IPSR_GPSR(IP0_11_8,	HCTS0_N),
 	PINMUX_IPSR_GPSR(IP0_11_8,	A2),
 
 	PINMUX_IPSR_GPSR(IP0_15_12,	DU_DR5),
-	PINMUX_IPSR_GPSR(IP0_15_12,	CTS4_N),
-	PINMUX_IPSR_GPSR(IP0_15_12,	GETHER_RMII_RXD1),
+	PINMUX_IPSR_GPSR(IP0_15_12,	HTX0),
 	PINMUX_IPSR_GPSR(IP0_15_12,	A3),
 
 	PINMUX_IPSR_GPSR(IP0_19_16,	DU_DR6),
-	PINMUX_IPSR_GPSR(IP0_19_16,	RTS4_N),
-	PINMUX_IPSR_GPSR(IP0_19_16,	GETHER_RMII_TXD_EN),
+	PINMUX_IPSR_GPSR(IP0_19_16,	MSIOF3_RXD),
 	PINMUX_IPSR_GPSR(IP0_19_16,	A4),
 
 	PINMUX_IPSR_GPSR(IP0_23_20,	DU_DR7),
-	PINMUX_IPSR_GPSR(IP0_23_20,	GETHER_RMII_TXD0),
+	PINMUX_IPSR_GPSR(IP0_23_20,	MSIOF3_TXD),
 	PINMUX_IPSR_GPSR(IP0_23_20,	A5),
 
 	PINMUX_IPSR_GPSR(IP0_27_24,	DU_DG2),
-	PINMUX_IPSR_GPSR(IP0_27_24,	GETHER_RMII_TXD1),
+	PINMUX_IPSR_GPSR(IP0_27_24,	MSIOF3_SS1),
 	PINMUX_IPSR_GPSR(IP0_27_24,	A6),
 
 	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DG3),
-	PINMUX_IPSR_GPSR(IP0_31_28,	CPG_CPCKOUT),
-	PINMUX_IPSR_GPSR(IP0_31_28,	GETHER_RMII_REFCLK),
+	PINMUX_IPSR_GPSR(IP0_31_28,	MSIOF3_SS2),
 	PINMUX_IPSR_GPSR(IP0_31_28,	A7),
 	PINMUX_IPSR_GPSR(IP0_31_28,	PWMFSW0),
 
 	/* IPSR1 */
 	PINMUX_IPSR_GPSR(IP1_3_0,	DU_DG4),
-	PINMUX_IPSR_GPSR(IP1_3_0,	SCL5),
 	PINMUX_IPSR_GPSR(IP1_3_0,	A8),
+	PINMUX_IPSR_MSEL(IP1_3_0,	FSO_CFE_0_N_A,	SEL_RFSO_0),
 
 	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DG5),
-	PINMUX_IPSR_GPSR(IP1_7_4,	SDA5),
-	PINMUX_IPSR_MSEL(IP1_7_4,	GETHER_MDC_B, SEL_GETHER_1),
 	PINMUX_IPSR_GPSR(IP1_7_4,	A9),
+	PINMUX_IPSR_MSEL(IP1_7_4,	FSO_CFE_1_N_A,	SEL_RFSO_0),
 
 	PINMUX_IPSR_GPSR(IP1_11_8,	DU_DG6),
-	PINMUX_IPSR_MSEL(IP1_11_8,	SCIF_CLK_A, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP1_11_8,	GETHER_MDIO_B, SEL_GETHER_1),
 	PINMUX_IPSR_GPSR(IP1_11_8,	A10),
+	PINMUX_IPSR_MSEL(IP1_11_8,	FSO_TOE_N_A,	SEL_RFSO_0),
 
 	PINMUX_IPSR_GPSR(IP1_15_12,	DU_DG7),
-	PINMUX_IPSR_MSEL(IP1_15_12,	HRX0_A, SEL_HSCIF0_0),
 	PINMUX_IPSR_GPSR(IP1_15_12,	A11),
+	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ1),
 
 	PINMUX_IPSR_GPSR(IP1_19_16,	DU_DB2),
-	PINMUX_IPSR_MSEL(IP1_19_16,	HSCK0_A, SEL_HSCIF0_0),
 	PINMUX_IPSR_GPSR(IP1_19_16,	A12),
-	PINMUX_IPSR_GPSR(IP1_19_16,	IRQ1),
+	PINMUX_IPSR_GPSR(IP1_19_16,	IRQ2),
 
 	PINMUX_IPSR_GPSR(IP1_23_20,	DU_DB3),
-	PINMUX_IPSR_MSEL(IP1_23_20,	HRTS0_N_A, SEL_HSCIF0_0),
 	PINMUX_IPSR_GPSR(IP1_23_20,	A13),
-	PINMUX_IPSR_GPSR(IP1_23_20,	IRQ2),
+	PINMUX_IPSR_GPSR(IP1_23_20,	FXR_CLKOUT1),
 
 	PINMUX_IPSR_GPSR(IP1_27_24,	DU_DB4),
-	PINMUX_IPSR_MSEL(IP1_27_24,	HCTS0_N_A, SEL_HSCIF0_0),
 	PINMUX_IPSR_GPSR(IP1_27_24,	A14),
-	PINMUX_IPSR_GPSR(IP1_27_24,	IRQ3),
+	PINMUX_IPSR_GPSR(IP1_27_24,	FXR_CLKOUT2),
 
 	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB5),
-	PINMUX_IPSR_MSEL(IP1_31_28,	HTX0_A, SEL_HSCIF0_0),
-	PINMUX_IPSR_MSEL(IP1_31_28,	PWM0_A, SEL_PWM0_0),
 	PINMUX_IPSR_GPSR(IP1_31_28,	A15),
+	PINMUX_IPSR_GPSR(IP1_31_28,	FXR_TXENA_N),
 
 	/* IPSR2 */
 	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB6),
-	PINMUX_IPSR_GPSR(IP2_3_0,	MSIOF3_RXD),
 	PINMUX_IPSR_GPSR(IP2_3_0,	A16),
+	PINMUX_IPSR_GPSR(IP2_3_0,	FXR_TXENB_N),
 
 	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB7),
-	PINMUX_IPSR_GPSR(IP2_7_4,	MSIOF3_TXD),
 	PINMUX_IPSR_GPSR(IP2_7_4,	A17),
 
 	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DOTCLKOUT),
-	PINMUX_IPSR_GPSR(IP2_11_8,	MSIOF3_SS1),
-	PINMUX_IPSR_MSEL(IP2_11_8,	GETHER_LINK_B, SEL_GETHER_1),
+	PINMUX_IPSR_MSEL(IP2_11_8,	SCIF_CLK_A,	SEL_HSCIF0_0),
 	PINMUX_IPSR_GPSR(IP2_11_8,	A18),
 
 	PINMUX_IPSR_GPSR(IP2_15_12,	DU_EXHSYNC_DU_HSYNC),
-	PINMUX_IPSR_GPSR(IP2_15_12,	MSIOF3_SS2),
-	PINMUX_IPSR_MSEL(IP2_15_12,	GETHER_PHY_INT_B, SEL_GETHER_1),
+	PINMUX_IPSR_GPSR(IP2_15_12,	HRX0),
 	PINMUX_IPSR_GPSR(IP2_15_12,	A19),
-	PINMUX_IPSR_GPSR(IP2_15_12,	FXR_TXENA_N),
+	PINMUX_IPSR_GPSR(IP2_15_12,	IRQ3),
 
 	PINMUX_IPSR_GPSR(IP2_19_16,	DU_EXVSYNC_DU_VSYNC),
 	PINMUX_IPSR_GPSR(IP2_19_16,	MSIOF3_SCK),
-	PINMUX_IPSR_GPSR(IP2_19_16,	FXR_TXENB_N),
 
 	PINMUX_IPSR_GPSR(IP2_23_20,	DU_EXODDF_DU_ODDF_DISP_CDE),
 	PINMUX_IPSR_GPSR(IP2_23_20,	MSIOF3_SYNC),
···
 	PINMUX_IPSR_GPSR(IP3_19_16,	VI0_DATA1),
 	PINMUX_IPSR_GPSR(IP3_19_16,	MSIOF2_SS2),
 	PINMUX_IPSR_GPSR(IP3_19_16,	SCK1),
-	PINMUX_IPSR_MSEL(IP3_19_16,	SPEEDIN_A, SEL_RSP_0),
+	PINMUX_IPSR_MSEL(IP3_19_16,	SPEEDIN_A,	SEL_RSP_0),
 
 	PINMUX_IPSR_GPSR(IP3_23_20,	VI0_DATA2),
-	PINMUX_IPSR_GPSR(IP3_23_20,	AVB_AVTP_PPS),
+	PINMUX_IPSR_GPSR(IP3_23_20,	AVB0_AVTP_PPS),
+	PINMUX_IPSR_MSEL(IP3_23_20,	SDA3_A,		SEL_I2C3_0),
 
 	PINMUX_IPSR_GPSR(IP3_27_24,	VI0_DATA3),
 	PINMUX_IPSR_GPSR(IP3_27_24,	HSCK1),
+	PINMUX_IPSR_MSEL(IP3_27_24,	SCL3_A,		SEL_I2C3_0),
 
 	PINMUX_IPSR_GPSR(IP3_31_28,	VI0_DATA4),
 	PINMUX_IPSR_GPSR(IP3_31_28,	HRTS1_N),
-	PINMUX_IPSR_MSEL(IP3_31_28,	RX1_A, SEL_SCIF1_0),
+	PINMUX_IPSR_MSEL(IP3_31_28,	RX1_A,	SEL_SCIF1_0),
 
 	/* IPSR4 */
 	PINMUX_IPSR_GPSR(IP4_3_0,	VI0_DATA5),
 	PINMUX_IPSR_GPSR(IP4_3_0,	HCTS1_N),
-	PINMUX_IPSR_MSEL(IP4_3_0,	TX1_A, SEL_SCIF1_0),
+	PINMUX_IPSR_MSEL(IP4_3_0,	TX1_A,	SEL_SCIF1_0),
 
 	PINMUX_IPSR_GPSR(IP4_7_4,	VI0_DATA6),
 	PINMUX_IPSR_GPSR(IP4_7_4,	HTX1),
···
 
 	PINMUX_IPSR_GPSR(IP4_15_12,	VI0_DATA8),
 	PINMUX_IPSR_GPSR(IP4_15_12,	HSCK2),
+	PINMUX_IPSR_MSEL(IP4_15_12,	PWM0_A,	SEL_PWM0_0),
 
 	PINMUX_IPSR_GPSR(IP4_19_16,	VI0_DATA9),
 	PINMUX_IPSR_GPSR(IP4_19_16,	HCTS2_N),
-	PINMUX_IPSR_MSEL(IP4_19_16,	PWM1_A, SEL_PWM1_0),
+	PINMUX_IPSR_MSEL(IP4_19_16,	PWM1_A,	SEL_PWM1_0),
+	PINMUX_IPSR_MSEL(IP4_19_16,	FSO_CFE_0_N_B,	SEL_RFSO_1),
 
 	PINMUX_IPSR_GPSR(IP4_23_20,	VI0_DATA10),
 	PINMUX_IPSR_GPSR(IP4_23_20,	HRTS2_N),
-	PINMUX_IPSR_MSEL(IP4_23_20,	PWM2_A, SEL_PWM2_0),
+	PINMUX_IPSR_MSEL(IP4_23_20,	PWM2_A,	SEL_PWM2_0),
+	PINMUX_IPSR_MSEL(IP4_23_20,	FSO_CFE_1_N_B,	SEL_RFSO_1),
 
 	PINMUX_IPSR_GPSR(IP4_27_24,	VI0_DATA11),
 	PINMUX_IPSR_GPSR(IP4_27_24,	HTX2),
-	PINMUX_IPSR_MSEL(IP4_27_24,	PWM3_A, SEL_PWM3_0),
+	PINMUX_IPSR_MSEL(IP4_27_24,	PWM3_A,	SEL_PWM3_0),
+	PINMUX_IPSR_MSEL(IP4_27_24,	FSO_TOE_N_B,	SEL_RFSO_1),
 
 	PINMUX_IPSR_GPSR(IP4_31_28,	VI0_FIELD),
 	PINMUX_IPSR_GPSR(IP4_31_28,	HRX2),
-	PINMUX_IPSR_MSEL(IP4_31_28,	PWM4_A, SEL_PWM4_0),
+	PINMUX_IPSR_MSEL(IP4_31_28,	PWM4_A,	SEL_PWM4_0),
 	PINMUX_IPSR_GPSR(IP4_31_28,	CS1_N),
+	PINMUX_IPSR_GPSR(IP4_31_28,	FSCLKST2_N_A),
 
 	/* IPSR5 */
 	PINMUX_IPSR_GPSR(IP5_3_0,	VI1_CLK),
···
 	PINMUX_IPSR_GPSR(IP5_19_16,	VI1_DATA0),
 	PINMUX_IPSR_GPSR(IP5_19_16,	MSIOF1_SS1),
 	PINMUX_IPSR_GPSR(IP5_19_16,	D3),
-	PINMUX_IPSR_GPSR(IP5_19_16,	MMC_WP),
 
 	PINMUX_IPSR_GPSR(IP5_23_20,	VI1_DATA1),
 	PINMUX_IPSR_GPSR(IP5_23_20,	MSIOF1_SS2),
 	PINMUX_IPSR_GPSR(IP5_23_20,	D4),
-	PINMUX_IPSR_GPSR(IP5_23_20,	MMC_CD),
+	PINMUX_IPSR_GPSR(IP5_23_20,	MMC_CMD),
 
 	PINMUX_IPSR_GPSR(IP5_27_24,	VI1_DATA2),
-	PINMUX_IPSR_MSEL(IP5_27_24,	CANFD0_TX_B, SEL_CANFD0_1),
+	PINMUX_IPSR_MSEL(IP5_27_24,	CANFD0_TX_B,	SEL_CANFD0_1),
 	PINMUX_IPSR_GPSR(IP5_27_24,	D5),
-	PINMUX_IPSR_GPSR(IP5_27_24,	MMC_DS),
+	PINMUX_IPSR_GPSR(IP5_27_24,	MMC_D0),
 
 	PINMUX_IPSR_GPSR(IP5_31_28,	VI1_DATA3),
-	PINMUX_IPSR_MSEL(IP5_31_28,	CANFD0_RX_B, SEL_CANFD0_1),
+	PINMUX_IPSR_MSEL(IP5_31_28,	CANFD0_RX_B,	SEL_CANFD0_1),
 	PINMUX_IPSR_GPSR(IP5_31_28,	D6),
-	PINMUX_IPSR_GPSR(IP5_31_28,	MMC_CMD),
+	PINMUX_IPSR_GPSR(IP5_31_28,	MMC_D1),
 
 	/* IPSR6 */
 	PINMUX_IPSR_GPSR(IP6_3_0,	VI1_DATA4),
-	PINMUX_IPSR_MSEL(IP6_3_0,	CANFD_CLK_B, SEL_CANFD0_1),
+	PINMUX_IPSR_MSEL(IP6_3_0,	CANFD_CLK_B,	SEL_CANFD0_1),
 	PINMUX_IPSR_GPSR(IP6_3_0,	D7),
-	PINMUX_IPSR_GPSR(IP6_3_0,	MMC_D0),
+	PINMUX_IPSR_GPSR(IP6_3_0,	MMC_D2),
 
 	PINMUX_IPSR_GPSR(IP6_7_4,	VI1_DATA5),
+	PINMUX_IPSR_GPSR(IP6_7_4,	SCK4),
 	PINMUX_IPSR_GPSR(IP6_7_4,	D8),
-	PINMUX_IPSR_GPSR(IP6_7_4,	MMC_D1),
+	PINMUX_IPSR_GPSR(IP6_7_4,	MMC_D3),
 
 	PINMUX_IPSR_GPSR(IP6_11_8,	VI1_DATA6),
+	PINMUX_IPSR_GPSR(IP6_11_8,	RX4),
 	PINMUX_IPSR_GPSR(IP6_11_8,	D9),
-	PINMUX_IPSR_GPSR(IP6_11_8,	MMC_D2),
+	PINMUX_IPSR_GPSR(IP6_11_8,	MMC_CLK),
 
 	PINMUX_IPSR_GPSR(IP6_15_12,	VI1_DATA7),
+	PINMUX_IPSR_GPSR(IP6_15_12,	TX4),
 	PINMUX_IPSR_GPSR(IP6_15_12,	D10),
-	PINMUX_IPSR_GPSR(IP6_15_12,	MMC_D3),
+	PINMUX_IPSR_GPSR(IP6_15_12,	MMC_D4),
 
 	PINMUX_IPSR_GPSR(IP6_19_16,	VI1_DATA8),
+	PINMUX_IPSR_GPSR(IP6_19_16,	CTS4_N),
 	PINMUX_IPSR_GPSR(IP6_19_16,	D11),
-	PINMUX_IPSR_GPSR(IP6_19_16,	MMC_CLK),
+	PINMUX_IPSR_GPSR(IP6_19_16,	MMC_D5),
 
 	PINMUX_IPSR_GPSR(IP6_23_20,	VI1_DATA9),
-	PINMUX_IPSR_MSEL(IP6_23_20,	TCLK1_A, SEL_TMU_0),
+	PINMUX_IPSR_GPSR(IP6_23_20,	RTS4_N),
 	PINMUX_IPSR_GPSR(IP6_23_20,	D12),
-	PINMUX_IPSR_GPSR(IP6_23_20,	MMC_D4),
+	PINMUX_IPSR_GPSR(IP6_23_20,	MMC_D6),
+	PINMUX_IPSR_MSEL(IP6_23_20,	SCL3_B,	SEL_I2C3_1),
 
 	PINMUX_IPSR_GPSR(IP6_27_24,	VI1_DATA10),
-	PINMUX_IPSR_MSEL(IP6_27_24,	TCLK2_A, SEL_TMU_0),
 	PINMUX_IPSR_GPSR(IP6_27_24,	D13),
-	PINMUX_IPSR_GPSR(IP6_27_24,	MMC_D5),
+	PINMUX_IPSR_GPSR(IP6_27_24,	MMC_D7),
+	PINMUX_IPSR_MSEL(IP6_27_24,	SDA3_B,	SEL_I2C3_1),
 
 	PINMUX_IPSR_GPSR(IP6_31_28,	VI1_DATA11),
 	PINMUX_IPSR_GPSR(IP6_31_28,	SCL4),
+	PINMUX_IPSR_GPSR(IP6_31_28,	IRQ4),
 	PINMUX_IPSR_GPSR(IP6_31_28,	D14),
-	PINMUX_IPSR_GPSR(IP6_31_28,	MMC_D6),
 
 	/* IPSR7 */
 	PINMUX_IPSR_GPSR(IP7_3_0,	VI1_FIELD),
 	PINMUX_IPSR_GPSR(IP7_3_0,	SDA4),
+	PINMUX_IPSR_GPSR(IP7_3_0,	IRQ5),
 	PINMUX_IPSR_GPSR(IP7_3_0,	D15),
-	PINMUX_IPSR_GPSR(IP7_3_0,	MMC_D7),
 
 	PINMUX_IPSR_GPSR(IP7_7_4,	SCL0),
+	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR0),
+	PINMUX_IPSR_GPSR(IP7_7_4,	TPU0TO0),
 	PINMUX_IPSR_GPSR(IP7_7_4,	CLKOUT),
+	PINMUX_IPSR_GPSR(IP7_7_4,	MSIOF0_RXD),
 
 	PINMUX_IPSR_GPSR(IP7_11_8,	SDA0),
+	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR1),
+	PINMUX_IPSR_GPSR(IP7_11_8,	TPU0TO1),
 	PINMUX_IPSR_GPSR(IP7_11_8,	BS_N),
 	PINMUX_IPSR_GPSR(IP7_11_8,	SCK0),
-	PINMUX_IPSR_MSEL(IP7_11_8,	HSCK0_B, SEL_HSCIF0_1),
+	PINMUX_IPSR_GPSR(IP7_11_8,	MSIOF0_TXD),
 
 	PINMUX_IPSR_GPSR(IP7_15_12,	SCL1),
+	PINMUX_IPSR_GPSR(IP7_15_12,	DU_DG0),
 	PINMUX_IPSR_GPSR(IP7_15_12,	TPU0TO2),
 	PINMUX_IPSR_GPSR(IP7_15_12,	RD_N),
 	PINMUX_IPSR_GPSR(IP7_15_12,	CTS0_N),
-	PINMUX_IPSR_GPSR(IP7_15_12,	HCTS0_N_B),
+	PINMUX_IPSR_GPSR(IP7_15_12,	MSIOF0_SCK),
 
 	PINMUX_IPSR_GPSR(IP7_19_16,	SDA1),
+	PINMUX_IPSR_GPSR(IP7_19_16,	DU_DG1),
 	PINMUX_IPSR_GPSR(IP7_19_16,	TPU0TO3),
 	PINMUX_IPSR_GPSR(IP7_19_16,	WE0_N),
 	PINMUX_IPSR_GPSR(IP7_19_16,	RTS0_N),
-	PINMUX_IPSR_MSEL(IP1_23_20,	HRTS0_N_B, SEL_HSCIF0_1),
+	PINMUX_IPSR_GPSR(IP7_19_16,	MSIOF0_SYNC),
 
 	PINMUX_IPSR_GPSR(IP7_23_20,	SCL2),
+	PINMUX_IPSR_GPSR(IP7_23_20,	DU_DB0),
+	PINMUX_IPSR_MSEL(IP7_23_20,	TCLK1_A,	SEL_TMU_0),
 	PINMUX_IPSR_GPSR(IP7_23_20,	WE1_N),
 	PINMUX_IPSR_GPSR(IP7_23_20,	RX0),
-	PINMUX_IPSR_MSEL(IP7_23_20,	HRX0_B, SEL_HSCIF0_1),
+	PINMUX_IPSR_GPSR(IP7_23_20,	MSIOF0_SS1),
 
 	PINMUX_IPSR_GPSR(IP7_27_24,	SDA2),
+	PINMUX_IPSR_GPSR(IP7_27_24,	DU_DB1),
+	PINMUX_IPSR_MSEL(IP7_27_24,	TCLK2_A,	SEL_TMU_0),
 	PINMUX_IPSR_GPSR(IP7_27_24,	EX_WAIT0),
 	PINMUX_IPSR_GPSR(IP7_27_24,	TX0),
-	PINMUX_IPSR_MSEL(IP7_27_24,	HTX0_B, SEL_HSCIF0_1),
+	PINMUX_IPSR_GPSR(IP7_27_24,	MSIOF0_SS2),
 
-	PINMUX_IPSR_GPSR(IP7_31_28,	AVB_AVTP_MATCH),
-	PINMUX_IPSR_GPSR(IP7_31_28,	TPU0TO0),
+	PINMUX_IPSR_GPSR(IP7_31_28,	AVB0_AVTP_CAPTURE),
+	PINMUX_IPSR_GPSR(IP7_31_28,	FSCLKST2_N_B),
 
 	/* IPSR8 */
-	PINMUX_IPSR_GPSR(IP8_3_0,	AVB_AVTP_CAPTURE),
-	PINMUX_IPSR_GPSR(IP8_3_0,	TPU0TO1),
+	PINMUX_IPSR_MSEL(IP8_3_0,	CANFD0_TX_A,	SEL_CANFD0_0),
+	PINMUX_IPSR_GPSR(IP8_3_0,	FXR_TXDA),
+	PINMUX_IPSR_MSEL(IP8_3_0,	PWM0_B,		SEL_PWM0_1),
+	PINMUX_IPSR_GPSR(IP8_3_0,	DU_DISP),
+	PINMUX_IPSR_GPSR(IP8_3_0,	FSCLKST2_N_C),
 
-	PINMUX_IPSR_MSEL(IP8_7_4,	CANFD0_TX_A, SEL_CANFD0_0),
-	PINMUX_IPSR_GPSR(IP8_7_4,	FXR_TXDA),
-	PINMUX_IPSR_MSEL(IP8_7_4,	PWM0_B, SEL_PWM0_1),
-	PINMUX_IPSR_GPSR(IP8_7_4,	DU_DISP),
+	PINMUX_IPSR_MSEL(IP8_7_4,	CANFD0_RX_A,	SEL_CANFD0_0),
+	PINMUX_IPSR_GPSR(IP8_7_4,	RXDA_EXTFXR),
+	PINMUX_IPSR_MSEL(IP8_7_4,	PWM1_B,		SEL_PWM1_1),
+	PINMUX_IPSR_GPSR(IP8_7_4,	DU_CDE),
 
-	PINMUX_IPSR_MSEL(IP8_11_8,	CANFD0_RX_A, SEL_CANFD0_0),
-	PINMUX_IPSR_GPSR(IP8_11_8,	RXDA_EXTFXR),
-	PINMUX_IPSR_MSEL(IP8_11_8,	PWM1_B, SEL_PWM1_1),
-	PINMUX_IPSR_GPSR(IP8_11_8,	DU_CDE),
+	PINMUX_IPSR_GPSR(IP8_11_8,	CANFD1_TX),
+	PINMUX_IPSR_GPSR(IP8_11_8,	FXR_TXDB),
+	PINMUX_IPSR_MSEL(IP8_11_8,	PWM2_B,		SEL_PWM2_1),
+	PINMUX_IPSR_MSEL(IP8_11_8,	TCLK1_B,	SEL_TMU_1),
+	PINMUX_IPSR_MSEL(IP8_11_8,	TX1_B,		SEL_SCIF1_1),
 
-	PINMUX_IPSR_GPSR(IP8_15_12,	CANFD1_TX),
-	PINMUX_IPSR_GPSR(IP8_15_12,	FXR_TXDB),
-	PINMUX_IPSR_MSEL(IP8_15_12,	PWM2_B, SEL_PWM2_1),
-	PINMUX_IPSR_MSEL(IP8_15_12,	TCLK1_B, SEL_TMU_1),
-	PINMUX_IPSR_MSEL(IP8_15_12,	TX1_B, SEL_SCIF1_1),
+	PINMUX_IPSR_GPSR(IP8_15_12,	CANFD1_RX),
+	PINMUX_IPSR_GPSR(IP8_15_12,	RXDB_EXTFXR),
+	PINMUX_IPSR_MSEL(IP8_15_12,	PWM3_B,		SEL_PWM3_1),
+	PINMUX_IPSR_MSEL(IP8_15_12,	TCLK2_B,	SEL_TMU_1),
+	PINMUX_IPSR_MSEL(IP8_15_12,	RX1_B,		SEL_SCIF1_1),
 
-	PINMUX_IPSR_GPSR(IP8_19_16,	CANFD1_RX),
-	PINMUX_IPSR_GPSR(IP8_19_16,	RXDB_EXTFXR),
-	PINMUX_IPSR_MSEL(IP8_19_16,	PWM3_B, SEL_PWM3_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	TCLK2_B, SEL_TMU_1),
-	PINMUX_IPSR_MSEL(IP8_19_16,	RX1_B, SEL_SCIF1_1),
+	PINMUX_IPSR_MSEL(IP8_19_16,	CANFD_CLK_A,	SEL_CANFD0_0),
+	PINMUX_IPSR_GPSR(IP8_19_16,	CLK_EXTFXR),
+	PINMUX_IPSR_MSEL(IP8_19_16,	PWM4_B,		SEL_PWM4_1),
+	PINMUX_IPSR_MSEL(IP8_19_16,	SPEEDIN_B,	SEL_RSP_1),
+	PINMUX_IPSR_MSEL(IP8_19_16,	SCIF_CLK_B,	SEL_HSCIF0_1),
 
-	PINMUX_IPSR_MSEL(IP8_23_20,	CANFD_CLK_A, SEL_CANFD0_0),
-	PINMUX_IPSR_GPSR(IP8_23_20,	CLK_EXTFXR),
-	PINMUX_IPSR_MSEL(IP8_23_20,	PWM4_B, SEL_PWM4_1),
-	PINMUX_IPSR_MSEL(IP8_23_20,	SPEEDIN_B, SEL_RSP_1),
-	PINMUX_IPSR_MSEL(IP8_23_20,	SCIF_CLK_B, SEL_HSCIF0_1),
+	PINMUX_IPSR_GPSR(IP8_23_20,	DIGRF_CLKIN),
+	PINMUX_IPSR_GPSR(IP8_23_20,	DIGRF_CLKEN_IN),
 
-	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKIN),
-	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKEN_IN),
-
-	PINMUX_IPSR_GPSR(IP8_31_28,	DIGRF_CLKOUT),
-	PINMUX_IPSR_GPSR(IP8_31_28,	DIGRF_CLKEN_OUT),
-
-	/* IPSR9 */
-	PINMUX_IPSR_GPSR(IP9_3_0,	IRQ4),
-	PINMUX_IPSR_GPSR(IP9_3_0,	VI0_DATA12),
-
-	PINMUX_IPSR_GPSR(IP9_7_4,	IRQ5),
-	PINMUX_IPSR_GPSR(IP9_7_4,	VI0_DATA13),
-
-	PINMUX_IPSR_GPSR(IP9_11_8,	MSIOF0_RXD),
-	PINMUX_IPSR_GPSR(IP9_11_8,	DU_DR0),
-	PINMUX_IPSR_GPSR(IP9_11_8,	VI0_DATA14),
-
-	PINMUX_IPSR_GPSR(IP9_15_12,	MSIOF0_TXD),
-	PINMUX_IPSR_GPSR(IP9_15_12,	DU_DR1),
-	PINMUX_IPSR_GPSR(IP9_15_12,	VI0_DATA15),
-
-	PINMUX_IPSR_GPSR(IP9_19_16,	MSIOF0_SCK),
-	PINMUX_IPSR_GPSR(IP9_19_16,	DU_DG0),
-	PINMUX_IPSR_GPSR(IP9_19_16,	VI0_DATA16),
-
-	PINMUX_IPSR_GPSR(IP9_23_20,	MSIOF0_SYNC),
-	PINMUX_IPSR_GPSR(IP9_23_20,	DU_DG1),
-	PINMUX_IPSR_GPSR(IP9_23_20,	VI0_DATA17),
-
-	PINMUX_IPSR_GPSR(IP9_27_24,	MSIOF0_SS1),
-	PINMUX_IPSR_GPSR(IP9_27_24,	DU_DB0),
-	PINMUX_IPSR_GPSR(IP9_27_24,	TCLK3),
-	PINMUX_IPSR_GPSR(IP9_27_24,	VI0_DATA18),
-
-	PINMUX_IPSR_GPSR(IP9_31_28,	MSIOF0_SS2),
-	PINMUX_IPSR_GPSR(IP9_31_28,	DU_DB1),
-	PINMUX_IPSR_GPSR(IP9_31_28,	TCLK4),
-	PINMUX_IPSR_GPSR(IP9_31_28,	VI0_DATA19),
-
-	/* IPSR10 */
-	PINMUX_IPSR_GPSR(IP10_3_0,	SCL3),
-	PINMUX_IPSR_GPSR(IP10_3_0,	VI0_DATA20),
-
-	PINMUX_IPSR_GPSR(IP10_7_4,	SDA3),
-	PINMUX_IPSR_GPSR(IP10_7_4,	VI0_DATA21),
-
-	PINMUX_IPSR_GPSR(IP10_11_8,	FSO_CFE_0_N),
-	PINMUX_IPSR_GPSR(IP10_11_8,	VI0_DATA22),
-
-	PINMUX_IPSR_GPSR(IP10_15_12,	FSO_CFE_1_N),
-	PINMUX_IPSR_GPSR(IP10_15_12,	VI0_DATA23),
-
-	PINMUX_IPSR_GPSR(IP10_19_16,	FSO_TOE_N),
+	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKOUT),
+	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKEN_OUT),
 };
 
 static const struct sh_pfc_pin pinmux_pins[] = {
 	PINMUX_GPIO_GP_ALL(),
 };
 
-/* - AVB -------------------------------------------------------------------- */
-static const unsigned int avb_link_pins[] = {
-	/* AVB_LINK */
+/* - AVB0 ------------------------------------------------------------------- */
+static const unsigned int avb0_link_pins[] = {
+	/* AVB0_LINK */
 	RCAR_GP_PIN(1, 18),
 };
-static const unsigned int avb_link_mux[] = {
-	AVB_LINK_MARK,
+static const unsigned int avb0_link_mux[] = {
+	AVB0_LINK_MARK,
 };
-static const unsigned int avb_magic_pins[] = {
-	/* AVB_MAGIC */
+static const unsigned int avb0_magic_pins[] = {
+	/* AVB0_MAGIC */
 	RCAR_GP_PIN(1, 16),
 };
-static const unsigned int avb_magic_mux[] = {
-	AVB_MAGIC_MARK,
+static const unsigned int avb0_magic_mux[] = {
+	AVB0_MAGIC_MARK,
 };
-static const unsigned int avb_phy_int_pins[] = {
-	/* AVB_PHY_INT */
+static const unsigned int avb0_phy_int_pins[] = {
+	/* AVB0_PHY_INT */
 	RCAR_GP_PIN(1, 17),
 };
-static const unsigned int avb_phy_int_mux[] = {
-	AVB_PHY_INT_MARK,
+static const unsigned int avb0_phy_int_mux[] = {
+	AVB0_PHY_INT_MARK,
 };
-static const unsigned int avb_mdio_pins[] = {
-	/* AVB_MDC, AVB_MDIO */
+static const unsigned int avb0_mdio_pins[] = {
+	/* AVB0_MDC, AVB0_MDIO */
 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
 };
-static const unsigned int avb_mdio_mux[] = {
-	AVB_MDC_MARK, AVB_MDIO_MARK,
+static const unsigned int avb0_mdio_mux[] = {
+	AVB0_MDC_MARK, AVB0_MDIO_MARK,
 };
-static const unsigned int avb_rgmii_pins[] = {
+static const unsigned int avb0_rgmii_pins[] = {
 	/*
-	 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
-	 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
+	 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
+	 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
 	 */
 	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
 	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
···
 	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
 	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
 };
-static const unsigned int avb_rgmii_mux[] = {
-	AVB_TX_CTL_MARK, AVB_TXC_MARK,
-	AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
-	AVB_RX_CTL_MARK, AVB_RXC_MARK,
-	AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
+static const unsigned int avb0_rgmii_mux[] = {
+	AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
+	AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
+	AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
+	AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
 };
-static const unsigned int avb_txcrefclk_pins[] = {
-	/* AVB_TXCREFCLK */
+static const unsigned int avb0_txcrefclk_pins[] = {
+	/* AVB0_TXCREFCLK */
 	RCAR_GP_PIN(1, 13),
 };
-static const unsigned int avb_txcrefclk_mux[] = {
-	AVB_TXCREFCLK_MARK,
+static const unsigned int avb0_txcrefclk_mux[] = {
+	AVB0_TXCREFCLK_MARK,
 };
-static const unsigned int avb_avtp_pps_pins[] = {
-	/* AVB_AVTP_PPS */
+static const unsigned int avb0_avtp_pps_pins[] = {
+	/* AVB0_AVTP_PPS */
 	RCAR_GP_PIN(2, 6),
 };
-static const unsigned int avb_avtp_pps_mux[] = {
-	AVB_AVTP_PPS_MARK,
+static const unsigned int avb0_avtp_pps_mux[] = {
+	AVB0_AVTP_PPS_MARK,
 };
-static const unsigned int avb_avtp_capture_pins[] = {
-	/* AVB_AVTP_CAPTURE */
+static const unsigned int avb0_avtp_capture_pins[] = {
+	/* AVB0_AVTP_CAPTURE */
 	RCAR_GP_PIN(1, 20),
 };
-static const unsigned int avb_avtp_capture_mux[] = {
-	AVB_AVTP_CAPTURE_MARK,
+static const unsigned int avb0_avtp_capture_mux[] = {
+	AVB0_AVTP_CAPTURE_MARK,
 };
-static const unsigned int avb_avtp_match_pins[] = {
-	/* AVB_AVTP_MATCH */
+static const unsigned int avb0_avtp_match_pins[] = {
+	/* AVB0_AVTP_MATCH */
 	RCAR_GP_PIN(1, 19),
 };
-static const unsigned int avb_avtp_match_mux[] = {
-	AVB_AVTP_MATCH_MARK,
-};
-
-/* - CANFD0 ----------------------------------------------------------------- */
-static const unsigned int canfd0_data_a_pins[] = {
-	/* CANFD0_TX, CANFD0_RX */
-	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
-};
-static const unsigned int canfd0_data_a_mux[] = {
-	CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
-};
-static const unsigned int canfd0_data_b_pins[] = {
-	/* CANFD0_TX, CANFD0_RX */
-	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
-};
-static const unsigned int canfd0_data_b_mux[] = {
-	CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
-};
-
-/* - CANFD1 ----------------------------------------------------------------- */
-static const unsigned int canfd1_data_pins[] = {
-	/* CANFD1_TX, CANFD1_RX */
-	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
-};
-static const unsigned int canfd1_data_mux[] = {
-	CANFD1_TX_MARK, CANFD1_RX_MARK,
+static const unsigned int avb0_avtp_match_mux[] = {
+	AVB0_AVTP_MATCH_MARK,
 };
 
 /* - CANFD Clock ------------------------------------------------------------ */
···
 	CANFD_CLK_B_MARK,
 };
 
+/* - CANFD0 ----------------------------------------------------------------- */
+static const unsigned int canfd0_data_a_pins[] = {
+	/* TX, RX */
+	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int canfd0_data_a_mux[] = {
+	CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
+};
+static const unsigned int canfd0_data_b_pins[] = {
+	/* TX, RX */
+	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int canfd0_data_b_mux[] = {
+	CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
+};
+
+/* - CANFD1 ----------------------------------------------------------------- */
+static const unsigned int canfd1_data_pins[] = {
+	/* TX, RX */
+	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
+};
+static const unsigned int canfd1_data_mux[] = {
+	CANFD1_TX_MARK, CANFD1_RX_MARK,
+};
+
 /* - DU --------------------------------------------------------------------- */
 static const unsigned int du_rgb666_pins[] = {
-	/* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
+	/* R[7:2], G[7:2], B[7:2] */
 	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
···
 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
 	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
 };
-static const unsigned int du_rgb888_pins[] = {
-	/* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
-	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
-	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
-	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
-	RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
-	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
-	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
-	RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
-};
-static const unsigned int du_rgb888_mux[] = {
-	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
-	DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
-	DU_DR1_MARK, DU_DR0_MARK,
-	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
-	DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
-	DU_DG1_MARK, DU_DG0_MARK,
-	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
-	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
-	DU_DB1_MARK, DU_DB0_MARK,
-};
 static const unsigned int du_clk_out_pins[] = {
-	/* DU_DOTCLKOUT */
+	/* DOTCLKOUT */
 	RCAR_GP_PIN(0, 18),
 };
 static const unsigned int du_clk_out_mux[] = {
 	DU_DOTCLKOUT_MARK,
 };
 static const unsigned int du_sync_pins[] = {
-	/* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
+	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 };
 static const unsigned int du_sync_mux[] = {
-	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
+	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
 };
 static const unsigned int du_oddf_pins[] = {
-	/* DU_EXODDF/DU_ODDF/DISP/CDE */
+	/* EXODDF/ODDF/DISP/CDE */
 	RCAR_GP_PIN(0, 21),
 };
 static const unsigned int du_oddf_mux[] = {
 	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
 };
 static const unsigned int du_cde_pins[] = {
-	/* DU_CDE */
+	/* CDE */
 	RCAR_GP_PIN(1, 22),
 };
 static const unsigned int du_cde_mux[] = {
 	DU_CDE_MARK,
 };
 static const unsigned int du_disp_pins[] = {
-	/* DU_DISP */
+	/* DISP */
 	RCAR_GP_PIN(1, 21),
 };
 static const unsigned int du_disp_mux[] = {
 	DU_DISP_MARK,
 };
 
-/* - GETHER ----------------------------------------------------------------- */
-static const unsigned int gether_link_a_pins[] = {
-	/* GETHER_LINK */
-	RCAR_GP_PIN(4, 24),
-};
-static const unsigned int gether_link_a_mux[] = {
-	GETHER_LINK_A_MARK,
-};
-static const unsigned int gether_phy_int_a_pins[] = {
-	/* GETHER_PHY_INT */
-	RCAR_GP_PIN(4, 23),
-};
-static const unsigned int gether_phy_int_a_mux[] = {
-	GETHER_PHY_INT_A_MARK,
-};
-static const unsigned int gether_mdio_a_pins[] = {
-	/* GETHER_MDC, GETHER_MDIO */
-	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
-};
-static const unsigned int gether_mdio_a_mux[] = {
-	GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
-};
-static const unsigned int gether_link_b_pins[] = {
-	/* GETHER_LINK */
-	RCAR_GP_PIN(0, 18),
-};
-static const unsigned int gether_link_b_mux[] = {
-	GETHER_LINK_B_MARK,
-};
-static const unsigned int gether_phy_int_b_pins[] = {
-	/* GETHER_PHY_INT */
-	RCAR_GP_PIN(0, 19),
-};
-static const unsigned int gether_phy_int_b_mux[] = {
-	GETHER_PHY_INT_B_MARK,
-};
-static const unsigned int gether_mdio_b_mux[] = {
-	GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
-};
-static const unsigned int gether_mdio_b_pins[] = {
-	/* GETHER_MDC, GETHER_MDIO */
-	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
-};
-static const unsigned int gether_magic_pins[] = {
-	/* GETHER_MAGIC */
-	RCAR_GP_PIN(4, 22),
-};
-static const unsigned int gether_magic_mux[] = {
-	GETHER_MAGIC_MARK,
-};
-static const unsigned int gether_rgmii_pins[] = {
-	/*
-	 * GETHER_TX_CTL, GETHER_TXC,
-	 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
-	 * GETHER_RX_CTL, GETHER_RXC,
-	 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
-	 */
-	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
-	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
-	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
-	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
-	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
-	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
-};
-static const unsigned int gether_rgmii_mux[] = {
-	GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
-	GETHER_TD0_MARK, GETHER_TD1_MARK,
-	GETHER_TD2_MARK, GETHER_TD3_MARK,
-	GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
-	GETHER_RD0_MARK, AVB_RD1_MARK,
-	GETHER_RD2_MARK, AVB_RD3_MARK,
-};
-static const unsigned int gether_txcrefclk_pins[] = {
-	/* GETHER_TXCREFCLK */
-	RCAR_GP_PIN(4, 18),
-};
-static const unsigned int gether_txcrefclk_mux[] = {
-	GETHER_TXCREFCLK_MARK,
-};
-static const unsigned int gether_txcrefclk_mega_pins[] = {
-	/* GETHER_TXCREFCLK_MEGA */
-	RCAR_GP_PIN(4, 19),
-};
-static const unsigned int gether_txcrefclk_mega_mux[] = {
-	GETHER_TXCREFCLK_MEGA_MARK,
-};
-static const unsigned int gether_rmii_pins[] = {
-	/*
-	 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
-	 * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
-	 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
-	 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
-	 */
-	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
-	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
-	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
-};
-static const unsigned int gether_rmii_mux[] = {
-	GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
-	GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
-	GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
-	GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
-};
-
 /* - HSCIF0 ----------------------------------------------------------------- */
-static const unsigned int hscif0_data_a_pins[] = {
-	/* HRX0, HTX0 */
-	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
+static const unsigned int hscif0_data_pins[] = {
+	/* HRX, HTX */
+	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
 };
-static const unsigned int hscif0_data_a_mux[] = {
-	HRX0_A_MARK, HTX0_A_MARK,
+static const unsigned int hscif0_data_mux[] = {
+	HRX0_MARK, HTX0_MARK,
 };
-static const unsigned int hscif0_clk_a_pins[] = {
-	/* HSCK0 */
-	RCAR_GP_PIN(0, 12),
+static const unsigned int hscif0_clk_pins[] = {
+	/* HSCK */
+	RCAR_GP_PIN(0, 0),
 };
-static const unsigned int hscif0_clk_a_mux[] = {
-	HSCK0_A_MARK,
+static const unsigned int hscif0_clk_mux[] = {
+	HSCK0_MARK,
 };
-static const unsigned int hscif0_ctrl_a_pins[] = {
-	/* HRTS0#, HCTS0# */
-	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
+static const unsigned int hscif0_ctrl_pins[] = {
+	/* HRTS#, HCTS# */
+	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
 };
-static const unsigned int hscif0_ctrl_a_mux[] = {
-	HRTS0_N_A_MARK, HCTS0_N_A_MARK,
-};
-static const unsigned int hscif0_data_b_pins[] = {
-	/* HRX0, HTX0 */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int hscif0_data_b_mux[] = {
-	HRX0_B_MARK, HTX0_B_MARK,
-};
-static const unsigned int hscif0_clk_b_pins[] = {
-	/* HSCK0 */
-	RCAR_GP_PIN(4, 1),
-};
-static const unsigned int hscif0_clk_b_mux[] = {
-	HSCK0_B_MARK,
-};
-static const unsigned int hscif0_ctrl_b_pins[] = {
-	/* HRTS0#, HCTS0# */
-	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
-};
-static const unsigned int hscif0_ctrl_b_mux[] = {
-	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
+static const unsigned int hscif0_ctrl_mux[] = {
+	HRTS0_N_MARK, HCTS0_N_MARK,
 };
 
 /* - HSCIF1 ----------------------------------------------------------------- */
 static const unsigned int hscif1_data_pins[] = {
-	/* HRX1, HTX1 */
+	/* HRX, HTX */
 	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
 };
 static const unsigned int hscif1_data_mux[] = {
 	HRX1_MARK, HTX1_MARK,
 };
 static const unsigned int hscif1_clk_pins[] = {
-	/* HSCK1 */
+	/* HSCK */
 	RCAR_GP_PIN(2, 7),
 };
 static const unsigned int hscif1_clk_mux[] = {
 	HSCK1_MARK,
 };
 static const unsigned int hscif1_ctrl_pins[] = {
-	/* HRTS1#, HCTS1# */
+	/* HRTS#, HCTS# */
 	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
 };
 static const unsigned int hscif1_ctrl_mux[] = {
···
 
 /* - HSCIF2 ----------------------------------------------------------------- */
 static const unsigned int hscif2_data_pins[] = {
-	/* HRX2, HTX2 */
+	/* HRX, HTX */
 	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
 };
 static const unsigned int hscif2_data_mux[] = {
 	HRX2_MARK, HTX2_MARK,
 };
 static const unsigned int hscif2_clk_pins[] = {
-	/* HSCK2 */
+	/* HSCK */
 	RCAR_GP_PIN(2, 12),
 };
 static const unsigned int hscif2_clk_mux[] = {
 	HSCK2_MARK,
 };
 static const unsigned int hscif2_ctrl_pins[] = {
-	/* HRTS2#, HCTS2# */
+	/* HRTS#, HCTS# */
 	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
 };
 static const unsigned int hscif2_ctrl_mux[] = {
···
 
 /* - HSCIF3 ----------------------------------------------------------------- */
 static const unsigned int hscif3_data_pins[] = {
-	/* HRX3, HTX3 */
+	/* HRX, HTX */
 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
 };
 static const unsigned int hscif3_data_mux[] = {
 	HRX3_MARK, HTX3_MARK,
 };
 static const unsigned int hscif3_clk_pins[] = {
-	/* HSCK3 */
+	/* HSCK */
 	RCAR_GP_PIN(2, 0),
 };
 static const unsigned int hscif3_clk_mux[] = {
 	HSCK3_MARK,
 };
 static const unsigned int hscif3_ctrl_pins[] = {
-	/* HRTS3#, HCTS3# */
+	/* HRTS#, HCTS# */
 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
 };
 static const unsigned int hscif3_ctrl_mux[] = {
···
 
 /* - I2C0 ------------------------------------------------------------------- */
 static const unsigned int i2c0_pins[] = {
-	/* SDA0, SCL0 */
+	/* SDA, SCL */
 	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
 };
 static const unsigned int i2c0_mux[] = {
···
 
 /* - I2C1 ------------------------------------------------------------------- */
 static const unsigned int i2c1_pins[] = {
-	/* SDA1, SCL1 */
+	/* SDA, SCL */
 	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
 };
 static const unsigned int i2c1_mux[] = {
···
 
 /* - I2C2 ------------------------------------------------------------------- */
 static const unsigned int i2c2_pins[] = {
-	/* SDA2, SCL2 */
+	/* SDA, SCL */
 	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
 };
 static const unsigned int i2c2_mux[] = {
···
 };
 
 /* - I2C3 ------------------------------------------------------------------- */
-static const unsigned int i2c3_pins[] = {
-	/* SDA3, SCL3 */
-	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
+static const unsigned int i2c3_a_pins[] = {
+	/* SDA, SCL */
+	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
 };
-static const unsigned int i2c3_mux[] = {
-	SDA3_MARK, SCL3_MARK,
+static const unsigned int i2c3_a_mux[] = {
+	SDA3_A_MARK, SCL3_A_MARK,
+};
+static const unsigned int i2c3_b_pins[] = {
+	/* SDA, SCL */
+	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int i2c3_b_mux[] = {
+	SDA3_B_MARK, SCL3_B_MARK,
 };
 
 /* - I2C4 ------------------------------------------------------------------- */
 static const unsigned int i2c4_pins[] = {
-	/* SDA4, SCL4 */
+	/* SDA, SCL */
 	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
 };
 static const unsigned int i2c4_mux[] = {
 	SDA4_MARK, SCL4_MARK,
-};
-
-/* - I2C5 ------------------------------------------------------------------- */
-static const unsigned int i2c5_pins[] = {
-	/* SDA5, SCL5 */
-	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
-};
-static const unsigned int i2c5_mux[] = {
-	SDA5_MARK, SCL5_MARK,
 };
 
 /* - INTC-EX ---------------------------------------------------------------- */
···
 };
 static const unsigned int intc_ex_irq1_pins[] = {
 	/* IRQ1 */
-	RCAR_GP_PIN(0, 12),
+	RCAR_GP_PIN(0, 11),
 };
 static const unsigned int intc_ex_irq1_mux[] = {
 	IRQ1_MARK,
 };
 static const unsigned int intc_ex_irq2_pins[] = {
 	/* IRQ2 */
-	RCAR_GP_PIN(0, 13),
+	RCAR_GP_PIN(0, 12),
 };
 static const unsigned int intc_ex_irq2_mux[] = {
 	IRQ2_MARK,
 };
 static const unsigned int intc_ex_irq3_pins[] = {
 	/* IRQ3 */
-	RCAR_GP_PIN(0, 14),
+	RCAR_GP_PIN(0, 19),
 };
 static const unsigned int intc_ex_irq3_mux[] = {
 	IRQ3_MARK,
 };
 static const unsigned int intc_ex_irq4_pins[] = {
 	/* IRQ4 */
-	RCAR_GP_PIN(2, 17),
+	RCAR_GP_PIN(3, 15),
 };
 static const unsigned int intc_ex_irq4_mux[] = {
 	IRQ4_MARK,
 };
 static const unsigned int intc_ex_irq5_pins[] = {
 	/* IRQ5 */
-	RCAR_GP_PIN(2, 18),
+	RCAR_GP_PIN(3, 16),
 };
 static const unsigned int intc_ex_irq5_mux[] = {
 	IRQ5_MARK,
···
 
 /* - MMC -------------------------------------------------------------------- */
 static const unsigned int mmc_data1_pins[] = {
-	/* MMC_D0 */
-	RCAR_GP_PIN(3, 8),
+	/* D0 */
+	RCAR_GP_PIN(3, 6),
 };
 static const unsigned int mmc_data1_mux[] = {
 	MMC_D0_MARK,
 };
 static const unsigned int mmc_data4_pins[] = {
-	/* MMC_D[0:3] */
+	/* D[0:3] */
+	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
 	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
 };
 static const unsigned int mmc_data4_mux[] = {
 	MMC_D0_MARK, MMC_D1_MARK,
 	MMC_D2_MARK, MMC_D3_MARK,
 };
 static const unsigned int mmc_data8_pins[] = {
-	/* MMC_D[0:7] */
+	/* D[0:7] */
+	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
 	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
-	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
-	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
 };
 static const unsigned int mmc_data8_mux[] = {
 	MMC_D0_MARK, MMC_D1_MARK,
···
 	MMC_D6_MARK, MMC_D7_MARK,
 };
 static const unsigned int mmc_ctrl_pins[] = {
-	/* MMC_CLK, MMC_CMD */
-	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
+	/* CLK, CMD */
+	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
 };
 static const unsigned int mmc_ctrl_mux[] = {
 	MMC_CLK_MARK, MMC_CMD_MARK,
 };
-static const unsigned int mmc_cd_pins[] = {
-	/* MMC_CD */
-	RCAR_GP_PIN(3, 5),
-};
-static const unsigned int mmc_cd_mux[] = {
-	MMC_CD_MARK,
-};
-static const unsigned int mmc_wp_pins[] = {
-	/* MMC_WP */
-	RCAR_GP_PIN(3, 4),
-};
-static const unsigned int mmc_wp_mux[] = {
-	MMC_WP_MARK,
-};
-static const unsigned int mmc_ds_pins[] = {
-	/* MMC_DS */
-	RCAR_GP_PIN(3, 6),
-};
-static const unsigned int mmc_ds_mux[] = {
-	MMC_DS_MARK,
-};
 
 /* - MSIOF0 ----------------------------------------------------------------- */
 static const unsigned int msiof0_clk_pins[] = {
-	/* MSIOF0_SCK */
-	RCAR_GP_PIN(2, 21),
+	/* SCK */
+	RCAR_GP_PIN(4, 2),
 };
 static const unsigned int msiof0_clk_mux[] = {
 	MSIOF0_SCK_MARK,
 };
 static const unsigned int msiof0_sync_pins[] = {
-	/* MSIOF0_SYNC */
-	RCAR_GP_PIN(2, 22),
+	/* SYNC */
+	RCAR_GP_PIN(4, 3),
 };
 static const unsigned int msiof0_sync_mux[] = {
 	MSIOF0_SYNC_MARK,
 };
 static const unsigned int msiof0_ss1_pins[] = {
-	/* MSIOF0_SS1 */
-	RCAR_GP_PIN(2, 23),
+	/* SS1 */
+	RCAR_GP_PIN(4, 4),
 };
 static const unsigned int msiof0_ss1_mux[] = {
 	MSIOF0_SS1_MARK,
 };
 static const unsigned int msiof0_ss2_pins[] = {
-	/* MSIOF0_SS2 */
-	RCAR_GP_PIN(2, 24),
+	/* SS2 */
+	RCAR_GP_PIN(4, 5),
 };
 static const unsigned int msiof0_ss2_mux[] = {
 	MSIOF0_SS2_MARK,
 };
 static const unsigned int msiof0_txd_pins[] = {
-	/* MSIOF0_TXD */
-	RCAR_GP_PIN(2, 20),
+	/* TXD */
+	RCAR_GP_PIN(4, 1),
 };
 static const unsigned int msiof0_txd_mux[] = {
 	MSIOF0_TXD_MARK,
 };
 static const unsigned int msiof0_rxd_pins[] = {
-	/* MSIOF0_RXD */
-	RCAR_GP_PIN(2, 19),
+	/* RXD */
+	RCAR_GP_PIN(4, 0),
 };
 static const unsigned int msiof0_rxd_mux[] = {
 	MSIOF0_RXD_MARK,
···
 
 /* - MSIOF1 ----------------------------------------------------------------- */
 static const unsigned int msiof1_clk_pins[] = {
-	/* MSIOF1_SCK */
+	/* SCK */
 	RCAR_GP_PIN(3, 2),
 };
 static const unsigned int msiof1_clk_mux[] = {
 	MSIOF1_SCK_MARK,
 };
 static const unsigned int msiof1_sync_pins[] = {
-	/* MSIOF1_SYNC */
+	/* SYNC */
 	RCAR_GP_PIN(3, 3),
 };
 static const unsigned int msiof1_sync_mux[] = {
 	MSIOF1_SYNC_MARK,
 };
 static const unsigned int msiof1_ss1_pins[] = {
-	/* MSIOF1_SS1 */
+	/* SS1 */
 	RCAR_GP_PIN(3, 4),
 };
 static const unsigned int msiof1_ss1_mux[] = {
 	MSIOF1_SS1_MARK,
 };
 static const unsigned int msiof1_ss2_pins[] = {
-	/* MSIOF1_SS2 */
+	/* SS2 */
 	RCAR_GP_PIN(3, 5),
 };
 static const unsigned int msiof1_ss2_mux[] = {
 	MSIOF1_SS2_MARK,
 };
 static const unsigned int msiof1_txd_pins[] = {
-	/* MSIOF1_TXD */
+	/* TXD */
 	RCAR_GP_PIN(3, 1),
 };
 static const unsigned int msiof1_txd_mux[] = {
 	MSIOF1_TXD_MARK,
 };
 static const unsigned int msiof1_rxd_pins[] = {
-	/* MSIOF1_RXD */
+	/* RXD */
 	RCAR_GP_PIN(3, 0),
 };
 static const unsigned int msiof1_rxd_mux[] = {
···
 
 /* - MSIOF2 ----------------------------------------------------------------- */
 static const unsigned int msiof2_clk_pins[] = {
-	/* MSIOF2_SCK */
+	/* SCK */
 	RCAR_GP_PIN(2, 0),
 };
 static const unsigned int msiof2_clk_mux[] = {
 	MSIOF2_SCK_MARK,
 };
 static const unsigned int msiof2_sync_pins[] = {
-	/* MSIOF2_SYNC */
+	/* SYNC */
 	RCAR_GP_PIN(2, 3),
 };
 static const unsigned int msiof2_sync_mux[] = {
 	MSIOF2_SYNC_MARK,
 };
 static const unsigned int msiof2_ss1_pins[] = {
-	/* MSIOF2_SS1 */
+	/* SS1 */
 	RCAR_GP_PIN(2, 4),
 };
 static const unsigned int msiof2_ss1_mux[] = {
 	MSIOF2_SS1_MARK,
 };
 static const unsigned int msiof2_ss2_pins[] = {
-	/* MSIOF2_SS2 */
+	/* SS2 */
 	RCAR_GP_PIN(2, 5),
 };
 static const unsigned int msiof2_ss2_mux[] = {
 	MSIOF2_SS2_MARK,
 };
 static const unsigned int msiof2_txd_pins[] = {
-	/* MSIOF2_TXD */
+	/* TXD */
 	RCAR_GP_PIN(2, 2),
 };
 static const unsigned int msiof2_txd_mux[] = {
 	MSIOF2_TXD_MARK,
 };
 static const unsigned int msiof2_rxd_pins[] = {
-	/* MSIOF2_RXD */
+	/* RXD */
 	RCAR_GP_PIN(2, 1),
 };
 static const unsigned int msiof2_rxd_mux[] = {
···
 
 /* - MSIOF3 ----------------------------------------------------------------- */
 static const unsigned int msiof3_clk_pins[] = {
-	/* MSIOF3_SCK */
+	/* SCK */
 	RCAR_GP_PIN(0, 20),
 };
 static const unsigned int msiof3_clk_mux[] = {
 	MSIOF3_SCK_MARK,
 };
 static const unsigned int msiof3_sync_pins[] = {
-	/* MSIOF3_SYNC */
+	/* SYNC */
 	RCAR_GP_PIN(0, 21),
 };
 static const unsigned int msiof3_sync_mux[] = {
 	MSIOF3_SYNC_MARK,
 };
 static const unsigned int msiof3_ss1_pins[] = {
-	/* MSIOF3_SS1 */
-	RCAR_GP_PIN(0, 18),
+	/* SS1 */
+	RCAR_GP_PIN(0, 6),
 };
 static const unsigned int msiof3_ss1_mux[] = {
 	MSIOF3_SS1_MARK,
 };
 static const unsigned int msiof3_ss2_pins[] = {
-	/* MSIOF3_SS2 */
-	RCAR_GP_PIN(0, 19),
+	/* SS2 */
+	RCAR_GP_PIN(0, 7),
 };
 static const unsigned int msiof3_ss2_mux[] = {
 	MSIOF3_SS2_MARK,
 };
 static const unsigned int msiof3_txd_pins[] = {
-	/* MSIOF3_TXD */
-	RCAR_GP_PIN(0, 17),
+	/* TXD */
+	RCAR_GP_PIN(0, 5),
 };
 static const unsigned int msiof3_txd_mux[] = {
 	MSIOF3_TXD_MARK,
 };
 static const unsigned int msiof3_rxd_pins[] = {
-	/* MSIOF3_RXD */
-	RCAR_GP_PIN(0, 16),
+	/* RXD */
+	RCAR_GP_PIN(0, 4),
 };
 static const unsigned int msiof3_rxd_mux[] = {
 	MSIOF3_RXD_MARK,
···
 
 /* - PWM0 ------------------------------------------------------------------- */
 static const unsigned int pwm0_a_pins[] = {
-	/* PWM0 */
-	RCAR_GP_PIN(0, 15),
+	RCAR_GP_PIN(2, 12),
 };
 static const unsigned int pwm0_a_mux[] = {
 	PWM0_A_MARK,
 };
 static const unsigned int pwm0_b_pins[] = {
-	/* PWM0 */
 	RCAR_GP_PIN(1, 21),
 };
 static const unsigned int pwm0_b_mux[] = {
···
 
 /* - PWM1 ------------------------------------------------------------------- */
 static const unsigned int pwm1_a_pins[] = {
-	/* PWM1 */
 	RCAR_GP_PIN(2, 13),
 };
 static const unsigned int pwm1_a_mux[] = {
 	PWM1_A_MARK,
 };
 static const unsigned int pwm1_b_pins[] = {
-	/* PWM1 */
 	RCAR_GP_PIN(1, 22),
 };
 static const unsigned int pwm1_b_mux[] = {
···
 
 /* - PWM2 ------------------------------------------------------------------- */
 static const unsigned int pwm2_a_pins[] = {
-	/* PWM2 */
 	RCAR_GP_PIN(2, 14),
 };
 static const unsigned int pwm2_a_mux[] = {
 	PWM2_A_MARK,
 };
 static const unsigned int pwm2_b_pins[] = {
-	/* PWM2 */
 	RCAR_GP_PIN(1, 23),
 };
 static const unsigned int pwm2_b_mux[] = {
···
 
 /* - PWM3 ------------------------------------------------------------------- */
 static const unsigned int pwm3_a_pins[] = {
-	/* PWM3 */
 	RCAR_GP_PIN(2, 15),
 };
 static const unsigned int pwm3_a_mux[] = {
 	PWM3_A_MARK,
 };
 static const unsigned int pwm3_b_pins[] = {
-	/* PWM3 */
 	RCAR_GP_PIN(1, 24),
 };
 static const unsigned int pwm3_b_mux[] = {
···
 
 /* - PWM4 ------------------------------------------------------------------- */
 static const unsigned int pwm4_a_pins[] = {
-	/* PWM4 */
 	RCAR_GP_PIN(2, 16),
 };
 static const unsigned int pwm4_a_mux[] = {
 	PWM4_A_MARK,
 };
 static const unsigned int pwm4_b_pins[] = {
-	/* PWM4 */
 	RCAR_GP_PIN(1, 25),
 };
 static const unsigned int pwm4_b_mux[] = {
···
 	RPC_WP_N_MARK,
 };
 
-/* - SCIF0 ------------------------------------------------------------------ */
-static const unsigned int scif0_data_pins[] = {
-	/* RX0, TX0 */
-	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int scif0_data_mux[] = {
-	RX0_MARK, TX0_MARK,
-};
-static const unsigned int scif0_clk_pins[] = {
-	/* SCK0 */
-	RCAR_GP_PIN(4, 1),
-};
-static const unsigned int scif0_clk_mux[] = {
-	SCK0_MARK,
-};
-static const unsigned int scif0_ctrl_pins[] = {
-	/* RTS0#, CTS0# */
-	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
-};
-static const unsigned int scif0_ctrl_mux[] = {
-	RTS0_N_MARK, CTS0_N_MARK,
-};
-
-/* - SCIF1 ------------------------------------------------------------------ */
-static const unsigned int scif1_data_a_pins[] = {
-	/* RX1, TX1 */
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-};
-static const unsigned int scif1_data_a_mux[] = {
-	RX1_A_MARK, TX1_A_MARK,
-};
-static const unsigned int scif1_clk_pins[] = {
-	/* SCK1 */
-	RCAR_GP_PIN(2, 5),
-};
-static const unsigned int scif1_clk_mux[] = {
-	SCK1_MARK,
-};
-static const unsigned int scif1_ctrl_pins[] = {
-	/* RTS1#, CTS1# */
-	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
-};
-static const unsigned int scif1_ctrl_mux[] = {
-	RTS1_N_MARK, CTS1_N_MARK,
-};
-static const unsigned int scif1_data_b_pins[] = {
-	/* RX1, TX1 */
-	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
-};
-static const unsigned int scif1_data_b_mux[] = {
-	RX1_B_MARK, TX1_B_MARK,
-};
-
-/* - SCIF3 ------------------------------------------------------------------ */
-static const unsigned int scif3_data_pins[] = {
-	/* RX3, TX3 */
-	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-};
-static const unsigned int scif3_data_mux[] = {
-	RX3_MARK, TX3_MARK,
-};
-static const unsigned int scif3_clk_pins[] = {
-	/* SCK3 */
-	RCAR_GP_PIN(2, 0),
-};
-static const unsigned int scif3_clk_mux[] = {
-	SCK3_MARK,
-};
-static const unsigned int scif3_ctrl_pins[] = {
-	/* RTS3#, CTS3# */
-	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
-};
-static const unsigned int scif3_ctrl_mux[] = {
-	RTS3_N_MARK, CTS3_N_MARK,
-};
-
-/* - SCIF4 ------------------------------------------------------------------ */
-static const unsigned int scif4_data_pins[] = {
-	/* RX4, TX4 */
-	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
-};
-static const unsigned int scif4_data_mux[] = {
-	RX4_MARK, TX4_MARK,
-};
-static const unsigned int scif4_clk_pins[] = {
-	/* SCK4 */
-	RCAR_GP_PIN(0, 0),
-};
-static const unsigned int scif4_clk_mux[] = {
-	SCK4_MARK,
-};
-static const unsigned int scif4_ctrl_pins[] = {
-	/* RTS4#, CTS4# */
-	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
-};
-static const unsigned int scif4_ctrl_mux[] = {
-	RTS4_N_MARK, CTS4_N_MARK,
-};
-
 /* - SCIF Clock ------------------------------------------------------------- */
 static const unsigned int scif_clk_a_pins[] = {
 	/* SCIF_CLK */
-	RCAR_GP_PIN(0, 10),
+	RCAR_GP_PIN(0, 18),
 };
 static const unsigned int scif_clk_a_mux[] = {
 	SCIF_CLK_A_MARK,
···
 	SCIF_CLK_B_MARK,
 };
 
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int scif0_data_mux[] = {
+	RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(4, 1),
+};
+static const unsigned int scif0_clk_mux[] = {
+	SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+	/* RTS#, CTS# */
+	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+	RTS0_N_MARK, CTS0_N_MARK,
+};
+
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_a_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int scif1_data_a_mux[] = {
+	RX1_A_MARK, TX1_A_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(2, 5),
+};
+static const unsigned int scif1_clk_mux[] = {
+	SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+	/* RTS#, CTS# */
+	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+	RTS1_N_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
+};
+static const unsigned int scif1_data_b_mux[] = {
+	RX1_B_MARK, TX1_B_MARK,
+};
+
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int scif3_data_mux[] = {
+	RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(2, 0),
+};
+static const unsigned int scif3_clk_mux[] = {
+	SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+	/* RTS#, CTS# */
+	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+	RTS3_N_MARK, CTS3_N_MARK,
+};
+
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int scif4_data_mux[] = {
+	RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(3, 9),
+};
+static const unsigned int scif4_clk_mux[] = {
+	SCK4_MARK,
+};
+static const unsigned int scif4_ctrl_pins[] = {
+	/* RTS#, CTS# */
+	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int scif4_ctrl_mux[] = {
+	RTS4_N_MARK, CTS4_N_MARK,
+};
+
 /* - TMU -------------------------------------------------------------------- */
 static const unsigned int tmu_tclk1_a_pins[] = {
 	/* TCLK1 */
-	RCAR_GP_PIN(3, 13),
+	RCAR_GP_PIN(4, 4),
 };
 static const unsigned int tmu_tclk1_a_mux[] = {
 	TCLK1_A_MARK,
···
 };
 static const unsigned int tmu_tclk2_a_pins[] = {
 	/* TCLK2 */
-	RCAR_GP_PIN(3, 14),
+	RCAR_GP_PIN(4, 5),
 };
 static const unsigned int tmu_tclk2_a_mux[] = {
 	TCLK2_A_MARK,
···
 	TCLK2_B_MARK,
 };
 
-/* - TPU ------------------------------------------------------------------- */
-static const unsigned int tpu_to0_pins[] = {
-	/* TPU0TO0 */
-	RCAR_GP_PIN(1, 19),
-};
-static const unsigned int tpu_to0_mux[] = {
-	TPU0TO0_MARK,
-};
-static const unsigned int tpu_to1_pins[] = {
-	/* TPU0TO1 */
-	RCAR_GP_PIN(1, 20),
-};
-static const unsigned int tpu_to1_mux[] = {
-	TPU0TO1_MARK,
-};
-static const unsigned int tpu_to2_pins[] = {
-	/* TPU0TO2 */
-	RCAR_GP_PIN(4, 2),
-};
-static const unsigned int tpu_to2_mux[] = {
-	TPU0TO2_MARK,
-};
-static const unsigned int tpu_to3_pins[] = {
-	/* TPU0TO3 */
-	RCAR_GP_PIN(4, 3),
-};
-static const unsigned int tpu_to3_mux[] = {
-	TPU0TO3_MARK,
-};
-
 /* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data vin0_data_pins = {
-	.data24 = {
+static const union vin_data12 vin0_data_pins = {
+	.data12 = {
 		RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
 		RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
 		RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
 		RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
 		RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
 		RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
-		RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
-		RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
-		RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
-		RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
-		RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
-		RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
 	},
 };
-static const union vin_data vin0_data_mux = {
-	.data24 = {
+static const union vin_data12 vin0_data_mux = {
+	.data12 = {
 		VI0_DATA0_MARK, VI0_DATA1_MARK,
 		VI0_DATA2_MARK, VI0_DATA3_MARK,
 		VI0_DATA4_MARK, VI0_DATA5_MARK,
 		VI0_DATA6_MARK, VI0_DATA7_MARK,
-		VI0_DATA8_MARK, VI0_DATA9_MARK,
+		VI0_DATA8_MARK,  VI0_DATA9_MARK,
 		VI0_DATA10_MARK, VI0_DATA11_MARK,
-		VI0_DATA12_MARK, VI0_DATA13_MARK,
-		VI0_DATA14_MARK, VI0_DATA15_MARK,
-		VI0_DATA16_MARK, VI0_DATA17_MARK,
-		VI0_DATA18_MARK, VI0_DATA19_MARK,
-		VI0_DATA20_MARK, VI0_DATA21_MARK,
-		VI0_DATA22_MARK, VI0_DATA23_MARK,
 	},
 };
-static const unsigned int vin0_data18_pins[] = {
-	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
-	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
-	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
-	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
-	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
-	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
-	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
-	RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
-};
-static const unsigned int vin0_data18_mux[] = {
-	VI0_DATA2_MARK, VI0_DATA3_MARK,
-	VI0_DATA4_MARK, VI0_DATA5_MARK,
-	VI0_DATA6_MARK, VI0_DATA7_MARK,
-	VI0_DATA10_MARK, VI0_DATA11_MARK,
-	VI0_DATA12_MARK, VI0_DATA13_MARK,
-	VI0_DATA14_MARK, VI0_DATA15_MARK,
-	VI0_DATA18_MARK, VI0_DATA19_MARK,
-	VI0_DATA20_MARK, VI0_DATA21_MARK,
-	VI0_DATA22_MARK, VI0_DATA23_MARK,
-};
 static const unsigned int vin0_sync_pins[] = {
-	/* VI0_VSYNC#, VI0_HSYNC# */
-	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
+	/* HSYNC#, VSYNC# */
+	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
 };
 static const unsigned int vin0_sync_mux[] = {
-	VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
+	VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
 };
 static const unsigned int vin0_field_pins[] = {
-	/* VI0_FIELD */
+	/* FIELD */
 	RCAR_GP_PIN(2, 16),
 };
 static const unsigned int vin0_field_mux[] = {
 	VI0_FIELD_MARK,
 };
 static const unsigned int vin0_clkenb_pins[] = {
-	/* VI0_CLKENB */
+	/* CLKENB */
 	RCAR_GP_PIN(2, 1),
 };
 static const unsigned int vin0_clkenb_mux[] = {
 	VI0_CLKENB_MARK,
 };
 static const unsigned int vin0_clk_pins[] = {
-	/* VI0_CLK */
+	/* CLK */
 	RCAR_GP_PIN(2, 0),
 };
 static const unsigned int vin0_clk_mux[] = {
···
 	},
 };
 static const unsigned int vin1_sync_pins[] = {
-	/* VI1_VSYNC#, VI1_HSYNC# */
-	 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
+	/* HSYNC#, VSYNC# */
+	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
 };
 static const unsigned int vin1_sync_mux[] = {
-	VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
+	VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
 };
 static const unsigned int vin1_field_pins[] = {
-	/* VI1_FIELD */
 	RCAR_GP_PIN(3, 16),
 };
 static const unsigned int vin1_field_mux[] = {
+	/* FIELD */
 	VI1_FIELD_MARK,
 };
 static const unsigned int vin1_clkenb_pins[] = {
-	/* VI1_CLKENB */
 	RCAR_GP_PIN(3, 1),
 };
 static const unsigned int vin1_clkenb_mux[] = {
+	/* CLKENB */
 	VI1_CLKENB_MARK,
 };
 static const unsigned int vin1_clk_pins[] = {
-	/* VI1_CLK */
 	RCAR_GP_PIN(3, 0),
 };
 static const unsigned int vin1_clk_mux[] = {
+	/* CLK */
 	VI1_CLK_MARK,
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
-	SH_PFC_PIN_GROUP(avb_link),
-	SH_PFC_PIN_GROUP(avb_magic),
-	SH_PFC_PIN_GROUP(avb_phy_int),
-	SH_PFC_PIN_GROUP(avb_mdio),
-	SH_PFC_PIN_GROUP(avb_rgmii),
-	SH_PFC_PIN_GROUP(avb_txcrefclk),
-	SH_PFC_PIN_GROUP(avb_avtp_pps),
-	SH_PFC_PIN_GROUP(avb_avtp_capture),
-	SH_PFC_PIN_GROUP(avb_avtp_match),
+	SH_PFC_PIN_GROUP(avb0_link),
+	SH_PFC_PIN_GROUP(avb0_magic),
+	SH_PFC_PIN_GROUP(avb0_phy_int),
+	SH_PFC_PIN_GROUP(avb0_mdio),
+	SH_PFC_PIN_GROUP(avb0_rgmii),
+	SH_PFC_PIN_GROUP(avb0_txcrefclk),
+	SH_PFC_PIN_GROUP(avb0_avtp_pps),
+	SH_PFC_PIN_GROUP(avb0_avtp_capture),
+	SH_PFC_PIN_GROUP(avb0_avtp_match),
+	SH_PFC_PIN_GROUP(canfd_clk_a),
+	SH_PFC_PIN_GROUP(canfd_clk_b),
 	SH_PFC_PIN_GROUP(canfd0_data_a),
 	SH_PFC_PIN_GROUP(canfd0_data_b),
 	SH_PFC_PIN_GROUP(canfd1_data),
-	SH_PFC_PIN_GROUP(canfd_clk_a),
-	SH_PFC_PIN_GROUP(canfd_clk_b),
 	SH_PFC_PIN_GROUP(du_rgb666),
-	SH_PFC_PIN_GROUP(du_rgb888),
 	SH_PFC_PIN_GROUP(du_clk_out),
 	SH_PFC_PIN_GROUP(du_sync),
 	SH_PFC_PIN_GROUP(du_oddf),
 	SH_PFC_PIN_GROUP(du_cde),
 	SH_PFC_PIN_GROUP(du_disp),
-	SH_PFC_PIN_GROUP(gether_link_a),
-	SH_PFC_PIN_GROUP(gether_phy_int_a),
-	SH_PFC_PIN_GROUP(gether_mdio_a),
-	SH_PFC_PIN_GROUP(gether_link_b),
-	SH_PFC_PIN_GROUP(gether_phy_int_b),
-	SH_PFC_PIN_GROUP(gether_mdio_b),
-	SH_PFC_PIN_GROUP(gether_magic),
-	SH_PFC_PIN_GROUP(gether_rgmii),
-	SH_PFC_PIN_GROUP(gether_txcrefclk),
-	SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
-	SH_PFC_PIN_GROUP(gether_rmii),
-	SH_PFC_PIN_GROUP(hscif0_data_a),
-	SH_PFC_PIN_GROUP(hscif0_clk_a),
-	SH_PFC_PIN_GROUP(hscif0_ctrl_a),
-	SH_PFC_PIN_GROUP(hscif0_data_b),
-	SH_PFC_PIN_GROUP(hscif0_clk_b),
-	SH_PFC_PIN_GROUP(hscif0_ctrl_b),
+	SH_PFC_PIN_GROUP(hscif0_data),
+	SH_PFC_PIN_GROUP(hscif0_clk),
+	SH_PFC_PIN_GROUP(hscif0_ctrl),
 	SH_PFC_PIN_GROUP(hscif1_data),
 	SH_PFC_PIN_GROUP(hscif1_clk),
 	SH_PFC_PIN_GROUP(hscif1_ctrl),
···
 	SH_PFC_PIN_GROUP(i2c0),
 	SH_PFC_PIN_GROUP(i2c1),
 	SH_PFC_PIN_GROUP(i2c2),
-	SH_PFC_PIN_GROUP(i2c3),
+	SH_PFC_PIN_GROUP(i2c3_a),
+	SH_PFC_PIN_GROUP(i2c3_b),
 	SH_PFC_PIN_GROUP(i2c4),
-	SH_PFC_PIN_GROUP(i2c5),
 	SH_PFC_PIN_GROUP(intc_ex_irq0),
 	SH_PFC_PIN_GROUP(intc_ex_irq1),
 	SH_PFC_PIN_GROUP(intc_ex_irq2),
···
 	SH_PFC_PIN_GROUP(mmc_data4),
 	SH_PFC_PIN_GROUP(mmc_data8),
 	SH_PFC_PIN_GROUP(mmc_ctrl),
-	SH_PFC_PIN_GROUP(mmc_cd),
-	SH_PFC_PIN_GROUP(mmc_wp),
-	SH_PFC_PIN_GROUP(mmc_ds),
 	SH_PFC_PIN_GROUP(msiof0_clk),
 	SH_PFC_PIN_GROUP(msiof0_sync),
 	SH_PFC_PIN_GROUP(msiof0_ss1),
···
 	SH_PFC_PIN_GROUP(rpc_reset),
 	SH_PFC_PIN_GROUP(rpc_int),
 	SH_PFC_PIN_GROUP(rpc_wp),
+	SH_PFC_PIN_GROUP(scif_clk_a),
+	SH_PFC_PIN_GROUP(scif_clk_b),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
···
 	SH_PFC_PIN_GROUP(scif4_data),
 	SH_PFC_PIN_GROUP(scif4_clk),
 	SH_PFC_PIN_GROUP(scif4_ctrl),
-	SH_PFC_PIN_GROUP(scif_clk_a),
-	SH_PFC_PIN_GROUP(scif_clk_b),
 	SH_PFC_PIN_GROUP(tmu_tclk1_a),
 	SH_PFC_PIN_GROUP(tmu_tclk1_b),
 	SH_PFC_PIN_GROUP(tmu_tclk2_a),
 	SH_PFC_PIN_GROUP(tmu_tclk2_b),
-	SH_PFC_PIN_GROUP(tpu_to0),
-	SH_PFC_PIN_GROUP(tpu_to1),
-	SH_PFC_PIN_GROUP(tpu_to2),
-	SH_PFC_PIN_GROUP(tpu_to3),
 	VIN_DATA_PIN_GROUP(vin0_data, 8),
 	VIN_DATA_PIN_GROUP(vin0_data, 10),
 	VIN_DATA_PIN_GROUP(vin0_data, 12),
-	VIN_DATA_PIN_GROUP(vin0_data, 16),
-	SH_PFC_PIN_GROUP(vin0_data18),
-	VIN_DATA_PIN_GROUP(vin0_data, 20),
-	VIN_DATA_PIN_GROUP(vin0_data, 24),
 	SH_PFC_PIN_GROUP(vin0_sync),
 	SH_PFC_PIN_GROUP(vin0_field),
 	SH_PFC_PIN_GROUP(vin0_clkenb),
···
 	SH_PFC_PIN_GROUP(vin1_clk),
 };
 
-static const char * const avb_groups[] = {
-	"avb_link",
-	"avb_magic",
-	"avb_phy_int",
-	"avb_mdio",
-	"avb_rgmii",
-	"avb_txcrefclk",
-	"avb_avtp_pps",
-	"avb_avtp_capture",
-	"avb_avtp_match",
+static const char * const avb0_groups[] = {
+	"avb0_link",
+	"avb0_magic",
+	"avb0_phy_int",
+	"avb0_mdio",
+	"avb0_rgmii",
+	"avb0_txcrefclk",
+	"avb0_avtp_pps",
+	"avb0_avtp_capture",
+	"avb0_avtp_match",
+};
+
+static const char * const canfd_clk_groups[] = {
+	"canfd_clk_a",
+	"canfd_clk_b",
 };
 
 static const char * const canfd0_groups[] = {
···
 	"canfd1_data",
 };
 
-static const char * const canfd_clk_groups[] = {
-	"canfd_clk_a",
-	"canfd_clk_b",
-};
-
 static const char * const du_groups[] = {
 	"du_rgb666",
-	"du_rgb888",
 	"du_clk_out",
 	"du_sync",
 	"du_oddf",
···
 	"du_disp",
 };
 
-static const char * const gether_groups[] = {
-	"gether_link_a",
-	"gether_phy_int_a",
-	"gether_mdio_a",
-	"gether_link_b",
-	"gether_phy_int_b",
-	"gether_mdio_b",
-	"gether_magic",
-	"gether_rgmii",
-	"gether_txcrefclk",
-	"gether_txcrefclk_mega",
-	"gether_rmii",
-};
-
 static const char * const hscif0_groups[] = {
-	"hscif0_data_a",
-	"hscif0_clk_a",
-	"hscif0_ctrl_a",
-	"hscif0_data_b",
-	"hscif0_clk_b",
-	"hscif0_ctrl_b",
+	"hscif0_data",
+	"hscif0_clk",
+	"hscif0_ctrl",
 };
 
 static const char * const hscif1_groups[] = {
···
 };
 
 static const char * const i2c3_groups[] = {
-	"i2c3",
+	"i2c3_a",
+	"i2c3_b",
 };
 
 static const char * const i2c4_groups[] = {
 	"i2c4",
-};
-
-static const char * const i2c5_groups[] = {
-	"i2c5",
 };
 
 static const char * const intc_ex_groups[] = {
···
 	"mmc_data4",
 	"mmc_data8",
 	"mmc_ctrl",
-	"mmc_cd",
-	"mmc_wp",
-	"mmc_ds",
 };
 
 static const char * const msiof0_groups[] = {
···
 	"rpc_wp",
 };
 
+static const char * const scif_clk_groups[] = {
+	"scif_clk_a",
+	"scif_clk_b",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
···
 	"scif4_ctrl",
 };
 
-static const char * const scif_clk_groups[] = {
-	"scif_clk_a",
-	"scif_clk_b",
-};
-
 static const char * const tmu_groups[] = {
 	"tmu_tclk1_a",
 	"tmu_tclk1_b",
···
 	"tmu_tclk2_b",
 };
 
-static const char * const tpu_groups[] = {
-	"tpu_to0",
-	"tpu_to1",
-	"tpu_to2",
-	"tpu_to3",
-};
-
 static const char * const vin0_groups[] = {
 	"vin0_data8",
 	"vin0_data10",
 	"vin0_data12",
-	"vin0_data16",
-	"vin0_data18",
-	"vin0_data20",
-	"vin0_data24",
 	"vin0_sync",
 	"vin0_field",
 	"vin0_clkenb",
···
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
-	SH_PFC_FUNCTION(avb),
+	SH_PFC_FUNCTION(avb0),
+	SH_PFC_FUNCTION(canfd_clk),
 	SH_PFC_FUNCTION(canfd0),
 	SH_PFC_FUNCTION(canfd1),
-	SH_PFC_FUNCTION(canfd_clk),
 	SH_PFC_FUNCTION(du),
-	SH_PFC_FUNCTION(gether),
 	SH_PFC_FUNCTION(hscif0),
 	SH_PFC_FUNCTION(hscif1),
 	SH_PFC_FUNCTION(hscif2),
···
 	SH_PFC_FUNCTION(i2c2),
 	SH_PFC_FUNCTION(i2c3),
 	SH_PFC_FUNCTION(i2c4),
-	SH_PFC_FUNCTION(i2c5),
 	SH_PFC_FUNCTION(intc_ex),
 	SH_PFC_FUNCTION(mmc),
 	SH_PFC_FUNCTION(msiof0),
···
 	SH_PFC_FUNCTION(qspi0),
 	SH_PFC_FUNCTION(qspi1),
 	SH_PFC_FUNCTION(rpc),
+	SH_PFC_FUNCTION(scif_clk),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif3),
 	SH_PFC_FUNCTION(scif4),
-	SH_PFC_FUNCTION(scif_clk),
 	SH_PFC_FUNCTION(tmu),
-	SH_PFC_FUNCTION(tpu),
 	SH_PFC_FUNCTION(vin0),
 	SH_PFC_FUNCTION(vin1),
 };
···
 	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
 		0, 0,
 		0, 0,
-		GP_2_29_FN,	GPSR2_29,
-		GP_2_28_FN,	GPSR2_28,
-		GP_2_27_FN,	GPSR2_27,
-		GP_2_26_FN,	GPSR2_26,
-		GP_2_25_FN,	GPSR2_25,
-		GP_2_24_FN,	GPSR2_24,
-		GP_2_23_FN,	GPSR2_23,
-		GP_2_22_FN,	GPSR2_22,
-		GP_2_21_FN,	GPSR2_21,
-		GP_2_20_FN,	GPSR2_20,
-		GP_2_19_FN,	GPSR2_19,
-		GP_2_18_FN,	GPSR2_18,
-		GP_2_17_FN,	GPSR2_17,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
 		GP_2_16_FN,	GPSR2_16,
 		GP_2_15_FN,	GPSR2_15,
 		GP_2_14_FN,	GPSR2_14,
···
 		0, 0,
 		0, 0,
 		0, 0,
-		GP_4_24_FN,	GPSR4_24,
-		GP_4_23_FN,	GPSR4_23,
-		GP_4_22_FN,	GPSR4_22,
-		GP_4_21_FN,	GPSR4_21,
-		GP_4_20_FN,	GPSR4_20,
-		GP_4_19_FN,	GPSR4_19,
-		GP_4_18_FN,	GPSR4_18,
-		GP_4_17_FN,	GPSR4_17,
-		GP_4_16_FN,	GPSR4_16,
-		GP_4_15_FN,	GPSR4_15,
-		GP_4_14_FN,	GPSR4_14,
-		GP_4_13_FN,	GPSR4_13,
-		GP_4_12_FN,	GPSR4_12,
-		GP_4_11_FN,	GPSR4_11,
-		GP_4_10_FN,	GPSR4_10,
-		GP_4_9_FN,	GPSR4_9,
-		GP_4_8_FN,	GPSR4_8,
-		GP_4_7_FN,	GPSR4_7,
-		GP_4_6_FN,	GPSR4_6,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
 		GP_4_5_FN,	GPSR4_5,
 		GP_4_4_FN,	GPSR4_4,
 		GP_4_3_FN,	GPSR4_3,
···
 		IP8_7_4
 		IP8_3_0 ))
 	},
-	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
-		IP9_31_28
-		IP9_27_24
-		IP9_23_20
-		IP9_19_16
-		IP9_15_12
-		IP9_11_8
-		IP9_7_4
-		IP9_3_0 ))
-	},
-	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
-		IP10_31_28
-		IP10_27_24
-		IP10_23_20
-		IP10_19_16
-		IP10_15_12
-		IP10_11_8
-		IP10_7_4
-		IP10_3_0 ))
-	},
 #undef F_
 #undef FM
 
···
 		MOD_SEL0_6
 		MOD_SEL0_5
 		MOD_SEL0_4
-		0, 0,
+		MOD_SEL0_3
 		MOD_SEL0_2
 		MOD_SEL0_1
 		MOD_SEL0_0 ))
···
 	POCCTRL0,
 	POCCTRL1,
 	POCCTRL2,
-	POCCTRL3,
 	TDSELCTRL,
 };
 
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
-	[POCCTRL0] = { 0xe6060380, },
-	[POCCTRL1] = { 0xe6060384, },
-	[POCCTRL2] = { 0xe6060388, },
-	[POCCTRL3] = { 0xe606038c, },
+	[POCCTRL0] = { 0xe6060380 },
+	[POCCTRL1] = { 0xe6060384 },
+	[POCCTRL2] = { 0xe6060388 },
 	[TDSELCTRL] = { 0xe60603c0, },
 	{ /* sentinel */ },
 };
 
-static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
+static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
 				   u32 *pocctrl)
 {
 	int bit = pin & 0x1f;
···
 	*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
 	if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
 		return bit;
-	else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+	if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
 		return bit + 22;
 
 	*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
 	if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
 		return bit - 10;
-	if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
-	    (pin >= RCAR_GP_PIN(3,  0) && pin <= RCAR_GP_PIN(3, 16)))
+	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
 		return bit + 7;
-
-	*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
-	if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
-		return pin - 25;
 
 	return -EINVAL;
 }
 
 static const struct sh_pfc_soc_operations pinmux_ops = {
-	.pin_to_pocctrl = r8a77980_pin_to_pocctrl,
+	.pin_to_pocctrl = r8a77970_pin_to_pocctrl,
 };
 
-const struct sh_pfc_soc_info r8a77980_pinmux_info = {
-	.name = "r8a77980_pfc",
+const struct sh_pfc_soc_info r8a77970_pinmux_info = {
+	.name = "r8a77970_pfc",
 	.ops = &pinmux_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 

drivers/pinctrl/sh-pfc/pfc-r8a77990.c drivers/pinctrl/renesas/pfc-r8a77990.c

···
  *
  * Copyright (C) 2018-2019 Renesas Electronics Corp.
  *
- * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+ * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
  *
  * R8A7796 processor support - PFC hardware block.
  *

drivers/pinctrl/sh-pfc/pfc-r8a77995.c drivers/pinctrl/renesas/pfc-r8a77995.c

···
  *
  * Copyright (C) 2017 Renesas Electronics Corp.
  *
- * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+ * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
  *
  * R-Car Gen3 processor support - PFC hardware block.
  *