Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/rockchip: vop2: set bg dly and prescan dly at vop2_post_config

We need to setup background delay cycle and prescan
delay cycle when a mode is enable to avoid trigger
POST_BUF_EMPTY irq on rk3588.

Note: RK356x has no such requirement.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20231211115815.1785131-1-andyshrk@163.com

authored by

Andy Yan and committed by
Heiko Stuebner
075a5b39 dd49ee46

+10 -16
+10 -16
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
··· 1460 1460 u32 top_margin = 100, bottom_margin = 100; 1461 1461 u16 hsize = hdisplay * (left_margin + right_margin) / 200; 1462 1462 u16 vsize = vdisplay * (top_margin + bottom_margin) / 200; 1463 + u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1463 1464 u16 hact_end, vact_end; 1464 1465 u32 val; 1466 + u32 bg_dly; 1467 + u32 pre_scan_dly; 1468 + 1469 + bg_dly = vp->data->pre_scan_max_dly[3]; 1470 + vop2_writel(vp->vop2, RK3568_VP_BG_MIX_CTRL(vp->id), 1471 + FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly)); 1472 + 1473 + pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len; 1474 + vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); 1465 1475 1466 1476 vsize = rounddown(vsize, 2); 1467 1477 hsize = rounddown(hsize, 2); ··· 1966 1956 u32 layer_sel = 0; 1967 1957 u32 port_sel; 1968 1958 unsigned int nlayer, ofs; 1969 - struct drm_display_mode *adjusted_mode; 1970 - u16 hsync_len; 1971 - u16 hdisplay; 1972 - u32 bg_dly; 1973 - u32 pre_scan_dly; 1974 1959 u32 ovl_ctrl; 1975 1960 int i; 1976 1961 struct vop2_video_port *vp0 = &vop2->vps[0]; 1977 1962 struct vop2_video_port *vp1 = &vop2->vps[1]; 1978 1963 struct vop2_video_port *vp2 = &vop2->vps[2]; 1979 1964 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); 1980 - 1981 - adjusted_mode = &vp->crtc.state->adjusted_mode; 1982 - hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1983 - hdisplay = adjusted_mode->crtc_hdisplay; 1984 - 1985 - bg_dly = vp->data->pre_scan_max_dly[3]; 1986 - vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id), 1987 - FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly)); 1988 - 1989 - pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len; 1990 - vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); 1991 1965 1992 1966 ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL); 1993 1967 ovl_ctrl |= RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD;