tjh.dev
+21
-2
tools/testing/selftests/kvm/riscv/get-reg-list.c
+21
-2
tools/testing/selftests/kvm/riscv/get-reg-list.c
···
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#define REG_MASK (KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK)
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bool filter_reg(__u64 reg)
16
{
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switch (reg & ~REG_MASK) {
···
50
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
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return true;
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default:
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break;
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}
···
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void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c)
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{
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struct vcpu_reg_sublist *s;
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/*
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* Disable all extensions which were enabled by default
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* if they were available in the risc-v host.
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*/
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-
for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++)
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-
__vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0);
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for_each_sublist(c, s) {
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if (!s->feature)
···
12
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#define REG_MASK (KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK)
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+
static bool isa_ext_cant_disable[KVM_RISCV_ISA_EXT_MAX];
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+
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bool filter_reg(__u64 reg)
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{
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switch (reg & ~REG_MASK) {
···
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
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return true;
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+
/* AIA registers are always available when Ssaia can't be disabled */
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case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):
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case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1):
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+
case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2):
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+
case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh):
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+
case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph):
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case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h):
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case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h):
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return isa_ext_cant_disable[KVM_RISCV_ISA_EXT_SSAIA];
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default:
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break;
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}
···
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void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c)
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{
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+
unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] = { 0 };
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struct vcpu_reg_sublist *s;
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+
int rc;
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+
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+
for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++)
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__vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(i), &isa_ext_state[i]);
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/*
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* Disable all extensions which were enabled by default
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* if they were available in the risc-v host.
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*/
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+
for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) {
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+
rc = __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0);
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if (rc && isa_ext_state[i])
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isa_ext_cant_disable[i] = true;
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+
}
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for_each_sublist(c, s) {
92
if (!s->feature)