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arm64: dts: lx2160a: Correct CPU core idle state name

lx2160a support PW15 but not PW20, correct name to avoid confusing.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Fixes: 00c5ce8ac023 ("arm64: dts: lx2160a: add cpu idle support")
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

authored by

Ran Wang and committed by
Shawn Guo 07159f67 21094ba5

+18 -18
+18 -18
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
··· 33 33 i-cache-line-size = <64>; 34 34 i-cache-sets = <192>; 35 35 next-level-cache = <&cluster0_l2>; 36 - cpu-idle-states = <&cpu_pw20>; 36 + cpu-idle-states = <&cpu_pw15>; 37 37 }; 38 38 39 39 cpu@1 { ··· 49 49 i-cache-line-size = <64>; 50 50 i-cache-sets = <192>; 51 51 next-level-cache = <&cluster0_l2>; 52 - cpu-idle-states = <&cpu_pw20>; 52 + cpu-idle-states = <&cpu_pw15>; 53 53 }; 54 54 55 55 cpu@100 { ··· 65 65 i-cache-line-size = <64>; 66 66 i-cache-sets = <192>; 67 67 next-level-cache = <&cluster1_l2>; 68 - cpu-idle-states = <&cpu_pw20>; 68 + cpu-idle-states = <&cpu_pw15>; 69 69 }; 70 70 71 71 cpu@101 { ··· 81 81 i-cache-line-size = <64>; 82 82 i-cache-sets = <192>; 83 83 next-level-cache = <&cluster1_l2>; 84 - cpu-idle-states = <&cpu_pw20>; 84 + cpu-idle-states = <&cpu_pw15>; 85 85 }; 86 86 87 87 cpu@200 { ··· 97 97 i-cache-line-size = <64>; 98 98 i-cache-sets = <192>; 99 99 next-level-cache = <&cluster2_l2>; 100 - cpu-idle-states = <&cpu_pw20>; 100 + cpu-idle-states = <&cpu_pw15>; 101 101 }; 102 102 103 103 cpu@201 { ··· 113 113 i-cache-line-size = <64>; 114 114 i-cache-sets = <192>; 115 115 next-level-cache = <&cluster2_l2>; 116 - cpu-idle-states = <&cpu_pw20>; 116 + cpu-idle-states = <&cpu_pw15>; 117 117 }; 118 118 119 119 cpu@300 { ··· 129 129 i-cache-line-size = <64>; 130 130 i-cache-sets = <192>; 131 131 next-level-cache = <&cluster3_l2>; 132 - cpu-idle-states = <&cpu_pw20>; 132 + cpu-idle-states = <&cpu_pw15>; 133 133 }; 134 134 135 135 cpu@301 { ··· 145 145 i-cache-line-size = <64>; 146 146 i-cache-sets = <192>; 147 147 next-level-cache = <&cluster3_l2>; 148 - cpu-idle-states = <&cpu_pw20>; 148 + cpu-idle-states = <&cpu_pw15>; 149 149 }; 150 150 151 151 cpu@400 { ··· 161 161 i-cache-line-size = <64>; 162 162 i-cache-sets = <192>; 163 163 next-level-cache = <&cluster4_l2>; 164 - cpu-idle-states = <&cpu_pw20>; 164 + cpu-idle-states = <&cpu_pw15>; 165 165 }; 166 166 167 167 cpu@401 { ··· 177 177 i-cache-line-size = <64>; 178 178 i-cache-sets = <192>; 179 179 next-level-cache = <&cluster4_l2>; 180 - cpu-idle-states = <&cpu_pw20>; 180 + cpu-idle-states = <&cpu_pw15>; 181 181 }; 182 182 183 183 cpu@500 { ··· 193 193 i-cache-line-size = <64>; 194 194 i-cache-sets = <192>; 195 195 next-level-cache = <&cluster5_l2>; 196 - cpu-idle-states = <&cpu_pw20>; 196 + cpu-idle-states = <&cpu_pw15>; 197 197 }; 198 198 199 199 cpu@501 { ··· 209 209 i-cache-line-size = <64>; 210 210 i-cache-sets = <192>; 211 211 next-level-cache = <&cluster5_l2>; 212 - cpu-idle-states = <&cpu_pw20>; 212 + cpu-idle-states = <&cpu_pw15>; 213 213 }; 214 214 215 215 cpu@600 { ··· 225 225 i-cache-line-size = <64>; 226 226 i-cache-sets = <192>; 227 227 next-level-cache = <&cluster6_l2>; 228 - cpu-idle-states = <&cpu_pw20>; 228 + cpu-idle-states = <&cpu_pw15>; 229 229 }; 230 230 231 231 cpu@601 { ··· 241 241 i-cache-line-size = <64>; 242 242 i-cache-sets = <192>; 243 243 next-level-cache = <&cluster6_l2>; 244 - cpu-idle-states = <&cpu_pw20>; 244 + cpu-idle-states = <&cpu_pw15>; 245 245 }; 246 246 247 247 cpu@700 { ··· 257 257 i-cache-line-size = <64>; 258 258 i-cache-sets = <192>; 259 259 next-level-cache = <&cluster7_l2>; 260 - cpu-idle-states = <&cpu_pw20>; 260 + cpu-idle-states = <&cpu_pw15>; 261 261 }; 262 262 263 263 cpu@701 { ··· 273 273 i-cache-line-size = <64>; 274 274 i-cache-sets = <192>; 275 275 next-level-cache = <&cluster7_l2>; 276 - cpu-idle-states = <&cpu_pw20>; 276 + cpu-idle-states = <&cpu_pw15>; 277 277 }; 278 278 279 279 cluster0_l2: l2-cache0 { ··· 340 340 cache-level = <2>; 341 341 }; 342 342 343 - cpu_pw20: cpu-pw20 { 343 + cpu_pw15: cpu-pw15 { 344 344 compatible = "arm,idle-state"; 345 - idle-state-name = "PW20"; 345 + idle-state-name = "PW15"; 346 346 arm,psci-suspend-param = <0x0>; 347 347 entry-latency-us = <2000>; 348 348 exit-latency-us = <2000>;