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kernel os linux

ARM: mediatek: add UART dts for mt8127 and mt8135

This add dts support for mt8127 and mt8135 SOC UART

Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

authored by

Eddie Huang and committed by
Matthias Brugger
07149473 e0bed077

+78
+38
arch/arm/boot/dts/mt8127.dtsi
··· 64 64 clock-frequency = <32000>; 65 65 #clock-cells = <0>; 66 66 }; 67 + 68 + uart_clk: dummy26m { 69 + compatible = "fixed-clock"; 70 + clock-frequency = <26000000>; 71 + #clock-cells = <0>; 72 + }; 67 73 }; 68 74 69 75 soc { ··· 105 99 <0 0x10212000 0 0x1000>, 106 100 <0 0x10214000 0 0x2000>, 107 101 <0 0x10216000 0 0x2000>; 102 + }; 103 + 104 + uart0: serial@11006000 { 105 + compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 106 + reg = <0 0x11002000 0 0x400>; 107 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 108 + clocks = <&uart_clk>; 109 + status = "disabled"; 110 + }; 111 + 112 + uart1: serial@11007000 { 113 + compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 114 + reg = <0 0x11003000 0 0x400>; 115 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 116 + clocks = <&uart_clk>; 117 + status = "disabled"; 118 + }; 119 + 120 + uart2: serial@11008000 { 121 + compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 122 + reg = <0 0x11004000 0 0x400>; 123 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 124 + clocks = <&uart_clk>; 125 + status = "disabled"; 126 + }; 127 + 128 + uart3: serial@11009000 { 129 + compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 130 + reg = <0 0x11005000 0 0x400>; 131 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 132 + clocks = <&uart_clk>; 133 + status = "disabled"; 108 134 }; 109 135 }; 110 136 };
+40
arch/arm/boot/dts/mt8135.dtsi
··· 86 86 clock-frequency = <32000>; 87 87 #clock-cells = <0>; 88 88 }; 89 + 90 + uart_clk: dummy26m { 91 + compatible = "fixed-clock"; 92 + clock-frequency = <26000000>; 93 + #clock-cells = <0>; 94 + }; 95 + 89 96 }; 90 97 91 98 soc { ··· 129 122 <0 0x10214000 0 0x2000>, 130 123 <0 0x10216000 0 0x2000>; 131 124 }; 125 + 126 + uart0: serial@11006000 { 127 + compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; 128 + reg = <0 0x11006000 0 0x400>; 129 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 130 + clocks = <&uart_clk>; 131 + status = "disabled"; 132 + }; 133 + 134 + uart1: serial@11007000 { 135 + compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; 136 + reg = <0 0x11007000 0 0x400>; 137 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 138 + clocks = <&uart_clk>; 139 + status = "disabled"; 140 + }; 141 + 142 + uart2: serial@11008000 { 143 + compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; 144 + reg = <0 0x11008000 0 0x400>; 145 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 146 + clocks = <&uart_clk>; 147 + status = "disabled"; 148 + }; 149 + 150 + uart3: serial@11009000 { 151 + compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; 152 + reg = <0 0x11009000 0 0x400>; 153 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 154 + clocks = <&uart_clk>; 155 + status = "disabled"; 156 + }; 157 + 132 158 }; 133 159 };