tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550

Align PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware Programming
Guide.

Signed-off-by: Can Guo <quic_cang@quicinc.com>
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Link: https://lore.kernel.org/r/1703742157-69840-2-git-send-email-quic_qianyu@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Can Guo and committed by
Vinod Koul 06e34728 f7c6249d

+16 -5
+11 -5
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 1967 1967 1968 1968 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 1969 1969 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 1970 - QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_Q_EN_RATES, 0xe), 1971 1970 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00), 1972 - QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00), 1973 - QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f), 1971 + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 1972 + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 1974 1973 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), 1975 1974 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 1976 1975 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), ··· 1986 1987 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1987 1988 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1988 1989 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1990 + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 1989 1991 }; 1990 1992 1991 1993 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = { ··· 1999 1999 }; 2000 2000 2001 2001 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = { 2002 - QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), 2002 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 2003 2003 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 2004 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 2004 2005 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 2005 2006 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 2006 2007 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 2007 2008 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c), 2008 2009 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 2010 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 2009 2011 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2010 2012 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 2011 2013 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), ··· 2029 2027 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78), 2030 2028 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 2031 2029 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 2030 + QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 2032 2031 }; 2033 2032 2034 2033 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = { 2034 + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 2035 2035 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), 2036 - QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL, 0x25), 2036 + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), 2037 2037 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), 2038 2038 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), 2039 2039 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), ··· 2046 2042 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 2047 2043 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), 2048 2044 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), 2045 + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), 2046 + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), 2049 2047 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), 2050 2048 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), 2051 2049 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
··· 12 12 #define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c 13 13 #define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090 14 14 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0 15 + #define QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME 0x0f0 16 + #define QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME 0x0f4 15 17 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108 16 18 #define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c 17 19 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
+1
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h
··· 7 7 #define QCOM_PHY_QMP_PCS_V6_20_H_ 8 8 9 9 /* Only for QMP V6_20 PHY - USB/PCIe PCS registers */ 10 + #define QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB 0x170 10 11 #define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178 11 12 #define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190 12 13 #define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
+2
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
··· 23 23 #define QSERDES_V6_20_RX_DFE_1 0xac 24 24 #define QSERDES_V6_20_RX_DFE_2 0xb0 25 25 #define QSERDES_V6_20_RX_DFE_3 0xb4 26 + #define QSERDES_V6_20_RX_TX_ADPT_CTRL 0xd4 27 + #define QSERDES_V6_20_VGA_CAL_CNTRL1 0xe0 26 28 #define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8 27 29 #define QSERDES_V6_20_RX_GM_CAL 0x10c 28 30 #define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4 0x120