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Staging: winbond: Fix Sparse Warnings in phy_calibration.c

This patch fixes Sparse Warnings "symbol was not
declared. Should it be static?" and "defined
but not used [-Wunused-function]" in
phy_calibration.c

Signed-off-by: Ebru Akagunduz <ebru.akagunduz@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Ebru Akagunduz and committed by
Greg Kroah-Hartman 06c789ed f0c80e4e

+16 -299
+16 -299
drivers/staging/winbond/phy_calibration.c
··· 44 44 45 45 /****************** FUNCTION DEFINITION SECTION *****************************/ 46 46 47 - s32 _s13_to_s32(u32 data) 47 + static s32 _s13_to_s32(u32 data) 48 48 { 49 49 u32 val; 50 50 ··· 56 56 return (s32) val; 57 57 } 58 58 59 - u32 _s32_to_s13(s32 data) 60 - { 61 - u32 val; 62 - 63 - if (data > 4095) 64 - data = 4095; 65 - else if (data < -4096) 66 - data = -4096; 67 - 68 - val = data & 0x1FFF; 69 - 70 - return val; 71 - } 72 - 73 59 /****************************************************************************/ 74 - s32 _s4_to_s32(u32 data) 60 + static s32 _s4_to_s32(u32 data) 75 61 { 76 62 s32 val; 77 63 ··· 69 83 return val; 70 84 } 71 85 72 - u32 _s32_to_s4(s32 data) 86 + static u32 _s32_to_s4(s32 data) 73 87 { 74 88 u32 val; 75 89 ··· 84 98 } 85 99 86 100 /****************************************************************************/ 87 - s32 _s5_to_s32(u32 data) 101 + static s32 _s5_to_s32(u32 data) 88 102 { 89 103 s32 val; 90 104 ··· 96 110 return val; 97 111 } 98 112 99 - u32 _s32_to_s5(s32 data) 113 + static u32 _s32_to_s5(s32 data) 100 114 { 101 115 u32 val; 102 116 ··· 111 125 } 112 126 113 127 /****************************************************************************/ 114 - s32 _s6_to_s32(u32 data) 128 + static s32 _s6_to_s32(u32 data) 115 129 { 116 130 s32 val; 117 131 ··· 123 137 return val; 124 138 } 125 139 126 - u32 _s32_to_s6(s32 data) 140 + static u32 _s32_to_s6(s32 data) 127 141 { 128 142 u32 val; 129 143 ··· 138 152 } 139 153 140 154 /****************************************************************************/ 141 - s32 _s9_to_s32(u32 data) 142 - { 143 - s32 val; 144 - 145 - val = data & 0x00FF; 146 - 147 - if ((data & BIT(8)) != 0) 148 - val |= 0xFFFFFF00; 149 - 150 - return val; 151 - } 152 - 153 - u32 _s32_to_s9(s32 data) 154 - { 155 - u32 val; 156 - 157 - if (data > 255) 158 - data = 255; 159 - else if (data < -256) 160 - data = -256; 161 - 162 - val = data & 0x01FF; 163 - 164 - return val; 165 - } 166 - 167 - /****************************************************************************/ 168 - s32 _floor(s32 n) 155 + static s32 _floor(s32 n) 169 156 { 170 157 if (n > 0) 171 158 n += 5; ··· 154 195 * sqsum is the input and the output is sq_rt; 155 196 * The maximum of sqsum = 2^27 -1; 156 197 */ 157 - u32 _sqrt(u32 sqsum) 198 + static u32 _sqrt(u32 sqsum) 158 199 { 159 200 u32 sq_rt; 160 201 ··· 222 263 } 223 264 224 265 /****************************************************************************/ 225 - void _sin_cos(s32 angle, s32 *sin, s32 *cos) 266 + static void _sin_cos(s32 angle, s32 *sin, s32 *cos) 226 267 { 227 268 s32 X, Y, TargetAngle, CurrAngle; 228 269 unsigned Step; ··· 279 320 #define hw_set_dxx_reg(_A, _B, _C) hal_set_dxx_reg(_A, _B, (u32)_C) 280 321 281 322 282 - void _reset_rx_cal(struct hw_data *phw_data) 323 + static void _reset_rx_cal(struct hw_data *phw_data) 283 324 { 284 325 u32 val; 285 326 ··· 299 340 300 341 301 342 /**********************************************/ 302 - void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency) 343 + static void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency) 303 344 { 304 345 u32 reg_agc_ctrl3; 305 346 u32 reg_a_acq_ctrl; ··· 394 435 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 395 436 } 396 437 397 - /****************************************************************/ 398 - void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data) 399 - { 400 - u32 reg_agc_ctrl3; 401 - u32 reg_mode_ctrl; 402 - u32 reg_dc_cancel; 403 - s32 iqcal_image_i; 404 - s32 iqcal_image_q; 405 - u32 sqsum; 406 - s32 mag_0; 407 - s32 mag_1; 408 - s32 fix_cancel_dc_i = 0; 409 - u32 val; 410 - int loop; 411 - 412 - PHY_DEBUG(("[CAL] -> [2]_txidac_dc_offset_cancellation()\n")); 413 - 414 - /* a. Set to "TX calibration mode" */ 415 - 416 - /* 0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits */ 417 - phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); 418 - /* 0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit */ 419 - phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6); 420 - /* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */ 421 - phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A); 422 - /* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */ 423 - phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C); 424 - /* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */ 425 - phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); 426 - 427 - hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */ 428 - 429 - /* a. Disable AGC */ 430 - hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3); 431 - reg_agc_ctrl3 &= ~BIT(2); 432 - reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 433 - hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 434 - 435 - hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); 436 - val |= MASK_AGC_FIX_GAIN; 437 - hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); 438 - 439 - /* b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0 */ 440 - hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 441 - 442 - PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 443 - reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); 444 - 445 - /* mode=2, tone=0 */ 446 - /* reg_mode_ctrl |= (MASK_CALIB_START|2); */ 447 - 448 - /* mode=2, tone=1 */ 449 - /* reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2)); */ 450 - 451 - /* mode=2, tone=2 */ 452 - reg_mode_ctrl |= (MASK_CALIB_START|2|(2<<2)); 453 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 454 - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 455 - 456 - hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel); 457 - PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel)); 458 - 459 - for (loop = 0; loop < LOOP_TIMES; loop++) { 460 - PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop)); 461 - 462 - /* c. reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel */ 463 - reg_dc_cancel &= ~(0x03FF); 464 - PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 465 - hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 466 - 467 - hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); 468 - PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); 469 - 470 - iqcal_image_i = _s13_to_s32(val & 0x00001FFF); 471 - iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); 472 - sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; 473 - mag_0 = (s32) _sqrt(sqsum); 474 - PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", 475 - mag_0, iqcal_image_i, iqcal_image_q)); 476 - 477 - /* d. */ 478 - reg_dc_cancel |= (1 << CANCEL_DC_I_SHIFT); 479 - PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 480 - hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 481 - 482 - hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); 483 - PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); 484 - 485 - iqcal_image_i = _s13_to_s32(val & 0x00001FFF); 486 - iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); 487 - sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; 488 - mag_1 = (s32) _sqrt(sqsum); 489 - PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", 490 - mag_1, iqcal_image_i, iqcal_image_q)); 491 - 492 - /* e. Calculate the correct DC offset cancellation value for I */ 493 - if (mag_0 != mag_1) 494 - fix_cancel_dc_i = (mag_0*10000) / (mag_0*10000 - mag_1*10000); 495 - else { 496 - if (mag_0 == mag_1) 497 - PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n")); 498 - fix_cancel_dc_i = 0; 499 - } 500 - 501 - PHY_DEBUG(("[CAL] ** fix_cancel_dc_i = %d (0x%04X)\n", 502 - fix_cancel_dc_i, 503 - _s32_to_s5(fix_cancel_dc_i))); 504 - 505 - if ((abs(mag_1-mag_0)*6) > mag_0) 506 - break; 507 - } 508 - 509 - if (loop >= 19) 510 - fix_cancel_dc_i = 0; 511 - 512 - reg_dc_cancel &= ~(0x03FF); 513 - reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_i) << CANCEL_DC_I_SHIFT); 514 - hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 515 - PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 516 - 517 - /* g. */ 518 - reg_mode_ctrl &= ~MASK_CALIB_START; 519 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 520 - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 521 - } 522 - 523 - /*****************************************************/ 524 - void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data) 525 - { 526 - u32 reg_agc_ctrl3; 527 - u32 reg_mode_ctrl; 528 - u32 reg_dc_cancel; 529 - s32 iqcal_image_i; 530 - s32 iqcal_image_q; 531 - u32 sqsum; 532 - s32 mag_0; 533 - s32 mag_1; 534 - s32 fix_cancel_dc_q = 0; 535 - u32 val; 536 - int loop; 537 - 538 - PHY_DEBUG(("[CAL] -> [3]_txqdac_dc_offset_cacellation()\n")); 539 - /*0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits */ 540 - phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); 541 - /* 0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit */ 542 - phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6); 543 - /* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */ 544 - phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A); 545 - /* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */ 546 - phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C); 547 - /* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */ 548 - phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); 549 - 550 - hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */ 551 - 552 - /* a. Disable AGC */ 553 - hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3); 554 - reg_agc_ctrl3 &= ~BIT(2); 555 - reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 556 - hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 557 - 558 - hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); 559 - val |= MASK_AGC_FIX_GAIN; 560 - hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); 561 - 562 - /* a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0 */ 563 - hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 564 - PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 565 - 566 - /* reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); */ 567 - reg_mode_ctrl &= ~(MASK_IQCAL_MODE); 568 - reg_mode_ctrl |= (MASK_CALIB_START|3); 569 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 570 - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 571 - 572 - hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel); 573 - PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel)); 574 - 575 - for (loop = 0; loop < LOOP_TIMES; loop++) { 576 - PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop)); 577 - 578 - /* b. reset cancel_dc_q[4:0] in register DC_Cancel */ 579 - reg_dc_cancel &= ~(0x001F); 580 - PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 581 - hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 582 - 583 - hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); 584 - PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); 585 - 586 - iqcal_image_i = _s13_to_s32(val & 0x00001FFF); 587 - iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); 588 - sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; 589 - mag_0 = _sqrt(sqsum); 590 - PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", 591 - mag_0, iqcal_image_i, iqcal_image_q)); 592 - 593 - /* c. */ 594 - reg_dc_cancel |= (1 << CANCEL_DC_Q_SHIFT); 595 - PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 596 - hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 597 - 598 - hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); 599 - PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); 600 - 601 - iqcal_image_i = _s13_to_s32(val & 0x00001FFF); 602 - iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); 603 - sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; 604 - mag_1 = _sqrt(sqsum); 605 - PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", 606 - mag_1, iqcal_image_i, iqcal_image_q)); 607 - 608 - /* d. Calculate the correct DC offset cancellation value for I */ 609 - if (mag_0 != mag_1) 610 - fix_cancel_dc_q = (mag_0*10000) / (mag_0*10000 - mag_1*10000); 611 - else { 612 - if (mag_0 == mag_1) 613 - PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n")); 614 - fix_cancel_dc_q = 0; 615 - } 616 - 617 - PHY_DEBUG(("[CAL] ** fix_cancel_dc_q = %d (0x%04X)\n", 618 - fix_cancel_dc_q, _s32_to_s5(fix_cancel_dc_q))); 619 - 620 - if ((abs(mag_1-mag_0)*6) > mag_0) 621 - break; 622 - } 623 - 624 - if (loop >= 19) 625 - fix_cancel_dc_q = 0; 626 - 627 - reg_dc_cancel &= ~(0x001F); 628 - reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_q) << CANCEL_DC_Q_SHIFT); 629 - hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 630 - PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 631 - 632 - 633 - /* f. */ 634 - reg_mode_ctrl &= ~MASK_CALIB_START; 635 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 636 - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 637 - } 638 - 639 438 /* 20060612.1.a 20060718.1 Modify */ 640 - u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, 439 + static u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, 641 440 s32 a_2_threshold, 642 441 s32 b_2_threshold) 643 442 { ··· 679 962 return 1; 680 963 } 681 964 682 - void _tx_iq_calibration_winbond(struct hw_data *phw_data) 965 + static void _tx_iq_calibration_winbond(struct hw_data *phw_data) 683 966 { 684 967 u32 reg_agc_ctrl3; 685 968 #ifdef _DEBUG ··· 825 1108 } 826 1109 827 1110 /*****************************************************/ 828 - u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency) 1111 + static u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency) 829 1112 { 830 1113 u32 reg_mode_ctrl; 831 1114 s32 iqcal_tone_i; ··· 1099 1382 /*************************************************/ 1100 1383 1101 1384 /***************************************************************/ 1102 - void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency) 1385 + static void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency) 1103 1386 { 1104 1387 /* figo 20050523 marked this flag for can't compile for release */ 1105 1388 #ifdef _DEBUG