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ARM: dts: r8a7794: Add SCIF fallback compatibility strings

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

authored by

Geert Uytterhoeven and committed by
Simon Horman 06930a1f 3ffc90a3

+36 -18
+36 -18
arch/arm/boot/dts/r8a7794.dtsi
··· 282 282 }; 283 283 284 284 scifa0: serial@e6c40000 { 285 - compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 285 + compatible = "renesas,scifa-r8a7794", 286 + "renesas,rcar-gen2-scifa", "renesas,scifa"; 286 287 reg = <0 0xe6c40000 0 64>; 287 288 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 288 289 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; ··· 295 294 }; 296 295 297 296 scifa1: serial@e6c50000 { 298 - compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 297 + compatible = "renesas,scifa-r8a7794", 298 + "renesas,rcar-gen2-scifa", "renesas,scifa"; 299 299 reg = <0 0xe6c50000 0 64>; 300 300 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 301 301 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; ··· 308 306 }; 309 307 310 308 scifa2: serial@e6c60000 { 311 - compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 309 + compatible = "renesas,scifa-r8a7794", 310 + "renesas,rcar-gen2-scifa", "renesas,scifa"; 312 311 reg = <0 0xe6c60000 0 64>; 313 312 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 314 313 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; ··· 321 318 }; 322 319 323 320 scifa3: serial@e6c70000 { 324 - compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 321 + compatible = "renesas,scifa-r8a7794", 322 + "renesas,rcar-gen2-scifa", "renesas,scifa"; 325 323 reg = <0 0xe6c70000 0 64>; 326 324 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 327 325 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; ··· 334 330 }; 335 331 336 332 scifa4: serial@e6c78000 { 337 - compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 333 + compatible = "renesas,scifa-r8a7794", 334 + "renesas,rcar-gen2-scifa", "renesas,scifa"; 338 335 reg = <0 0xe6c78000 0 64>; 339 336 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 340 337 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; ··· 347 342 }; 348 343 349 344 scifa5: serial@e6c80000 { 350 - compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 345 + compatible = "renesas,scifa-r8a7794", 346 + "renesas,rcar-gen2-scifa", "renesas,scifa"; 351 347 reg = <0 0xe6c80000 0 64>; 352 348 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 353 349 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; ··· 360 354 }; 361 355 362 356 scifb0: serial@e6c20000 { 363 - compatible = "renesas,scifb-r8a7794", "renesas,scifb"; 357 + compatible = "renesas,scifb-r8a7794", 358 + "renesas,rcar-gen2-scifb", "renesas,scifb"; 364 359 reg = <0 0xe6c20000 0 64>; 365 360 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 366 361 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; ··· 373 366 }; 374 367 375 368 scifb1: serial@e6c30000 { 376 - compatible = "renesas,scifb-r8a7794", "renesas,scifb"; 369 + compatible = "renesas,scifb-r8a7794", 370 + "renesas,rcar-gen2-scifb", "renesas,scifb"; 377 371 reg = <0 0xe6c30000 0 64>; 378 372 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 379 373 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; ··· 386 378 }; 387 379 388 380 scifb2: serial@e6ce0000 { 389 - compatible = "renesas,scifb-r8a7794", "renesas,scifb"; 381 + compatible = "renesas,scifb-r8a7794", 382 + "renesas,rcar-gen2-scifb", "renesas,scifb"; 390 383 reg = <0 0xe6ce0000 0 64>; 391 384 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 392 385 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; ··· 399 390 }; 400 391 401 392 scif0: serial@e6e60000 { 402 - compatible = "renesas,scif-r8a7794", "renesas,scif"; 393 + compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 394 + "renesas,scif"; 403 395 reg = <0 0xe6e60000 0 64>; 404 396 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 405 397 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>; ··· 412 402 }; 413 403 414 404 scif1: serial@e6e68000 { 415 - compatible = "renesas,scif-r8a7794", "renesas,scif"; 405 + compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 406 + "renesas,scif"; 416 407 reg = <0 0xe6e68000 0 64>; 417 408 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 418 409 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>; ··· 425 414 }; 426 415 427 416 scif2: serial@e6e58000 { 428 - compatible = "renesas,scif-r8a7794", "renesas,scif"; 417 + compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 418 + "renesas,scif"; 429 419 reg = <0 0xe6e58000 0 64>; 430 420 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 431 421 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>; ··· 438 426 }; 439 427 440 428 scif3: serial@e6ea8000 { 441 - compatible = "renesas,scif-r8a7794", "renesas,scif"; 429 + compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 430 + "renesas,scif"; 442 431 reg = <0 0xe6ea8000 0 64>; 443 432 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 444 433 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>; ··· 451 438 }; 452 439 453 440 scif4: serial@e6ee0000 { 454 - compatible = "renesas,scif-r8a7794", "renesas,scif"; 441 + compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 442 + "renesas,scif"; 455 443 reg = <0 0xe6ee0000 0 64>; 456 444 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 457 445 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>; ··· 464 450 }; 465 451 466 452 scif5: serial@e6ee8000 { 467 - compatible = "renesas,scif-r8a7794", "renesas,scif"; 453 + compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 454 + "renesas,scif"; 468 455 reg = <0 0xe6ee8000 0 64>; 469 456 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 470 457 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>; ··· 477 462 }; 478 463 479 464 hscif0: serial@e62c0000 { 480 - compatible = "renesas,hscif-r8a7794", "renesas,hscif"; 465 + compatible = "renesas,hscif-r8a7794", 466 + "renesas,rcar-gen2-hscif", "renesas,hscif"; 481 467 reg = <0 0xe62c0000 0 96>; 482 468 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 483 469 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>; ··· 490 474 }; 491 475 492 476 hscif1: serial@e62c8000 { 493 - compatible = "renesas,hscif-r8a7794", "renesas,hscif"; 477 + compatible = "renesas,hscif-r8a7794", 478 + "renesas,rcar-gen2-hscif", "renesas,hscif"; 494 479 reg = <0 0xe62c8000 0 96>; 495 480 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 496 481 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>; ··· 503 486 }; 504 487 505 488 hscif2: serial@e62d0000 { 506 - compatible = "renesas,hscif-r8a7794", "renesas,hscif"; 489 + compatible = "renesas,hscif-r8a7794", 490 + "renesas,rcar-gen2-hscif", "renesas,hscif"; 507 491 reg = <0 0xe62d0000 0 96>; 508 492 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 509 493 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;