tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'renesas-dt3-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Third Round of Renesas ARM Based SoC DT Updates for v3.16" from Simon
Horman:

r8a7791 (R-Car M2), r8a7779 (R-Car H1), r8a7778 (R-Car M1),
r8a7740 (R-Mobile A1) and r8a73a4 (R-Mobile APE6) SoCs
* Move interrupt-parent property to root node

r8a7791 (R-Car M2) and r8a7790 (R-Car H2) SoCs
* Add GPIO clocks

r8a7791 (R-Car M2) based Henninger board
* Add MSIOF0, QSPI and SDHI0/2 support
* Specify EXTAL frequency

r8a7779 (R-Car H1) based Marzen board
* Set SMSC lan to use irq-push-pull

r8a7740 (R-Mobile A1) SoC
* Remove duplicate interrupt-parent property

r8a7740 (R-Mobile A1) based Armadillo800 EVA board
* Add Ethernet support

* tag 'renesas-dt3-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7740 dtsi: Remove duplicate interrupt-parent property
ARM: shmobile: marzen-reference: Set SMSC lan to use irq-push-pull
ARM: shmobile: r8a7791 dtsi: Add GPIO clocks
ARM: shmobile: r8a7790 dtsi: Add GPIO clocks
ARM: shmobile: dts: Move interrupt-parent property to root node
ARM: shmobile: armadillo-reference dts: Add Ethernet support
ARM: shmobile: r8a7740 dtsi: Add Ethernet support
ARM: shmobile: henninger: add MSIOF0 DT support
ARM: shmobile: henninger: add QSPI DT support
ARM: shmobile: henninger: add SDHI0/2 DT support
ARM: shmobile: henninger: specify EXTAL frequency

Signed-off-by: Olof Johansson <olof@lixom.net>

Olof Johansson 0673836c 5669aab8

+200 -73
-18
arch/arm/boot/dts/r8a73a4.dtsi
··· 55 55 #interrupt-cells = <2>; 56 56 interrupt-controller; 57 57 reg = <0 0xe61c0000 0 0x200>; 58 - interrupt-parent = <&gic>; 59 58 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, 60 59 <0 1 IRQ_TYPE_LEVEL_HIGH>, 61 60 <0 2 IRQ_TYPE_LEVEL_HIGH>, ··· 94 95 #interrupt-cells = <2>; 95 96 interrupt-controller; 96 97 reg = <0 0xe61c0200 0 0x200>; 97 - interrupt-parent = <&gic>; 98 98 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, 99 99 <0 33 IRQ_TYPE_LEVEL_HIGH>, 100 100 <0 34 IRQ_TYPE_LEVEL_HIGH>, ··· 134 136 dma0: dma-controller@e6700020 { 135 137 compatible = "renesas,shdma-r8a73a4"; 136 138 reg = <0 0xe6700020 0 0x89e0>; 137 - interrupt-parent = <&gic>; 138 139 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH 139 140 0 200 IRQ_TYPE_LEVEL_HIGH 140 141 0 201 IRQ_TYPE_LEVEL_HIGH ··· 168 171 compatible = "renesas,rcar-thermal"; 169 172 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 170 173 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; 171 - interrupt-parent = <&gic>; 172 174 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 173 175 }; 174 176 ··· 176 180 #size-cells = <0>; 177 181 compatible = "renesas,rmobile-iic"; 178 182 reg = <0 0xe6500000 0 0x428>; 179 - interrupt-parent = <&gic>; 180 183 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 181 184 status = "disabled"; 182 185 }; ··· 185 190 #size-cells = <0>; 186 191 compatible = "renesas,rmobile-iic"; 187 192 reg = <0 0xe6510000 0 0x428>; 188 - interrupt-parent = <&gic>; 189 193 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; 190 194 status = "disabled"; 191 195 }; ··· 194 200 #size-cells = <0>; 195 201 compatible = "renesas,rmobile-iic"; 196 202 reg = <0 0xe6520000 0 0x428>; 197 - interrupt-parent = <&gic>; 198 203 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; 199 204 status = "disabled"; 200 205 }; ··· 203 210 #size-cells = <0>; 204 211 compatible = "renesas,rmobile-iic"; 205 212 reg = <0 0xe6530000 0 0x428>; 206 - interrupt-parent = <&gic>; 207 213 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; 208 214 status = "disabled"; 209 215 }; ··· 212 220 #size-cells = <0>; 213 221 compatible = "renesas,rmobile-iic"; 214 222 reg = <0 0xe6540000 0 0x428>; 215 - interrupt-parent = <&gic>; 216 223 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; 217 224 status = "disabled"; 218 225 }; ··· 221 230 #size-cells = <0>; 222 231 compatible = "renesas,rmobile-iic"; 223 232 reg = <0 0xe60b0000 0 0x428>; 224 - interrupt-parent = <&gic>; 225 233 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; 226 234 status = "disabled"; 227 235 }; ··· 230 240 #size-cells = <0>; 231 241 compatible = "renesas,rmobile-iic"; 232 242 reg = <0 0xe6550000 0 0x428>; 233 - interrupt-parent = <&gic>; 234 243 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 235 244 status = "disabled"; 236 245 }; ··· 239 250 #size-cells = <0>; 240 251 compatible = "renesas,rmobile-iic"; 241 252 reg = <0 0xe6560000 0 0x428>; 242 - interrupt-parent = <&gic>; 243 253 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; 244 254 status = "disabled"; 245 255 }; ··· 248 260 #size-cells = <0>; 249 261 compatible = "renesas,rmobile-iic"; 250 262 reg = <0 0xe6570000 0 0x428>; 251 - interrupt-parent = <&gic>; 252 263 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; 253 264 status = "disabled"; 254 265 }; ··· 255 268 mmcif0: mmc@ee200000 { 256 269 compatible = "renesas,sh-mmcif"; 257 270 reg = <0 0xee200000 0 0x80>; 258 - interrupt-parent = <&gic>; 259 271 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; 260 272 reg-io-width = <4>; 261 273 status = "disabled"; ··· 263 277 mmcif1: mmc@ee220000 { 264 278 compatible = "renesas,sh-mmcif"; 265 279 reg = <0 0xee220000 0 0x80>; 266 - interrupt-parent = <&gic>; 267 280 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; 268 281 reg-io-width = <4>; 269 282 status = "disabled"; ··· 294 309 sdhi0: sd@ee100000 { 295 310 compatible = "renesas,sdhi-r8a73a4"; 296 311 reg = <0 0xee100000 0 0x100>; 297 - interrupt-parent = <&gic>; 298 312 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 299 313 cap-sd-highspeed; 300 314 status = "disabled"; ··· 302 318 sdhi1: sd@ee120000 { 303 319 compatible = "renesas,sdhi-r8a73a4"; 304 320 reg = <0 0xee120000 0 0x100>; 305 - interrupt-parent = <&gic>; 306 321 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; 307 322 cap-sd-highspeed; 308 323 status = "disabled"; ··· 310 327 sdhi2: sd@ee140000 { 311 328 compatible = "renesas,sdhi-r8a73a4"; 312 329 reg = <0 0xee140000 0 0x100>; 313 - interrupt-parent = <&gic>; 314 330 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; 315 331 cap-sd-highspeed; 316 332 status = "disabled";
+17
arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
··· 158 158 }; 159 159 }; 160 160 161 + &ether { 162 + pinctrl-0 = <&ether_pins>; 163 + pinctrl-names = "default"; 164 + 165 + phy-handle = <&phy0>; 166 + status = "ok"; 167 + 168 + phy0: ethernet-phy@0 { 169 + reg = <0>; 170 + }; 171 + }; 172 + 161 173 &i2c0 { 162 174 status = "okay"; 163 175 touchscreen@55 { ··· 200 188 &pfc { 201 189 pinctrl-0 = <&scifa1_pins>; 202 190 pinctrl-names = "default"; 191 + 192 + ether_pins: ether { 193 + renesas,groups = "gether_mii", "gether_int"; 194 + renesas,function = "gether"; 195 + }; 203 196 204 197 scifa1_pins: serial1 { 205 198 renesas,groups = "scifa1_data";
+13 -11
arch/arm/boot/dts/r8a7740.dtsi
··· 14 14 15 15 / { 16 16 compatible = "renesas,r8a7740"; 17 + interrupt-parent = <&gic>; 17 18 18 19 cpus { 19 20 #address-cells = <1>; ··· 49 48 <0xe6900020 1>, 50 49 <0xe6900040 1>, 51 50 <0xe6900060 1>; 52 - interrupt-parent = <&gic>; 53 51 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 54 52 0 149 IRQ_TYPE_LEVEL_HIGH 55 53 0 149 IRQ_TYPE_LEVEL_HIGH ··· 69 69 <0xe6900024 1>, 70 70 <0xe6900044 1>, 71 71 <0xe6900064 1>; 72 - interrupt-parent = <&gic>; 73 72 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 74 73 0 149 IRQ_TYPE_LEVEL_HIGH 75 74 0 149 IRQ_TYPE_LEVEL_HIGH ··· 89 90 <0xe6900028 1>, 90 91 <0xe6900048 1>, 91 92 <0xe6900068 1>; 92 - interrupt-parent = <&gic>; 93 93 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 94 94 0 149 IRQ_TYPE_LEVEL_HIGH 95 95 0 149 IRQ_TYPE_LEVEL_HIGH ··· 109 111 <0xe690002c 1>, 110 112 <0xe690004c 1>, 111 113 <0xe690006c 1>; 112 - interrupt-parent = <&gic>; 113 114 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 114 115 0 149 IRQ_TYPE_LEVEL_HIGH 115 116 0 149 IRQ_TYPE_LEVEL_HIGH ··· 119 122 0 149 IRQ_TYPE_LEVEL_HIGH>; 120 123 }; 121 124 125 + ether: ethernet@e9a00000 { 126 + compatible = "renesas,gether-r8a7740"; 127 + reg = <0xe9a00000 0x800>, 128 + <0xe9a01800 0x800>; 129 + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 130 + /* clocks = <&mstp3_clks R8A7740_CLK_GETHER>; */ 131 + phy-mode = "mii"; 132 + #address-cells = <1>; 133 + #size-cells = <0>; 134 + status = "disabled"; 135 + }; 136 + 122 137 i2c0: i2c@fff20000 { 123 138 #address-cells = <1>; 124 139 #size-cells = <0>; 125 140 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; 126 141 reg = <0xfff20000 0x425>; 127 - interrupt-parent = <&gic>; 128 142 interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH 129 143 0 202 IRQ_TYPE_LEVEL_HIGH 130 144 0 203 IRQ_TYPE_LEVEL_HIGH ··· 148 140 #size-cells = <0>; 149 141 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; 150 142 reg = <0xe6c20000 0x425>; 151 - interrupt-parent = <&gic>; 152 143 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH 153 144 0 71 IRQ_TYPE_LEVEL_HIGH 154 145 0 72 IRQ_TYPE_LEVEL_HIGH ··· 182 175 mmcif0: mmc@e6bd0000 { 183 176 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; 184 177 reg = <0xe6bd0000 0x100>; 185 - interrupt-parent = <&gic>; 186 178 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH 187 179 0 57 IRQ_TYPE_LEVEL_HIGH>; 188 180 status = "disabled"; ··· 190 184 sdhi0: sd@e6850000 { 191 185 compatible = "renesas,sdhi-r8a7740"; 192 186 reg = <0xe6850000 0x100>; 193 - interrupt-parent = <&gic>; 194 187 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH 195 188 0 118 IRQ_TYPE_LEVEL_HIGH 196 189 0 119 IRQ_TYPE_LEVEL_HIGH>; ··· 201 196 sdhi1: sd@e6860000 { 202 197 compatible = "renesas,sdhi-r8a7740"; 203 198 reg = <0xe6860000 0x100>; 204 - interrupt-parent = <&gic>; 205 199 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH 206 200 0 122 IRQ_TYPE_LEVEL_HIGH 207 201 0 123 IRQ_TYPE_LEVEL_HIGH>; ··· 212 208 sdhi2: sd@e6870000 { 213 209 compatible = "renesas,sdhi-r8a7740"; 214 210 reg = <0xe6870000 0x100>; 215 - interrupt-parent = <&gic>; 216 211 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH 217 212 0 126 IRQ_TYPE_LEVEL_HIGH 218 213 0 127 IRQ_TYPE_LEVEL_HIGH>; ··· 224 221 #sound-dai-cells = <1>; 225 222 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; 226 223 reg = <0xfe1f0000 0x400>; 227 - interrupt-parent = <&gic>; 228 224 interrupts = <0 9 0x4>; 229 225 status = "disabled"; 230 226 };
+1 -17
arch/arm/boot/dts/r8a7778.dtsi
··· 20 20 21 21 / { 22 22 compatible = "renesas,r8a7778"; 23 + interrupt-parent = <&gic>; 23 24 24 25 cpus { 25 26 cpu@0 { ··· 53 52 <0xfe780024 4>, 54 53 <0xfe780044 4>, 55 54 <0xfe780064 4>; 56 - interrupt-parent = <&gic>; 57 55 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH 58 56 0 28 IRQ_TYPE_LEVEL_HIGH 59 57 0 29 IRQ_TYPE_LEVEL_HIGH ··· 63 63 gpio0: gpio@ffc40000 { 64 64 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 65 65 reg = <0xffc40000 0x2c>; 66 - interrupt-parent = <&gic>; 67 66 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 68 67 #gpio-cells = <2>; 69 68 gpio-controller; ··· 74 75 gpio1: gpio@ffc41000 { 75 76 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 76 77 reg = <0xffc41000 0x2c>; 77 - interrupt-parent = <&gic>; 78 78 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 79 79 #gpio-cells = <2>; 80 80 gpio-controller; ··· 85 87 gpio2: gpio@ffc42000 { 86 88 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 87 89 reg = <0xffc42000 0x2c>; 88 - interrupt-parent = <&gic>; 89 90 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 90 91 #gpio-cells = <2>; 91 92 gpio-controller; ··· 96 99 gpio3: gpio@ffc43000 { 97 100 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 98 101 reg = <0xffc43000 0x2c>; 99 - interrupt-parent = <&gic>; 100 102 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 101 103 #gpio-cells = <2>; 102 104 gpio-controller; ··· 107 111 gpio4: gpio@ffc44000 { 108 112 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 109 113 reg = <0xffc44000 0x2c>; 110 - interrupt-parent = <&gic>; 111 114 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 112 115 #gpio-cells = <2>; 113 116 gpio-controller; ··· 125 130 #size-cells = <0>; 126 131 compatible = "renesas,i2c-r8a7778"; 127 132 reg = <0xffc70000 0x1000>; 128 - interrupt-parent = <&gic>; 129 133 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; 130 134 status = "disabled"; 131 135 }; ··· 134 140 #size-cells = <0>; 135 141 compatible = "renesas,i2c-r8a7778"; 136 142 reg = <0xffc71000 0x1000>; 137 - interrupt-parent = <&gic>; 138 143 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 139 144 status = "disabled"; 140 145 }; ··· 143 150 #size-cells = <0>; 144 151 compatible = "renesas,i2c-r8a7778"; 145 152 reg = <0xffc72000 0x1000>; 146 - interrupt-parent = <&gic>; 147 153 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; 148 154 status = "disabled"; 149 155 }; ··· 152 160 #size-cells = <0>; 153 161 compatible = "renesas,i2c-r8a7778"; 154 162 reg = <0xffc73000 0x1000>; 155 - interrupt-parent = <&gic>; 156 163 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; 157 164 status = "disabled"; 158 165 }; ··· 159 168 mmcif: mmc@ffe4e000 { 160 169 compatible = "renesas,sh-mmcif"; 161 170 reg = <0xffe4e000 0x100>; 162 - interrupt-parent = <&gic>; 163 171 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; 164 172 status = "disabled"; 165 173 }; ··· 166 176 sdhi0: sd@ffe4c000 { 167 177 compatible = "renesas,sdhi-r8a7778"; 168 178 reg = <0xffe4c000 0x100>; 169 - interrupt-parent = <&gic>; 170 179 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; 171 180 cap-sd-highspeed; 172 181 cap-sdio-irq; ··· 175 186 sdhi1: sd@ffe4d000 { 176 187 compatible = "renesas,sdhi-r8a7778"; 177 188 reg = <0xffe4d000 0x100>; 178 - interrupt-parent = <&gic>; 179 189 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 180 190 cap-sd-highspeed; 181 191 cap-sdio-irq; ··· 184 196 sdhi2: sd@ffe4f000 { 185 197 compatible = "renesas,sdhi-r8a7778"; 186 198 reg = <0xffe4f000 0x100>; 187 - interrupt-parent = <&gic>; 188 199 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 189 200 cap-sd-highspeed; 190 201 cap-sdio-irq; ··· 193 206 hspi0: spi@fffc7000 { 194 207 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 195 208 reg = <0xfffc7000 0x18>; 196 - interrupt-parent = <&gic>; 197 209 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; 198 210 #address-cells = <1>; 199 211 #size-cells = <0>; ··· 202 216 hspi1: spi@fffc8000 { 203 217 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 204 218 reg = <0xfffc8000 0x18>; 205 - interrupt-parent = <&gic>; 206 219 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 207 220 #address-cells = <1>; 208 221 #size-cells = <0>; ··· 211 226 hspi2: spi@fffc6000 { 212 227 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 213 228 reg = <0xfffc6000 0x18>; 214 - interrupt-parent = <&gic>; 215 229 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 216 230 #address-cells = <1>; 217 231 #size-cells = <0>;
+1
arch/arm/boot/dts/r8a7779-marzen-reference.dts
··· 45 45 phy-mode = "mii"; 46 46 interrupt-parent = <&irqpin0>; 47 47 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 48 + smsc,irq-push-pull; 48 49 reg-io-width = <4>; 49 50 vddvario-supply = <&fixedregulator3v3>; 50 51 vdd33a-supply = <&fixedregulator3v3>;
+1 -20
arch/arm/boot/dts/r8a7779.dtsi
··· 15 15 16 16 / { 17 17 compatible = "renesas,r8a7779"; 18 + interrupt-parent = <&gic>; 18 19 19 20 cpus { 20 21 #address-cells = <1>; ··· 60 59 gpio0: gpio@ffc40000 { 61 60 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 62 61 reg = <0xffc40000 0x2c>; 63 - interrupt-parent = <&gic>; 64 62 interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>; 65 63 #gpio-cells = <2>; 66 64 gpio-controller; ··· 71 71 gpio1: gpio@ffc41000 { 72 72 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 73 73 reg = <0xffc41000 0x2c>; 74 - interrupt-parent = <&gic>; 75 74 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>; 76 75 #gpio-cells = <2>; 77 76 gpio-controller; ··· 82 83 gpio2: gpio@ffc42000 { 83 84 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 84 85 reg = <0xffc42000 0x2c>; 85 - interrupt-parent = <&gic>; 86 86 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; 87 87 #gpio-cells = <2>; 88 88 gpio-controller; ··· 93 95 gpio3: gpio@ffc43000 { 94 96 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 95 97 reg = <0xffc43000 0x2c>; 96 - interrupt-parent = <&gic>; 97 98 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; 98 99 #gpio-cells = <2>; 99 100 gpio-controller; ··· 104 107 gpio4: gpio@ffc44000 { 105 108 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 106 109 reg = <0xffc44000 0x2c>; 107 - interrupt-parent = <&gic>; 108 110 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; 109 111 #gpio-cells = <2>; 110 112 gpio-controller; ··· 115 119 gpio5: gpio@ffc45000 { 116 120 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 117 121 reg = <0xffc45000 0x2c>; 118 - interrupt-parent = <&gic>; 119 122 interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>; 120 123 #gpio-cells = <2>; 121 124 gpio-controller; ··· 126 131 gpio6: gpio@ffc46000 { 127 132 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 128 133 reg = <0xffc46000 0x2c>; 129 - interrupt-parent = <&gic>; 130 134 interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>; 131 135 #gpio-cells = <2>; 132 136 gpio-controller; ··· 144 150 <0xfe780024 4>, 145 151 <0xfe780044 4>, 146 152 <0xfe780064 4>; 147 - interrupt-parent = <&gic>; 148 153 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH 149 154 0 28 IRQ_TYPE_LEVEL_HIGH 150 155 0 29 IRQ_TYPE_LEVEL_HIGH ··· 156 163 #size-cells = <0>; 157 164 compatible = "renesas,i2c-r8a7779"; 158 165 reg = <0xffc70000 0x1000>; 159 - interrupt-parent = <&gic>; 160 166 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; 161 167 status = "disabled"; 162 168 }; ··· 165 173 #size-cells = <0>; 166 174 compatible = "renesas,i2c-r8a7779"; 167 175 reg = <0xffc71000 0x1000>; 168 - interrupt-parent = <&gic>; 169 176 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 170 177 status = "disabled"; 171 178 }; ··· 174 183 #size-cells = <0>; 175 184 compatible = "renesas,i2c-r8a7779"; 176 185 reg = <0xffc72000 0x1000>; 177 - interrupt-parent = <&gic>; 178 186 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 179 187 status = "disabled"; 180 188 }; ··· 183 193 #size-cells = <0>; 184 194 compatible = "renesas,i2c-r8a7779"; 185 195 reg = <0xffc73000 0x1000>; 186 - interrupt-parent = <&gic>; 187 196 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 188 197 status = "disabled"; 189 198 }; ··· 200 211 sata: sata@fc600000 { 201 212 compatible = "renesas,rcar-sata"; 202 213 reg = <0xfc600000 0x2000>; 203 - interrupt-parent = <&gic>; 204 214 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 205 215 }; 206 216 207 217 sdhi0: sd@ffe4c000 { 208 218 compatible = "renesas,sdhi-r8a7779"; 209 219 reg = <0xffe4c000 0x100>; 210 - interrupt-parent = <&gic>; 211 220 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 212 221 cap-sd-highspeed; 213 222 cap-sdio-irq; ··· 215 228 sdhi1: sd@ffe4d000 { 216 229 compatible = "renesas,sdhi-r8a7779"; 217 230 reg = <0xffe4d000 0x100>; 218 - interrupt-parent = <&gic>; 219 231 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 220 232 cap-sd-highspeed; 221 233 cap-sdio-irq; ··· 224 238 sdhi2: sd@ffe4e000 { 225 239 compatible = "renesas,sdhi-r8a7779"; 226 240 reg = <0xffe4e000 0x100>; 227 - interrupt-parent = <&gic>; 228 241 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 229 242 cap-sd-highspeed; 230 243 cap-sdio-irq; ··· 233 248 sdhi3: sd@ffe4f000 { 234 249 compatible = "renesas,sdhi-r8a7779"; 235 250 reg = <0xffe4f000 0x100>; 236 - interrupt-parent = <&gic>; 237 251 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 238 252 cap-sd-highspeed; 239 253 cap-sdio-irq; ··· 242 258 hspi0: spi@fffc7000 { 243 259 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 244 260 reg = <0xfffc7000 0x18>; 245 - interrupt-parent = <&gic>; 246 261 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 247 262 #address-cells = <1>; 248 263 #size-cells = <0>; ··· 251 268 hspi1: spi@fffc8000 { 252 269 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 253 270 reg = <0xfffc8000 0x18>; 254 - interrupt-parent = <&gic>; 255 271 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 256 272 #address-cells = <1>; 257 273 #size-cells = <0>; ··· 260 278 hspi2: spi@fffc6000 { 261 279 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 262 280 reg = <0xfffc6000 0x18>; 263 - interrupt-parent = <&gic>; 264 281 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 265 282 #address-cells = <1>; 266 283 #size-cells = <0>;
+12 -1
arch/arm/boot/dts/r8a7790.dtsi
··· 117 117 gpio-ranges = <&pfc 0 0 32>; 118 118 #interrupt-cells = <2>; 119 119 interrupt-controller; 120 + clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; 120 121 }; 121 122 122 123 gpio1: gpio@e6051000 { ··· 129 128 gpio-ranges = <&pfc 0 32 32>; 130 129 #interrupt-cells = <2>; 131 130 interrupt-controller; 131 + clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; 132 132 }; 133 133 134 134 gpio2: gpio@e6052000 { ··· 141 139 gpio-ranges = <&pfc 0 64 32>; 142 140 #interrupt-cells = <2>; 143 141 interrupt-controller; 142 + clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; 144 143 }; 145 144 146 145 gpio3: gpio@e6053000 { ··· 153 150 gpio-ranges = <&pfc 0 96 32>; 154 151 #interrupt-cells = <2>; 155 152 interrupt-controller; 153 + clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; 156 154 }; 157 155 158 156 gpio4: gpio@e6054000 { ··· 165 161 gpio-ranges = <&pfc 0 128 32>; 166 162 #interrupt-cells = <2>; 167 163 interrupt-controller; 164 + clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; 168 165 }; 169 166 170 167 gpio5: gpio@e6055000 { ··· 177 172 gpio-ranges = <&pfc 0 160 32>; 178 173 #interrupt-cells = <2>; 179 174 interrupt-controller; 175 + clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; 180 176 }; 181 177 182 178 thermal@e61f0000 { ··· 808 802 mstp9_clks: mstp9_clks@e6150994 { 809 803 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 810 804 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; 811 - clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, 805 + clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, 806 + <&cp_clk>, <&cp_clk>, <&cp_clk>, 807 + <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, 812 808 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; 813 809 #clock-cells = <1>; 814 810 renesas,clock-indices = < 811 + R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 812 + R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 815 813 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS 816 814 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 817 815 >; 818 816 clock-output-names = 817 + "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", 819 818 "rcan1", "rcan0", "qspi_mod", "iic3", 820 819 "i2c3", "i2c2", "i2c1", "i2c0"; 821 820 };
+139
arch/arm/boot/dts/r8a7791-henninger.dts
··· 11 11 12 12 /dts-v1/; 13 13 #include "r8a7791.dtsi" 14 + #include <dt-bindings/gpio/gpio.h> 14 15 15 16 / { 16 17 model = "Henninger"; ··· 34 33 device_type = "memory"; 35 34 reg = <2 0x00000000 0 0x40000000>; 36 35 }; 36 + 37 + vcc_sdhi0: regulator@0 { 38 + compatible = "regulator-fixed"; 39 + 40 + regulator-name = "SDHI0 Vcc"; 41 + regulator-min-microvolt = <3300000>; 42 + regulator-max-microvolt = <3300000>; 43 + regulator-always-on; 44 + }; 45 + 46 + vccq_sdhi0: regulator@1 { 47 + compatible = "regulator-gpio"; 48 + 49 + regulator-name = "SDHI0 VccQ"; 50 + regulator-min-microvolt = <1800000>; 51 + regulator-max-microvolt = <3300000>; 52 + 53 + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 54 + gpios-states = <1>; 55 + states = <3300000 1 56 + 1800000 0>; 57 + }; 58 + 59 + vcc_sdhi2: regulator@2 { 60 + compatible = "regulator-fixed"; 61 + 62 + regulator-name = "SDHI2 Vcc"; 63 + regulator-min-microvolt = <3300000>; 64 + regulator-max-microvolt = <3300000>; 65 + regulator-always-on; 66 + }; 67 + 68 + vccq_sdhi2: regulator@3 { 69 + compatible = "regulator-gpio"; 70 + 71 + regulator-name = "SDHI2 VccQ"; 72 + regulator-min-microvolt = <1800000>; 73 + regulator-max-microvolt = <3300000>; 74 + 75 + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; 76 + gpios-states = <1>; 77 + states = <3300000 1 78 + 1800000 0>; 79 + }; 80 + }; 81 + 82 + &extal_clk { 83 + clock-frequency = <20000000>; 37 84 }; 38 85 39 86 &pfc { ··· 98 49 phy1_pins: phy1 { 99 50 renesas,groups = "intc_irq0"; 100 51 renesas,function = "intc"; 52 + }; 53 + 54 + sdhi0_pins: sd0 { 55 + renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; 56 + renesas,function = "sdhi0"; 57 + }; 58 + 59 + sdhi2_pins: sd2 { 60 + renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; 61 + renesas,function = "sdhi2"; 62 + }; 63 + 64 + qspi_pins: spi0 { 65 + renesas,groups = "qspi_ctrl", "qspi_data4"; 66 + renesas,function = "qspi"; 67 + }; 68 + 69 + msiof0_pins: spi1 { 70 + renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", 71 + "msiof0_tx"; 72 + renesas,function = "msiof0"; 101 73 }; 102 74 }; 103 75 ··· 147 77 148 78 &sata0 { 149 79 status = "okay"; 80 + }; 81 + 82 + &sdhi0 { 83 + pinctrl-0 = <&sdhi0_pins>; 84 + pinctrl-names = "default"; 85 + 86 + vmmc-supply = <&vcc_sdhi0>; 87 + vqmmc-supply = <&vccq_sdhi0>; 88 + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; 89 + wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; 90 + status = "okay"; 91 + }; 92 + 93 + &sdhi2 { 94 + pinctrl-0 = <&sdhi2_pins>; 95 + pinctrl-names = "default"; 96 + 97 + vmmc-supply = <&vcc_sdhi2>; 98 + vqmmc-supply = <&vccq_sdhi2>; 99 + cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; 100 + status = "okay"; 101 + }; 102 + 103 + &qspi { 104 + pinctrl-0 = <&qspi_pins>; 105 + pinctrl-names = "default"; 106 + 107 + status = "okay"; 108 + 109 + flash@0 { 110 + #address-cells = <1>; 111 + #size-cells = <1>; 112 + compatible = "spansion,s25fl512s"; 113 + reg = <0>; 114 + spi-max-frequency = <30000000>; 115 + spi-tx-bus-width = <4>; 116 + spi-rx-bus-width = <4>; 117 + m25p,fast-read; 118 + 119 + partition@0 { 120 + label = "loader_prg"; 121 + reg = <0x00000000 0x00040000>; 122 + read-only; 123 + }; 124 + partition@40000 { 125 + label = "user_prg"; 126 + reg = <0x00040000 0x00400000>; 127 + read-only; 128 + }; 129 + partition@440000 { 130 + label = "flash_fs"; 131 + reg = <0x00440000 0x03bc0000>; 132 + }; 133 + }; 134 + }; 135 + 136 + &msiof0 { 137 + pinctrl-0 = <&msiof0_pins>; 138 + pinctrl-names = "default"; 139 + 140 + status = "okay"; 141 + 142 + pmic@0 { 143 + compatible = "renesas,r2a11302ft"; 144 + reg = <0>; 145 + spi-max-frequency = <6000000>; 146 + spi-cpol; 147 + spi-cpha; 148 + }; 150 149 };
+16 -6
arch/arm/boot/dts/r8a7791.dtsi
··· 76 76 gpio-ranges = <&pfc 0 0 32>; 77 77 #interrupt-cells = <2>; 78 78 interrupt-controller; 79 + clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; 79 80 }; 80 81 81 82 gpio1: gpio@e6051000 { ··· 88 87 gpio-ranges = <&pfc 0 32 32>; 89 88 #interrupt-cells = <2>; 90 89 interrupt-controller; 90 + clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; 91 91 }; 92 92 93 93 gpio2: gpio@e6052000 { ··· 100 98 gpio-ranges = <&pfc 0 64 32>; 101 99 #interrupt-cells = <2>; 102 100 interrupt-controller; 101 + clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; 103 102 }; 104 103 105 104 gpio3: gpio@e6053000 { ··· 112 109 gpio-ranges = <&pfc 0 96 32>; 113 110 #interrupt-cells = <2>; 114 111 interrupt-controller; 112 + clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; 115 113 }; 116 114 117 115 gpio4: gpio@e6054000 { ··· 124 120 gpio-ranges = <&pfc 0 128 32>; 125 121 #interrupt-cells = <2>; 126 122 interrupt-controller; 123 + clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; 127 124 }; 128 125 129 126 gpio5: gpio@e6055000 { ··· 136 131 gpio-ranges = <&pfc 0 160 32>; 137 132 #interrupt-cells = <2>; 138 133 interrupt-controller; 134 + clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; 139 135 }; 140 136 141 137 gpio6: gpio@e6055400 { ··· 148 142 gpio-ranges = <&pfc 0 192 32>; 149 143 #interrupt-cells = <2>; 150 144 interrupt-controller; 145 + clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; 151 146 }; 152 147 153 148 gpio7: gpio@e6055800 { ··· 160 153 gpio-ranges = <&pfc 0 224 26>; 161 154 #interrupt-cells = <2>; 162 155 interrupt-controller; 156 + clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; 163 157 }; 164 158 165 159 thermal@e61f0000 { ··· 297 289 sdhi0: sd@ee100000 { 298 290 compatible = "renesas,sdhi-r8a7791"; 299 291 reg = <0 0xee100000 0 0x200>; 300 - interrupt-parent = <&gic>; 301 292 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 302 293 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; 303 294 status = "disabled"; ··· 305 298 sdhi1: sd@ee140000 { 306 299 compatible = "renesas,sdhi-r8a7791"; 307 300 reg = <0 0xee140000 0 0x100>; 308 - interrupt-parent = <&gic>; 309 301 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; 310 302 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; 311 303 status = "disabled"; ··· 313 307 sdhi2: sd@ee160000 { 314 308 compatible = "renesas,sdhi-r8a7791"; 315 309 reg = <0 0xee160000 0 0x100>; 316 - interrupt-parent = <&gic>; 317 310 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; 318 311 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; 319 312 status = "disabled"; ··· 810 805 mstp9_clks: mstp9_clks@e6150994 { 811 806 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 812 807 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; 813 - clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, 808 + clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 809 + <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 810 + <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, 814 811 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, 815 812 <&hp_clk>, <&hp_clk>; 816 813 #clock-cells = <1>; 817 814 renesas,clock-indices = < 815 + R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 816 + R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 818 817 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 819 818 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 820 819 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 821 820 >; 822 821 clock-output-names = 823 - "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", 824 - "i2c2", "i2c1", "i2c0"; 822 + "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", 823 + "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", 824 + "i2c1", "i2c0"; 825 825 }; 826 826 mstp11_clks: mstp11_clks@e615099c { 827 827 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";