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ARM: Provide common header for hard_smp_processor_id()

Provide a common header to read the SMP CPU number from the MPIDR.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Russell King 06717352 971acb9b

+18 -53
+12
arch/arm/include/asm/smp_mpidr.h
··· 1 + #ifndef ASMARM_SMP_MIDR_H 2 + #define ASMARM_SMP_MIDR_H 3 + 4 + #define hard_smp_processor_id() \ 5 + ({ \ 6 + unsigned int cpunum; \ 7 + __asm__("mrc p15, 0, %0, c0, c0, 5\n" \ 8 + : "=r" (cpunum)); \ 9 + cpunum &= 0x0F; \ 10 + }) 11 + 12 + #endif
+1 -9
arch/arm/mach-realview/include/mach/smp.h
··· 1 1 #ifndef ASMARM_ARCH_SMP_H 2 2 #define ASMARM_ARCH_SMP_H 3 3 4 - 5 4 #include <asm/hardware/gic.h> 6 - 7 - #define hard_smp_processor_id() \ 8 - ({ \ 9 - unsigned int cpunum; \ 10 - __asm__("mrc p15, 0, %0, c0, c0, 5" \ 11 - : "=r" (cpunum)); \ 12 - cpunum &= 0x0F; \ 13 - }) 5 + #include <asm/smp_mpidr.h> 14 6 15 7 /* 16 8 * We use IRQ1 as the IPI
+1 -8
arch/arm/mach-s5pv310/include/mach/smp.h
··· 7 7 #define ASM_ARCH_SMP_H __FILE__ 8 8 9 9 #include <asm/hardware/gic.h> 10 + #include <asm/smp_mpidr.h> 10 11 11 12 extern void __iomem *gic_cpu_base_addr; 12 - 13 - #define hard_smp_processor_id() \ 14 - ({ \ 15 - unsigned int cpunum; \ 16 - __asm__("mrc p15, 0, %0, c0, c0, 5" \ 17 - : "=r" (cpunum)); \ 18 - cpunum &= 0x03; \ 19 - }) 20 13 21 14 /* 22 15 * We use IRQ1 as the IPI
+1 -9
arch/arm/mach-tegra/include/mach/smp.h
··· 1 1 #ifndef ASMARM_ARCH_SMP_H 2 2 #define ASMARM_ARCH_SMP_H 3 3 4 - 5 4 #include <asm/hardware/gic.h> 6 - 7 - #define hard_smp_processor_id() \ 8 - ({ \ 9 - unsigned int cpunum; \ 10 - __asm__("mrc p15, 0, %0, c0, c0, 5" \ 11 - : "=r" (cpunum)); \ 12 - cpunum &= 0x0F; \ 13 - }) 5 + #include <asm/smp_mpidr.h> 14 6 15 7 /* 16 8 * We use IRQ1 as the IPI
+1 -8
arch/arm/mach-ux500/include/mach/smp.h
··· 10 10 #define ASMARM_ARCH_SMP_H 11 11 12 12 #include <asm/hardware/gic.h> 13 + #include <asm/smp_mpidr.h> 13 14 14 15 /* This is required to wakeup the secondary core */ 15 16 extern void u8500_secondary_startup(void); 16 - 17 - #define hard_smp_processor_id() \ 18 - ({ \ 19 - unsigned int cpunum; \ 20 - __asm__("mrc p15, 0, %0, c0, c0, 5" \ 21 - : "=r" (cpunum)); \ 22 - cpunum &= 0x0F; \ 23 - }) 24 17 25 18 /* 26 19 * We use IRQ1 as the IPI
+1 -8
arch/arm/mach-vexpress/include/mach/smp.h
··· 2 2 #define __MACH_SMP_H 3 3 4 4 #include <asm/hardware/gic.h> 5 - 6 - #define hard_smp_processor_id() \ 7 - ({ \ 8 - unsigned int cpunum; \ 9 - __asm__("mrc p15, 0, %0, c0, c0, 5" \ 10 - : "=r" (cpunum)); \ 11 - cpunum &= 0x0F; \ 12 - }) 5 + #include <asm/smp_mpidr.h> 13 6 14 7 /* 15 8 * We use IRQ1 as the IPI
+1 -11
arch/arm/plat-omap/include/plat/smp.h
··· 18 18 #define OMAP_ARCH_SMP_H 19 19 20 20 #include <asm/hardware/gic.h> 21 + #include <asm/smp_mpidr.h> 21 22 22 23 /* Needed for secondary core boot */ 23 24 extern void omap_secondary_startup(void); ··· 33 32 { 34 33 gic_raise_softirq(mask, 1); 35 34 } 36 - 37 - /* 38 - * Read MPIDR: Multiprocessor affinity register 39 - */ 40 - #define hard_smp_processor_id() \ 41 - ({ \ 42 - unsigned int cpunum; \ 43 - __asm__("mrc p15, 0, %0, c0, c0, 5" \ 44 - : "=r" (cpunum)); \ 45 - cpunum &= 0x0F; \ 46 - }) 47 35 48 36 #endif