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dt-bindings: memory-controllers: qcom,ebi2: Split out child node properties
In order to validate devices in child nodes, the device schemas need to
reference any child node properties. In order to do that, the properties
for child nodes need to be included in mc-peripheral-props.yaml.
"reg: { maxItems: 1 }" was also incorrect. It's up to the device schemas
how many reg entries they have.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250203-dt-lan9115-fix-v1-2-eb35389a7365@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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+1
Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml
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Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml
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Documentation/devicetree/bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml
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Documentation/devicetree/bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2-peripheral-props.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Peripheral Properties for Qualcomm External Bus Interface 2 (EBI2)
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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properties:
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# SLOW chip selects
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qcom,xmem-recovery-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The time the memory continues to drive the data bus after OE
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is de-asserted, in order to avoid contention on the data bus.
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They are inserted when reading one CS and switching to another
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CS or read followed by write on the same CS. Minimum value is
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actually 1, so a value of 0 will still yield 1 recovery cycle.
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minimum: 0
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maximum: 15
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qcom,xmem-write-hold-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The extra cycles inserted after every write minimum 1. The
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data out is driven from the time WE is asserted until CS is
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asserted. With a hold of 1 (value = 0), the CS stays active
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for 1 extra cycle, etc.
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minimum: 0
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maximum: 15
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+
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qcom,xmem-write-delta-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The initial latency for write cycles inserted for the first
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write to a page or burst memory.
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minimum: 0
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maximum: 255
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qcom,xmem-read-delta-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The initial latency for read cycles inserted for the first
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read to a page or burst memory.
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minimum: 0
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maximum: 255
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qcom,xmem-write-wait-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The number of wait cycles for every write access.
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minimum: 0
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maximum: 15
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qcom,xmem-read-wait-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The number of wait cycles for every read access.
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minimum: 0
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maximum: 15
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# FAST chip selects
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qcom,xmem-address-hold-enable:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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Holds the address for an extra cycle to meet hold time
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requirements with ADV assertion, when set to 1.
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enum: [ 0, 1 ]
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qcom,xmem-adv-to-oe-recovery-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The number of cycles elapsed before an OE assertion, with
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respect to the cycle where ADV (address valid) is asserted.
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minimum: 0
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maximum: 3
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qcom,xmem-read-hold-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The length in cycles of the first segment of a read transfer.
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For a single read transfer this will be the time from CS
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assertion to OE assertion.
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minimum: 0
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maximum: 15
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additionalProperties: true
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Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml
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Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml
···
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"^.*@[0-5],[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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reg:
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maxItems: 1
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-
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# SLOW chip selects
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qcom,xmem-recovery-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The time the memory continues to drive the data bus after OE
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is de-asserted, in order to avoid contention on the data bus.
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They are inserted when reading one CS and switching to another
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CS or read followed by write on the same CS. Minimum value is
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actually 1, so a value of 0 will still yield 1 recovery cycle.
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minimum: 0
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maximum: 15
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-
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qcom,xmem-write-hold-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The extra cycles inserted after every write minimum 1. The
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data out is driven from the time WE is asserted until CS is
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asserted. With a hold of 1 (value = 0), the CS stays active
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for 1 extra cycle, etc.
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minimum: 0
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maximum: 15
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-
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qcom,xmem-write-delta-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The initial latency for write cycles inserted for the first
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write to a page or burst memory.
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minimum: 0
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maximum: 255
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-
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qcom,xmem-read-delta-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The initial latency for read cycles inserted for the first
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read to a page or burst memory.
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minimum: 0
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maximum: 255
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-
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qcom,xmem-write-wait-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The number of wait cycles for every write access.
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minimum: 0
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maximum: 15
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-
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qcom,xmem-read-wait-cycles:
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-
$ref: /schemas/types.yaml#/definitions/uint32
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-
description: >
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The number of wait cycles for every read access.
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minimum: 0
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maximum: 15
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-
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-
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# FAST chip selects
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qcom,xmem-address-hold-enable:
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-
$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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Holds the address for an extra cycle to meet hold time
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requirements with ADV assertion, when set to 1.
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enum: [ 0, 1 ]
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-
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qcom,xmem-adv-to-oe-recovery-cycles:
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-
$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The number of cycles elapsed before an OE assertion, with
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respect to the cycle where ADV (address valid) is asserted.
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minimum: 0
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maximum: 3
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-
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qcom,xmem-read-hold-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The length in cycles of the first segment of a read transfer.
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For a single read transfer this will be the time from CS
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assertion to OE assertion.
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minimum: 0
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maximum: 15
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-
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required:
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- reg
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additionalProperties: false
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