tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: add hub->ctx_distance in setup_vmid_config
add hub->ctx_distance when read CONTEXT1_CNTL, align w/
write back operation.
v2: fix coding style errors reported by checkpatch.pl (Christian)
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Lang Yu <lang.yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Yifan Zhang
and committed by
Alex Deucher
061863e5
79df45dc
+18
-17
+1
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c
···
297
297
uint32_t tmp;
298
298
299
299
for (i = 0; i <= 14; i++) {
300
-
tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);
300
+
tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
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tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
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302
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
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303
adev->vm_manager.num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
···
260
260
block_size -= 9;
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for (i = 0; i <= 14; i++) {
263
-
tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
263
+
tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i * hub->ctx_distance);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
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num_level);
+2
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
+2
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
···
329
329
for_each_inst(j, xcc_mask) {
330
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hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
331
331
for (i = 0; i <= 14; i++) {
332
-
tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL, i);
332
+
tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,
333
+
i * hub->ctx_distance);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
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num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
···
287
287
uint32_t tmp;
288
288
289
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for (i = 0; i <= 14; i++) {
290
-
tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
290
+
tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
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tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
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adev->vm_manager.num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
···
296
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uint32_t tmp;
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for (i = 0; i <= 14; i++) {
299
-
tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
299
+
tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
300
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tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
302
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adev->vm_manager.num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
···
294
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uint32_t tmp;
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for (i = 0; i <= 14; i++) {
297
-
tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);
297
+
tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
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tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
300
300
adev->vm_manager.num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
···
299
299
uint32_t tmp;
300
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301
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for (i = 0; i <= 14; i++) {
302
-
tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);
302
+
tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
303
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tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
304
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tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
305
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adev->vm_manager.num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
···
242
242
block_size -= 9;
243
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for (i = 0; i <= 14; i++) {
245
-
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
245
+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i * hub->ctx_distance);
246
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
247
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
248
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num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
···
274
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block_size -= 9;
275
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for (i = 0; i <= 14; i++) {
277
-
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i);
277
+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i * hub->ctx_distance);
278
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
279
279
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
280
280
num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
···
344
344
hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
345
345
for (i = 0; i <= 14; i++) {
346
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tmp = RREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,
347
-
i);
347
+
i * hub->ctx_distance);
348
348
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
349
349
ENABLE_CONTEXT, 1);
350
350
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
···
367
367
uint32_t tmp;
368
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369
369
for (i = 0; i <= 14; i++) {
370
-
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
370
+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
371
371
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
372
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
373
373
adev->vm_manager.num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
···
285
285
uint32_t tmp;
286
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287
287
for (i = 0; i <= 14; i++) {
288
-
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
288
+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
289
289
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
290
290
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
291
291
adev->vm_manager.num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
···
323
323
uint32_t tmp;
324
324
325
325
for (i = 0; i <= 14; i++) {
326
-
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
326
+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
327
327
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
328
328
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
329
329
adev->vm_manager.num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
···
310
310
uint32_t tmp;
311
311
312
312
for (i = 0; i <= 14; i++) {
313
-
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
313
+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
314
314
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
315
315
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
316
316
adev->vm_manager.num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
···
315
315
uint32_t tmp;
316
316
317
317
for (i = 0; i <= 14; i++) {
318
-
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
318
+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
319
319
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
320
320
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
321
321
adev->vm_manager.num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c
···
303
303
uint32_t tmp;
304
304
305
305
for (i = 0; i <= 14; i++) {
306
-
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
306
+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
307
307
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
308
308
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
309
309
adev->vm_manager.num_level);
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
···
308
308
309
309
for (i = 0; i <= 14; i++) {
310
310
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
311
-
hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
311
+
hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i * hub->ctx_distance);
312
312
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
313
313
ENABLE_CONTEXT, 1);
314
314
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,