···22IP-Aliasing:33============4455-IP-aliases are additional IP-addresses/masks hooked up to a base 66-interface by adding a colon and a string when running ifconfig. 55+IP-aliases are an obsolete way to manage multiple IP-addresses/masks66+per interface. Newer tools such as iproute2 support multiple77+address/prefixes per interface, but aliases are still supported88+for backwards compatibility.99+1010+An alias is formed by adding a colon and a string when running ifconfig.711This string is usually numeric, but this is not a must.88-99-IP-Aliases are avail if CONFIG_INET (`standard' IPv4 networking) 1010-is configured in the kernel.1111-12121313o Alias creation.1414 Alias creation is done by 'magic' interface naming: eg. to create a···38383939 If the base device is shut down the added aliases will be deleted 4040 too.4141-4242-4343-Contact4444--------4545-Please finger or e-mail me:4646- Juan Jose Ciarlante <jjciarla@raiz.uncu.edu.ar>4747-4848-Updated by Erik Schoenfelder <schoenfr@gaertner.DE>4949-5050-; local variables:5151-; mode: indented-text5252-; mode: auto-fill5353-; end:
-2
MAINTAINERS
···28362836MAC8021128372837P: Johannes Berg28382838M: johannes@sipsolutions.net28392839-P: Michael Wu28402840-M: flamingice@sourmilk.net28412839L: linux-wireless@vger.kernel.org28422840W: http://linuxwireless.org/28432841T: git kernel.org:/pub/scm/linux/kernel/git/linville/wireless-2.6.git
+2-2
drivers/net/e1000/e1000_main.c
···31313232char e1000_driver_name[] = "e1000";3333static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";3434-#define DRV_VERSION "7.3.21-k2-NAPI"3434+#define DRV_VERSION "7.3.21-k3-NAPI"3535const char e1000_driver_version[] = DRV_VERSION;3636static const char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";3737···36973697 struct e1000_hw *hw = &adapter->hw;36983698 u32 rctl, icr = er32(ICR);3699369937003700- if (unlikely(!icr))37003700+ if (unlikely((!icr) || test_bit(__E1000_RESETTING, &adapter->flags)))37013701 return IRQ_NONE; /* Not our interrupt */3702370237033703 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
+2
drivers/net/gianfar_mii.c
···234234 if (NULL == new_bus)235235 return -ENOMEM;236236237237+ device_init_wakeup(&ofdev->dev, 1);238238+237239 new_bus->name = "Gianfar MII Bus",238240 new_bus->read = &gfar_mdio_read,239241 new_bus->write = &gfar_mdio_write,
···675675 rc = efx->phy_op->init(efx);676676 if (rc)677677 return rc;678678- efx->phy_op->reconfigure(efx);679679-680678 mutex_lock(&efx->mac_lock);679679+ efx->phy_op->reconfigure(efx);681680 rc = falcon_switch_mac(efx);682681 mutex_unlock(&efx->mac_lock);683682 if (rc)···684685 efx->mac_op->reconfigure(efx);685686686687 efx->port_initialized = true;687687- efx->stats_enabled = true;688688+ efx_stats_enable(efx);688689 return 0;689690690691fail:···733734 if (!efx->port_initialized)734735 return;735736737737+ efx_stats_disable(efx);736738 efx->phy_op->fini(efx);737739 efx->port_initialized = false;738740···13521352 return 0;13531353}1354135413551355+void efx_stats_disable(struct efx_nic *efx)13561356+{13571357+ spin_lock(&efx->stats_lock);13581358+ ++efx->stats_disable_count;13591359+ spin_unlock(&efx->stats_lock);13601360+}13611361+13621362+void efx_stats_enable(struct efx_nic *efx)13631363+{13641364+ spin_lock(&efx->stats_lock);13651365+ --efx->stats_disable_count;13661366+ spin_unlock(&efx->stats_lock);13671367+}13681368+13551369/* Context: process, dev_base_lock or RTNL held, non-blocking. */13561370static struct net_device_stats *efx_net_stats(struct net_device *net_dev)13571371{···13741360 struct net_device_stats *stats = &net_dev->stats;1375136113761362 /* Update stats if possible, but do not wait if another thread13771377- * is updating them (or resetting the NIC); slightly stale13781378- * stats are acceptable.13631363+ * is updating them or if MAC stats fetches are temporarily13641364+ * disabled; slightly stale stats are acceptable.13791365 */13801366 if (!spin_trylock(&efx->stats_lock))13811367 return stats;13821382- if (efx->stats_enabled) {13681368+ if (!efx->stats_disable_count) {13831369 efx->mac_op->update_stats(efx);13841370 falcon_update_nic_stats(efx);13851371 }···1627161316281614/* Tears down the entire software state and most of the hardware state16291615 * before reset. */16301630-void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd)16161616+void efx_reset_down(struct efx_nic *efx, enum reset_type method,16171617+ struct ethtool_cmd *ecmd)16311618{16321619 EFX_ASSERT_RESET_SERIALISED(efx);1633162016341634- /* The net_dev->get_stats handler is quite slow, and will fail16351635- * if a fetch is pending over reset. Serialise against it. */16361636- spin_lock(&efx->stats_lock);16371637- efx->stats_enabled = false;16381638- spin_unlock(&efx->stats_lock);16391639-16211621+ efx_stats_disable(efx);16401622 efx_stop_all(efx);16411623 mutex_lock(&efx->mac_lock);16421624 mutex_lock(&efx->spi_lock);···16401630 efx->phy_op->get_settings(efx, ecmd);1641163116421632 efx_fini_channels(efx);16331633+ if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)16341634+ efx->phy_op->fini(efx);16431635}1644163616451637/* This function will always ensure that the locks acquired in···16491637 * that we were unable to reinitialise the hardware, and the16501638 * driver should be disabled. If ok is false, then the rx and tx16511639 * engines are not restarted, pending a RESET_DISABLE. */16521652-int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd, bool ok)16401640+int efx_reset_up(struct efx_nic *efx, enum reset_type method,16411641+ struct ethtool_cmd *ecmd, bool ok)16531642{16541643 int rc;16551644···16601647 if (rc) {16611648 EFX_ERR(efx, "failed to initialise NIC\n");16621649 ok = false;16501650+ }16511651+16521652+ if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {16531653+ if (ok) {16541654+ rc = efx->phy_op->init(efx);16551655+ if (rc)16561656+ ok = false;16571657+ } else16581658+ efx->port_initialized = false;16631659 }1664166016651661 if (ok) {···1683166116841662 if (ok) {16851663 efx_start_all(efx);16861686- efx->stats_enabled = true;16641664+ efx_stats_enable(efx);16871665 }16881666 return rc;16891667}···1715169317161694 EFX_INFO(efx, "resetting (%d)\n", method);1717169517181718- efx_reset_down(efx, &ecmd);16961696+ efx_reset_down(efx, method, &ecmd);1719169717201698 rc = falcon_reset_hw(efx, method);17211699 if (rc) {···1734171217351713 /* Leave device stopped if necessary */17361714 if (method == RESET_TYPE_DISABLE) {17371737- efx_reset_up(efx, &ecmd, false);17151715+ efx_reset_up(efx, method, &ecmd, false);17381716 rc = -EIO;17391717 } else {17401740- rc = efx_reset_up(efx, &ecmd, true);17181718+ rc = efx_reset_up(efx, method, &ecmd, true);17411719 }1742172017431721out_disable:···18891867 efx->rx_checksum_enabled = true;18901868 spin_lock_init(&efx->netif_stop_lock);18911869 spin_lock_init(&efx->stats_lock);18701870+ efx->stats_disable_count = 1;18921871 mutex_init(&efx->mac_lock);18931872 efx->mac_op = &efx_dummy_mac_operations;18941873 efx->phy_op = &efx_dummy_phy_operations;
···219219 struct efx_nic *efx = netdev_priv(net_dev);220220 int rc;221221222222- if (EFX_WORKAROUND_13963(efx) && !ecmd->autoneg)223223- return -EINVAL;224224-225222 /* Falcon GMAC does not support 1000Mbps HD */226223 if (ecmd->speed == SPEED_1000 && ecmd->duplex != DUPLEX_FULL) {227224 EFX_LOG(efx, "rejecting unsupported 1000Mbps HD"
+18-14
drivers/net/sfc/falcon.c
···824824 rx_ev_pause_frm ? " [PAUSE]" : "");825825 }826826#endif827827-828828- if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&829829- efx->phy_type == PHY_TYPE_SFX7101))830830- tenxpress_crc_err(efx);831827}832828833829/* Handle receive events that are not in-order. */···1883188718841888 /* MAC stats will fail whilst the TX fifo is draining. Serialise18851889 * the drain sequence with the statistics fetch */18861886- spin_lock(&efx->stats_lock);18901890+ efx_stats_disable(efx);1887189118881892 falcon_read(efx, ®, MAC0_CTRL_REG_KER);18891893 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0, 1);···19131917 udelay(10);19141918 }1915191919161916- spin_unlock(&efx->stats_lock);19201920+ efx_stats_enable(efx);1917192119181922 /* If we've reset the EM block and the link is up, then19191923 * we'll have to kick the XAUI link so the PHY can recover */···22732277 struct efx_mac_operations *old_mac_op = efx->mac_op;22742278 efx_oword_t nic_stat;22752279 unsigned strap_val;22802280+ int rc = 0;22812281+22822282+ /* Don't try to fetch MAC stats while we're switching MACs */22832283+ efx_stats_disable(efx);2276228422772285 /* Internal loopbacks override the phy speed setting */22782286 if (efx->loopback_mode == LOOPBACK_GMAC) {···22872287 efx->link_fd = true;22882288 }2289228922902290+ WARN_ON(!mutex_is_locked(&efx->mac_lock));22902291 efx->mac_op = (EFX_IS10G(efx) ?22912292 &falcon_xmac_operations : &falcon_gmac_operations);22922292- if (old_mac_op == efx->mac_op)22932293- return 0;2294229322952295- WARN_ON(!mutex_is_locked(&efx->mac_lock));22962296-22972297- /* Not all macs support a mac-level link state */22982298- efx->mac_up = true;22992299-22942294+ /* Always push the NIC_STAT_REG setting even if the mac hasn't22952295+ * changed, because this function is run post online reset */23002296 falcon_read(efx, &nic_stat, NIC_STAT_REG);23012297 strap_val = EFX_IS10G(efx) ? 5 : 3;23022298 if (falcon_rev(efx) >= FALCON_REV_B0) {···23052309 BUG_ON(EFX_OWORD_FIELD(nic_stat, STRAP_PINS) != strap_val);23062310 }2307231123122312+ if (old_mac_op == efx->mac_op)23132313+ goto out;2308231423092315 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');23102310- return falcon_reset_macs(efx);23162316+ /* Not all macs support a mac-level link state */23172317+ efx->mac_up = true;23182318+23192319+ rc = falcon_reset_macs(efx);23202320+out:23212321+ efx_stats_enable(efx);23222322+ return rc;23112323}2312232423132325/* This call is responsible for hooking in the MAC and PHY operations */
+87-100
drivers/net/sfc/mdio_10g.c
···1515#include "net_driver.h"1616#include "mdio_10g.h"1717#include "boards.h"1818+#include "workarounds.h"18191920int mdio_clause45_reset_mmd(struct efx_nic *port, int mmd,2021 int spins, int spintime)···180179 return false;181180 else if (efx_phy_mode_disabled(efx->phy_mode))182181 return false;183183- else if (efx->loopback_mode == LOOPBACK_PHYXS) {182182+ else if (efx->loopback_mode == LOOPBACK_PHYXS)184183 mmd_mask &= ~(MDIO_MMDREG_DEVS_PHYXS |185184 MDIO_MMDREG_DEVS_PCS |186185 MDIO_MMDREG_DEVS_PMAPMD |187186 MDIO_MMDREG_DEVS_AN);188188- if (!mmd_mask) {189189- reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,190190- MDIO_PHYXS_STATUS2);191191- return !(reg & (1 << MDIO_PHYXS_STATUS2_RX_FAULT_LBN));192192- }193193- } else if (efx->loopback_mode == LOOPBACK_PCS)187187+ else if (efx->loopback_mode == LOOPBACK_PCS)194188 mmd_mask &= ~(MDIO_MMDREG_DEVS_PCS |195189 MDIO_MMDREG_DEVS_PMAPMD |196190 MDIO_MMDREG_DEVS_AN);197191 else if (efx->loopback_mode == LOOPBACK_PMAPMD)198192 mmd_mask &= ~(MDIO_MMDREG_DEVS_PMAPMD |199193 MDIO_MMDREG_DEVS_AN);194194+195195+ if (!mmd_mask) {196196+ /* Use presence of XGMII faults in leui of link state */197197+ reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,198198+ MDIO_PHYXS_STATUS2);199199+ return !(reg & (1 << MDIO_PHYXS_STATUS2_RX_FAULT_LBN));200200+ }200201201202 while (mmd_mask) {202203 if (mmd_mask & 1) {···266263 }267264}268265269269-static u32 mdio_clause45_get_an(struct efx_nic *efx, u16 addr, u32 xnp)266266+static u32 mdio_clause45_get_an(struct efx_nic *efx, u16 addr)270267{271268 int phy_id = efx->mii.phy_id;272269 u32 result = 0;···281278 result |= ADVERTISED_100baseT_Half;282279 if (reg & ADVERTISE_100FULL)283280 result |= ADVERTISED_100baseT_Full;284284- if (reg & LPA_RESV)285285- result |= xnp;286286-287281 return result;288282}289283···310310 */311311void mdio_clause45_get_settings_ext(struct efx_nic *efx,312312 struct ethtool_cmd *ecmd,313313- u32 xnp, u32 xnp_lpa)313313+ u32 npage_adv, u32 npage_lpa)314314{315315 int phy_id = efx->mii.phy_id;316316 int reg;···361361 ecmd->autoneg = AUTONEG_ENABLE;362362 ecmd->advertising |=363363 ADVERTISED_Autoneg |364364- mdio_clause45_get_an(efx,365365- MDIO_AN_ADVERTISE, xnp);364364+ mdio_clause45_get_an(efx, MDIO_AN_ADVERTISE) |365365+ npage_adv;366366 } else367367 ecmd->autoneg = AUTONEG_DISABLE;368368 } else···371371 if (ecmd->autoneg) {372372 /* If AN is complete, report best common mode,373373 * otherwise report best advertised mode. */374374- u32 common = ecmd->advertising;374374+ u32 modes = 0;375375 if (mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,376376 MDIO_MMDREG_STAT1) &377377- (1 << MDIO_AN_STATUS_AN_DONE_LBN)) {378378- common &= mdio_clause45_get_an(efx, MDIO_AN_LPA,379379- xnp_lpa);380380- }381381- if (common & ADVERTISED_10000baseT_Full) {377377+ (1 << MDIO_AN_STATUS_AN_DONE_LBN))378378+ modes = (ecmd->advertising &379379+ (mdio_clause45_get_an(efx, MDIO_AN_LPA) |380380+ npage_lpa));381381+ if (modes == 0)382382+ modes = ecmd->advertising;383383+384384+ if (modes & ADVERTISED_10000baseT_Full) {382385 ecmd->speed = SPEED_10000;383386 ecmd->duplex = DUPLEX_FULL;384384- } else if (common & (ADVERTISED_1000baseT_Full |385385- ADVERTISED_1000baseT_Half)) {387387+ } else if (modes & (ADVERTISED_1000baseT_Full |388388+ ADVERTISED_1000baseT_Half)) {386389 ecmd->speed = SPEED_1000;387387- ecmd->duplex = !!(common & ADVERTISED_1000baseT_Full);388388- } else if (common & (ADVERTISED_100baseT_Full |389389- ADVERTISED_100baseT_Half)) {390390+ ecmd->duplex = !!(modes & ADVERTISED_1000baseT_Full);391391+ } else if (modes & (ADVERTISED_100baseT_Full |392392+ ADVERTISED_100baseT_Half)) {390393 ecmd->speed = SPEED_100;391391- ecmd->duplex = !!(common & ADVERTISED_100baseT_Full);394394+ ecmd->duplex = !!(modes & ADVERTISED_100baseT_Full);392395 } else {393396 ecmd->speed = SPEED_10;394394- ecmd->duplex = !!(common & ADVERTISED_10baseT_Full);397397+ ecmd->duplex = !!(modes & ADVERTISED_10baseT_Full);395398 }396399 } else {397400 /* Report forced settings */···418415 int phy_id = efx->mii.phy_id;419416 struct ethtool_cmd prev;420417 u32 required;421421- int ctrl1_bits, reg;418418+ int reg;422419423420 efx->phy_op->get_settings(efx, &prev);424421···433430 if (prev.port != PORT_TP || ecmd->port != PORT_TP)434431 return -EINVAL;435432436436- /* Check that PHY supports these settings and work out the437437- * basic control bits */438438- if (ecmd->duplex) {433433+ /* Check that PHY supports these settings */434434+ if (ecmd->autoneg) {435435+ required = SUPPORTED_Autoneg;436436+ } else if (ecmd->duplex) {439437 switch (ecmd->speed) {440440- case SPEED_10:441441- ctrl1_bits = BMCR_FULLDPLX;442442- required = SUPPORTED_10baseT_Full;443443- break;444444- case SPEED_100:445445- ctrl1_bits = BMCR_SPEED100 | BMCR_FULLDPLX;446446- required = SUPPORTED_100baseT_Full;447447- break;448448- case SPEED_1000:449449- ctrl1_bits = BMCR_SPEED1000 | BMCR_FULLDPLX;450450- required = SUPPORTED_1000baseT_Full;451451- break;452452- case SPEED_10000:453453- ctrl1_bits = (BMCR_SPEED1000 | BMCR_SPEED100 |454454- BMCR_FULLDPLX);455455- required = SUPPORTED_10000baseT_Full;456456- break;457457- default:458458- return -EINVAL;438438+ case SPEED_10: required = SUPPORTED_10baseT_Full; break;439439+ case SPEED_100: required = SUPPORTED_100baseT_Full; break;440440+ default: return -EINVAL;459441 }460442 } else {461443 switch (ecmd->speed) {462462- case SPEED_10:463463- ctrl1_bits = 0;464464- required = SUPPORTED_10baseT_Half;465465- break;466466- case SPEED_100:467467- ctrl1_bits = BMCR_SPEED100;468468- required = SUPPORTED_100baseT_Half;469469- break;470470- case SPEED_1000:471471- ctrl1_bits = BMCR_SPEED1000;472472- required = SUPPORTED_1000baseT_Half;473473- break;474474- default:475475- return -EINVAL;444444+ case SPEED_10: required = SUPPORTED_10baseT_Half; break;445445+ case SPEED_100: required = SUPPORTED_100baseT_Half; break;446446+ default: return -EINVAL;476447 }477448 }478478- if (ecmd->autoneg)479479- required |= SUPPORTED_Autoneg;480449 required |= ecmd->advertising;481450 if (required & ~prev.supported)482451 return -EINVAL;483452484484- /* Set the basic control bits */485485- reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,486486- MDIO_MMDREG_CTRL1);487487- reg &= ~(BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FULLDPLX | 0x003c);488488- reg |= ctrl1_bits;489489- mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, MDIO_MMDREG_CTRL1,490490- reg);453453+ if (ecmd->autoneg) {454454+ bool xnp = (ecmd->advertising & ADVERTISED_10000baseT_Full455455+ || EFX_WORKAROUND_13204(efx));491456492492- /* Set the AN registers */493493- if (ecmd->autoneg != prev.autoneg ||494494- ecmd->advertising != prev.advertising) {495495- bool xnp = false;457457+ /* Set up the base page */458458+ reg = ADVERTISE_CSMA;459459+ if (ecmd->advertising & ADVERTISED_10baseT_Half)460460+ reg |= ADVERTISE_10HALF;461461+ if (ecmd->advertising & ADVERTISED_10baseT_Full)462462+ reg |= ADVERTISE_10FULL;463463+ if (ecmd->advertising & ADVERTISED_100baseT_Half)464464+ reg |= ADVERTISE_100HALF;465465+ if (ecmd->advertising & ADVERTISED_100baseT_Full)466466+ reg |= ADVERTISE_100FULL;467467+ if (xnp)468468+ reg |= ADVERTISE_RESV;469469+ else if (ecmd->advertising & (ADVERTISED_1000baseT_Half |470470+ ADVERTISED_1000baseT_Full))471471+ reg |= ADVERTISE_NPAGE;472472+ reg |= efx_fc_advertise(efx->wanted_fc);473473+ mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,474474+ MDIO_AN_ADVERTISE, reg);496475497497- if (efx->phy_op->set_xnp_advertise)498498- xnp = efx->phy_op->set_xnp_advertise(efx,499499- ecmd->advertising);476476+ /* Set up the (extended) next page if necessary */477477+ if (efx->phy_op->set_npage_adv)478478+ efx->phy_op->set_npage_adv(efx, ecmd->advertising);500479501501- if (ecmd->autoneg) {502502- reg = 0;503503- if (ecmd->advertising & ADVERTISED_10baseT_Half)504504- reg |= ADVERTISE_10HALF;505505- if (ecmd->advertising & ADVERTISED_10baseT_Full)506506- reg |= ADVERTISE_10FULL;507507- if (ecmd->advertising & ADVERTISED_100baseT_Half)508508- reg |= ADVERTISE_100HALF;509509- if (ecmd->advertising & ADVERTISED_100baseT_Full)510510- reg |= ADVERTISE_100FULL;511511- if (xnp)512512- reg |= ADVERTISE_RESV;513513- mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,514514- MDIO_AN_ADVERTISE, reg);515515- }516516-480480+ /* Enable and restart AN */517481 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,518482 MDIO_MMDREG_CTRL1);519519- if (ecmd->autoneg)520520- reg |= BMCR_ANENABLE | BMCR_ANRESTART;521521- else522522- reg &= ~BMCR_ANENABLE;483483+ reg |= BMCR_ANENABLE;484484+ if (!(EFX_WORKAROUND_15195(efx) &&485485+ LOOPBACK_MASK(efx) & efx->phy_op->loopbacks))486486+ reg |= BMCR_ANRESTART;523487 if (xnp)524488 reg |= 1 << MDIO_AN_CTRL_XNP_LBN;525489 else526490 reg &= ~(1 << MDIO_AN_CTRL_XNP_LBN);527491 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,492492+ MDIO_MMDREG_CTRL1, reg);493493+ } else {494494+ /* Disable AN */495495+ mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_AN,496496+ MDIO_MMDREG_CTRL1,497497+ __ffs(BMCR_ANENABLE), false);498498+499499+ /* Set the basic control bits */500500+ reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,501501+ MDIO_MMDREG_CTRL1);502502+ reg &= ~(BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FULLDPLX |503503+ 0x003c);504504+ if (ecmd->speed == SPEED_100)505505+ reg |= BMCR_SPEED100;506506+ if (ecmd->duplex)507507+ reg |= BMCR_FULLDPLX;508508+ mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,528509 MDIO_MMDREG_CTRL1, reg);529510 }530511
···954954 do {955955 udelay(1);956956 val = smsc911x_reg_read(pdata, RX_DP_CTRL);957957- } while (timeout-- && (val & RX_DP_CTRL_RX_FFWD_));957957+ } while (--timeout && (val & RX_DP_CTRL_RX_FFWD_));958958959959 if (unlikely(timeout == 0))960960 SMSC_WARNING(HW, "Timed out waiting for "
+1-2
drivers/net/smsc9420.c
···1378137813791379 /* test the IRQ connection to the ISR */13801380 smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq);13811381+ pd->software_irq_signal = false;1381138213821383 spin_lock_irqsave(&pd->int_lock, flags);13831384 /* configure interrupt deassertion timer and enable interrupts */···13941393 smsc9420_pci_flush_write(pd);1395139413961395 timeout = 1000;13971397- pd->software_irq_signal = false;13981398- smp_wmb();13991396 while (timeout--) {14001397 if (pd->software_irq_signal)14011398 break;
+19-4
drivers/net/tulip/21142.c
···991010 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}1111 for more information on this driver.1212+1313+ DC21143 manual "21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller1414+ Hardware Reference Manual" is currently available at :1515+ http://developer.intel.com/design/network/manuals/278074.htm1616+1217 Please submit bugs to http://bugzilla.kernel.org/ .1318*/1419···3732 int csr12 = ioread32(ioaddr + CSR12);3833 int next_tick = 60*HZ;3934 int new_csr6 = 0;3535+ int csr14 = ioread32(ioaddr + CSR14);40363737+ /* CSR12[LS10,LS100] are not reliable during autonegotiation */3838+ if ((csr14 & 0x80) && (csr12 & 0x7000) != 0x5000)3939+ csr12 |= 6;4140 if (tulip_debug > 2)4241 printk(KERN_INFO"%s: 21143 negotiation status %8.8x, %s.\n",4342 dev->name, csr12, medianame[dev->if_port]);···8576 new_csr6 = 0x83860000;8677 dev->if_port = 3;8778 iowrite32(0, ioaddr + CSR13);8888- iowrite32(0x0003FF7F, ioaddr + CSR14);7979+ iowrite32(0x0003FFFF, ioaddr + CSR14);8980 iowrite16(8, ioaddr + CSR15);9081 iowrite32(1, ioaddr + CSR13);9182 }···141132 struct tulip_private *tp = netdev_priv(dev);142133 void __iomem *ioaddr = tp->base_addr;143134 int csr12 = ioread32(ioaddr + CSR12);135135+ int csr14 = ioread32(ioaddr + CSR14);144136137137+ /* CSR12[LS10,LS100] are not reliable during autonegotiation */138138+ if ((csr14 & 0x80) && (csr12 & 0x7000) != 0x5000)139139+ csr12 |= 6;145140 if (tulip_debug > 1)146141 printk(KERN_INFO"%s: 21143 link status interrupt %8.8x, CSR5 %x, "147147- "%8.8x.\n", dev->name, csr12, csr5, ioread32(ioaddr + CSR14));142142+ "%8.8x.\n", dev->name, csr12, csr5, csr14);148143149144 /* If NWay finished and we have a negotiated partner capability. */150145 if (tp->nway && !tp->nwayset && (csr12 & 0x7000) == 0x5000) {···156143 int negotiated = tp->sym_advertise & (csr12 >> 16);157144 tp->lpar = csr12 >> 16;158145 tp->nwayset = 1;159159- if (negotiated & 0x0100) dev->if_port = 5;146146+ /* If partner cannot negotiate, it is 10Mbps Half Duplex */147147+ if (!(csr12 & 0x8000)) dev->if_port = 0;148148+ else if (negotiated & 0x0100) dev->if_port = 5;160149 else if (negotiated & 0x0080) dev->if_port = 3;161150 else if (negotiated & 0x0040) dev->if_port = 4;162151 else if (negotiated & 0x0020) dev->if_port = 0;···229214 tp->timer.expires = RUN_AT(3*HZ);230215 add_timer(&tp->timer);231216 } else if (dev->if_port == 5)232232- iowrite32(ioread32(ioaddr + CSR14) & ~0x080, ioaddr + CSR14);217217+ iowrite32(csr14 & ~0x080, ioaddr + CSR14);233218 } else if (dev->if_port == 0 || dev->if_port == 4) {234219 if ((csr12 & 4) == 0)235220 printk(KERN_INFO"%s: 21143 10baseT link beat good.\n",
···10281028 * it's done by reseting the chip. To accomplish this we must10291029 * first cleanup any pending DMA, then restart stuff after a la10301030 * ath5k_init.10311031+ *10321032+ * Called with sc->lock.10311033 */10321034static int10331035ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)···28162814{28172815 struct ath5k_softc *sc = hw->priv;28182816 struct ieee80211_conf *conf = &hw->conf;28172817+ int ret;28182818+28192819+ mutex_lock(&sc->lock);2819282028202821 sc->bintval = conf->beacon_int;28212822 sc->power_level = conf->power_level;2822282328232823- return ath5k_chan_set(sc, conf->channel);28242824+ ret = ath5k_chan_set(sc, conf->channel);28252825+28262826+ mutex_unlock(&sc->lock);28272827+ return ret;28242828}2825282928262830static int
+4
drivers/net/wireless/iwlwifi/iwl-agn.c
···17191719 priv->ucode_data_backup.len = data_size;17201720 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);1721172117221722+ if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||17231723+ !priv->ucode_data_backup.v_addr)17241724+ goto err_pci_alloc;17251725+17221726 /* Initialization instructions and data */17231727 if (init_size && init_data_size) {17241728 priv->ucode_init.len = init_size;
···538538 * cannot be fixed without breaking all existing apps.539539 */540540 case TUNSETIFF:541541+ case TUNGETIFF:541542 case SIOCGIFFLAGS:542543 case SIOCGIFMETRIC:543544 case SIOCGIFMTU:···19831982COMPATIBLE_IOCTL(TUNSETDEBUG)19841983COMPATIBLE_IOCTL(TUNSETPERSIST)19851984COMPATIBLE_IOCTL(TUNSETOWNER)19851985+COMPATIBLE_IOCTL(TUNSETLINK)19861986+COMPATIBLE_IOCTL(TUNSETGROUP)19871987+COMPATIBLE_IOCTL(TUNGETFEATURES)19881988+COMPATIBLE_IOCTL(TUNSETOFFLOAD)19891989+COMPATIBLE_IOCTL(TUNSETTXFILTER)19861990/* Big V */19871991COMPATIBLE_IOCTL(VT_SETMODE)19881992COMPATIBLE_IOCTL(VT_GETMODE)···25792573HANDLE_IOCTL(SIOCGIFTXQLEN, dev_ifsioc)25802574HANDLE_IOCTL(SIOCSIFTXQLEN, dev_ifsioc)25812575HANDLE_IOCTL(TUNSETIFF, dev_ifsioc)25762576+HANDLE_IOCTL(TUNGETIFF, dev_ifsioc)25822577HANDLE_IOCTL(SIOCETHTOOL, ethtool_ioctl)25832578HANDLE_IOCTL(SIOCBONDENSLAVE, bond_ioctl)25842579HANDLE_IOCTL(SIOCBONDRELEASE, bond_ioctl)
+1-1
include/net/inet_hashtables.h
···183183 size = 2048;184184 if (nr_pcpus >= 32)185185 size = 4096;186186- if (sizeof(rwlock_t) != 0) {186186+ if (sizeof(spinlock_t) != 0) {187187#ifdef CONFIG_NUMA188188 if (size * sizeof(spinlock_t) > PAGE_SIZE)189189 hashinfo->ehash_locks = vmalloc(size * sizeof(spinlock_t));
···498498 * calculate the number of reg rules we will need. We will need one499499 * for each channel subband */500500 while (country_ie_len >= 3) {501501+ int end_channel = 0;501502 struct ieee80211_country_ie_triplet *triplet =502503 (struct ieee80211_country_ie_triplet *) country_ie;503504 int cur_sub_max_channel = 0, cur_channel = 0;···510509 continue;511510 }512511512512+ /* 2 GHz */513513+ if (triplet->chans.first_channel <= 14)514514+ end_channel = triplet->chans.first_channel +515515+ triplet->chans.num_channels;516516+ else517517+ /*518518+ * 5 GHz -- For example in country IEs if the first519519+ * channel given is 36 and the number of channels is 4520520+ * then the individual channel numbers defined for the521521+ * 5 GHz PHY by these parameters are: 36, 40, 44, and 48522522+ * and not 36, 37, 38, 39.523523+ *524524+ * See: http://tinyurl.com/11d-clarification525525+ */526526+ end_channel = triplet->chans.first_channel +527527+ (4 * (triplet->chans.num_channels - 1));528528+513529 cur_channel = triplet->chans.first_channel;514514- cur_sub_max_channel = ieee80211_channel_to_frequency(515515- cur_channel + triplet->chans.num_channels);530530+ cur_sub_max_channel = end_channel;516531517532 /* Basic sanity check */518533 if (cur_sub_max_channel < cur_channel)···607590 end_channel = triplet->chans.first_channel +608591 triplet->chans.num_channels;609592 else610610- /*611611- * 5 GHz -- For example in country IEs if the first612612- * channel given is 36 and the number of channels is 4613613- * then the individual channel numbers defined for the614614- * 5 GHz PHY by these parameters are: 36, 40, 44, and 48615615- * and not 36, 37, 38, 39.616616- *617617- * See: http://tinyurl.com/11d-clarification618618- */619593 end_channel = triplet->chans.first_channel +620594 (4 * (triplet->chans.num_channels - 1));621595···12841276 if (intersected_rd) {12851277 printk(KERN_DEBUG "cfg80211: We intersect both of these "12861278 "and get:\n");12871287- print_regdomain_info(rd);12791279+ print_regdomain_info(intersected_rd);12881280 return;12891281 }12901282 printk(KERN_DEBUG "cfg80211: Intersection between both failed\n");