drm/etnaviv: update hardware headers from rnndb

+223 -58

drivers/gpu/drm/etnaviv/common.xml.h

··· 8 8 git clone git://0x04.net/rules-ng-ng 9 9 10 10 The rules-ng-ng source files this header was generated from are: 11 - - state.xml ( 19930 bytes, from 2017-03-09 15:43:43) 12 - - common.xml ( 23473 bytes, from 2017-03-09 15:43:43) 13 - - state_hi.xml ( 26403 bytes, from 2017-03-09 15:43:43) 14 - - copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) 15 - - state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56) 16 - - state_3d.xml ( 66957 bytes, from 2017-03-09 15:43:43) 17 - - state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56) 11 + - texdesc_3d.xml ( 3183 bytes, from 2017-12-18 16:51:59) 12 + - copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) 13 + - common.xml ( 35468 bytes, from 2018-01-22 13:48:54) 14 + - common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) 18 15 19 - Copyright (C) 2012-2017 by the following authors: 16 + Copyright (C) 2012-2018 by the following authors: 20 17 - Wladimir J. van der Laan <laanwj@gmail.com> 21 18 - Christian Gmeiner <christian.gmeiner@gmail.com> 22 19 - Lucas Stach <l.stach@pengutronix.de> ··· 46 49 #define SYNC_RECIPIENT_RA 0x00000005 47 50 #define SYNC_RECIPIENT_PE 0x00000007 48 51 #define SYNC_RECIPIENT_DE 0x0000000b 49 - #define SYNC_RECIPIENT_VG 0x0000000f 50 - #define SYNC_RECIPIENT_TESSELATOR 0x00000010 51 - #define SYNC_RECIPIENT_VG2 0x00000011 52 - #define SYNC_RECIPIENT_TESSELATOR2 0x00000012 53 - #define SYNC_RECIPIENT_VG3 0x00000013 54 - #define SYNC_RECIPIENT_TESSELATOR3 0x00000014 52 + #define SYNC_RECIPIENT_BLT 0x00000010 55 53 #define ENDIAN_MODE_NO_SWAP 0x00000000 56 54 #define ENDIAN_MODE_SWAP_16 0x00000001 57 55 #define ENDIAN_MODE_SWAP_32 0x00000002 ··· 69 77 #define chipModel_GC800 0x00000800 70 78 #define chipModel_GC860 0x00000860 71 79 #define chipModel_GC880 0x00000880 80 + #define chipModel_GC900 0x00000900 72 81 #define chipModel_GC1000 0x00001000 73 82 #define chipModel_GC1500 0x00001500 74 83 #define chipModel_GC2000 0x00002000 ··· 81 88 #define chipModel_GC5000 0x00005000 82 89 #define chipModel_GC5200 0x00005200 83 90 #define chipModel_GC6400 0x00006400 91 + #define chipModel_GC7000 0x00007000 92 + #define chipModel_GC7400 0x00007400 93 + #define chipModel_GC8000 0x00008000 94 + #define chipModel_GC8100 0x00008100 95 + #define chipModel_GC8200 0x00008200 96 + #define chipModel_GC8400 0x00008400 84 97 #define RGBA_BITS_R 0x00000001 85 98 #define RGBA_BITS_G 0x00000002 86 99 #define RGBA_BITS_B 0x00000004 ··· 202 203 #define chipMinorFeatures2_RGB888 0x00001000 203 204 #define chipMinorFeatures2_TX__YUV_ASSEMBLER 0x00002000 204 205 #define chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING 0x00004000 205 - #define chipMinorFeatures2_EXTRA_TEXTURE_STATE 0x00008000 206 + #define chipMinorFeatures2_TX_FILTER 0x00008000 206 207 #define chipMinorFeatures2_FULL_DIRECTFB 0x00010000 207 208 #define chipMinorFeatures2_2D_TILING 0x00020000 208 209 #define chipMinorFeatures2_THREAD_WALKER_IN_PS 0x00040000 ··· 241 242 #define chipMinorFeatures3_TX_ENHANCEMENTS1 0x00080000 242 243 #define chipMinorFeatures3_SH_ENHANCEMENTS1 0x00100000 243 244 #define chipMinorFeatures3_SH_ENHANCEMENTS2 0x00200000 244 - #define chipMinorFeatures3_UNK22 0x00400000 245 + #define chipMinorFeatures3_PE_ENHANCEMENTS1 0x00400000 245 246 #define chipMinorFeatures3_2D_FC_SOURCE 0x00800000 246 - #define chipMinorFeatures3_UNK24 0x01000000 247 - #define chipMinorFeatures3_UNK25 0x02000000 247 + #define chipMinorFeatures3_BUG_FIXES_14 0x01000000 248 + #define chipMinorFeatures3_POWER_OPTIMIZATIONS_0 0x02000000 248 249 #define chipMinorFeatures3_NEW_HZ 0x04000000 249 - #define chipMinorFeatures3_UNK27 0x08000000 250 - #define chipMinorFeatures3_UNK28 0x10000000 250 + #define chipMinorFeatures3_PE_DITHER_FIX 0x08000000 251 + #define chipMinorFeatures3_DE_ENHANCEMENTS3 0x10000000 251 252 #define chipMinorFeatures3_SH_ENHANCEMENTS3 0x20000000 252 - #define chipMinorFeatures3_UNK30 0x40000000 253 - #define chipMinorFeatures3_UNK31 0x80000000 254 - #define chipMinorFeatures4_UNK0 0x00000001 253 + #define chipMinorFeatures3_SH_ENHANCEMENTS4 0x40000000 254 + #define chipMinorFeatures3_TX_ENHANCEMENTS2 0x80000000 255 + #define chipMinorFeatures4_FE_ENHANCEMENTS1 0x00000001 255 256 #define chipMinorFeatures4_PE_ENHANCEMENTS2 0x00000002 256 257 #define chipMinorFeatures4_FRUSTUM_CLIP_FIX 0x00000004 257 - #define chipMinorFeatures4_UNK3 0x00000008 258 - #define chipMinorFeatures4_UNK4 0x00000010 258 + #define chipMinorFeatures4_DE_NO_GAMMA 0x00000008 259 + #define chipMinorFeatures4_PA_ENHANCEMENTS_2 0x00000010 259 260 #define chipMinorFeatures4_2D_GAMMA 0x00000020 260 261 #define chipMinorFeatures4_SINGLE_BUFFER 0x00000040 261 - #define chipMinorFeatures4_UNK7 0x00000080 262 - #define chipMinorFeatures4_UNK8 0x00000100 263 - #define chipMinorFeatures4_UNK9 0x00000200 264 - #define chipMinorFeatures4_UNK10 0x00000400 262 + #define chipMinorFeatures4_HI_ENHANCEMENTS_1 0x00000080 263 + #define chipMinorFeatures4_TX_ENHANCEMENTS_3 0x00000100 264 + #define chipMinorFeatures4_SH_ENHANCEMENTS_5 0x00000200 265 + #define chipMinorFeatures4_FE_ENHANCEMENTS_2 0x00000400 265 266 #define chipMinorFeatures4_TX_LERP_PRECISION_FIX 0x00000800 266 267 #define chipMinorFeatures4_2D_COLOR_SPACE_CONVERSION 0x00001000 267 268 #define chipMinorFeatures4_TEXTURE_ASTC 0x00002000 268 - #define chipMinorFeatures4_UNK14 0x00004000 269 - #define chipMinorFeatures4_UNK15 0x00008000 269 + #define chipMinorFeatures4_PE_ENHANCEMENTS_4 0x00004000 270 + #define chipMinorFeatures4_MC_ENHANCEMENTS_1 0x00008000 270 271 #define chipMinorFeatures4_HALTI2 0x00010000 271 - #define chipMinorFeatures4_UNK17 0x00020000 272 + #define chipMinorFeatures4_2D_MIRROR_EXTENSION 0x00020000 272 273 #define chipMinorFeatures4_SMALL_MSAA 0x00040000 273 - #define chipMinorFeatures4_UNK19 0x00080000 274 + #define chipMinorFeatures4_BUG_FIXES_17 0x00080000 274 275 #define chipMinorFeatures4_NEW_RA 0x00100000 275 276 #define chipMinorFeatures4_2D_OPF_YUV_OUTPUT 0x00200000 276 277 #define chipMinorFeatures4_2D_MULTI_SOURCE_BLT_EX2 0x00400000 ··· 279 280 #define chipMinorFeatures4_BUG_FIXES18 0x02000000 280 281 #define chipMinorFeatures4_2D_COMPRESSION 0x04000000 281 282 #define chipMinorFeatures4_PROBE 0x08000000 282 - #define chipMinorFeatures4_UNK28 0x10000000 283 + #define chipMinorFeatures4_MEDIUM_PRECISION 0x10000000 283 284 #define chipMinorFeatures4_2D_SUPER_TILE_VERSION 0x20000000 284 - #define chipMinorFeatures4_UNK30 0x40000000 285 - #define chipMinorFeatures4_UNK31 0x80000000 286 - #define chipMinorFeatures5_UNK0 0x00000001 287 - #define chipMinorFeatures5_UNK1 0x00000002 288 - #define chipMinorFeatures5_UNK2 0x00000004 289 - #define chipMinorFeatures5_UNK3 0x00000008 285 + #define chipMinorFeatures4_BUG_FIXES19 0x40000000 286 + #define chipMinorFeatures4_SH_ENHANCEMENTS6 0x80000000 287 + #define chipMinorFeatures5_SH_ENHANCEMENTS7 0x00000001 288 + #define chipMinorFeatures5_BUG_FIXES20 0x00000002 289 + #define chipMinorFeatures5_DE_ADDRESS_40 0x00000004 290 + #define chipMinorFeatures5_MINI_MMU_FIX 0x00000008 290 291 #define chipMinorFeatures5_EEZ 0x00000010 291 - #define chipMinorFeatures5_UNK5 0x00000020 292 - #define chipMinorFeatures5_UNK6 0x00000040 293 - #define chipMinorFeatures5_UNK7 0x00000080 294 - #define chipMinorFeatures5_UNK8 0x00000100 292 + #define chipMinorFeatures5_BUG_FIXES21 0x00000020 293 + #define chipMinorFeatures5_EXTRA_VG_CAPS 0x00000040 294 + #define chipMinorFeatures5_MULTI_SRC_V15 0x00000080 295 + #define chipMinorFeatures5_BUG_FIXES22 0x00000100 295 296 #define chipMinorFeatures5_HALTI3 0x00000200 296 - #define chipMinorFeatures5_UNK10 0x00000400 297 + #define chipMinorFeatures5_TESSELATION_SHADERS 0x00000400 297 298 #define chipMinorFeatures5_2D_ONE_PASS_FILTER_TAP 0x00000800 298 - #define chipMinorFeatures5_UNK12 0x00001000 299 + #define chipMinorFeatures5_MULTI_SRC_V2_STR_QUAD 0x00001000 299 300 #define chipMinorFeatures5_SEPARATE_SRC_DST 0x00002000 300 301 #define chipMinorFeatures5_HALTI4 0x00004000 301 - #define chipMinorFeatures5_UNK15 0x00008000 302 + #define chipMinorFeatures5_RA_WRITE_DEPTH 0x00008000 302 303 #define chipMinorFeatures5_ANDROID_ONLY 0x00010000 303 304 #define chipMinorFeatures5_HAS_PRODUCTID 0x00020000 304 - #define chipMinorFeatures5_UNK18 0x00040000 305 - #define chipMinorFeatures5_UNK19 0x00080000 305 + #define chipMinorFeatures5_TX_SUPPORT_DEC 0x00040000 306 + #define chipMinorFeatures5_S8_MSAA_COMPRESSION 0x00080000 306 307 #define chipMinorFeatures5_PE_DITHER_FIX2 0x00100000 307 - #define chipMinorFeatures5_UNK21 0x00200000 308 - #define chipMinorFeatures5_UNK22 0x00400000 309 - #define chipMinorFeatures5_UNK23 0x00800000 310 - #define chipMinorFeatures5_UNK24 0x01000000 311 - #define chipMinorFeatures5_UNK25 0x02000000 312 - #define chipMinorFeatures5_UNK26 0x04000000 308 + #define chipMinorFeatures5_L2_CACHE_REMOVE 0x00200000 309 + #define chipMinorFeatures5_FE_ALLOW_RND_VTX_CNT 0x00400000 310 + #define chipMinorFeatures5_CUBE_MAP_FL28 0x00800000 311 + #define chipMinorFeatures5_TX_6BIT_FRAC 0x01000000 312 + #define chipMinorFeatures5_FE_ALLOW_STALL_PREFETCH_ENG 0x02000000 313 + #define chipMinorFeatures5_THIRD_PARTY_COMPRESSION 0x04000000 313 314 #define chipMinorFeatures5_RS_DEPTHSTENCIL_NATIVE_SUPPORT 0x08000000 314 315 #define chipMinorFeatures5_V2_MSAA_COMP_FIX 0x10000000 315 - #define chipMinorFeatures5_UNK29 0x20000000 316 - #define chipMinorFeatures5_UNK30 0x40000000 317 - #define chipMinorFeatures5_UNK31 0x80000000 316 + #define chipMinorFeatures5_HALTI5 0x20000000 317 + #define chipMinorFeatures5_EVIS 0x40000000 318 + #define chipMinorFeatures5_BLT_ENGINE 0x80000000 319 + #define chipMinorFeatures6_BUG_FIXES_23 0x00000001 320 + #define chipMinorFeatures6_BUG_FIXES_24 0x00000002 321 + #define chipMinorFeatures6_DEC 0x00000004 322 + #define chipMinorFeatures6_VS_TILE_NV12 0x00000008 323 + #define chipMinorFeatures6_VS_TILE_NV12_10BIT 0x00000010 324 + #define chipMinorFeatures6_RENDER_TARGET_8 0x00000020 325 + #define chipMinorFeatures6_TEX_LOD_FLOW_CORR 0x00000040 326 + #define chipMinorFeatures6_FACE_LOD 0x00000080 327 + #define chipMinorFeatures6_MULTI_CORE_SEMAPHORE_STALL_V2 0x00000100 328 + #define chipMinorFeatures6_VMSAA 0x00000200 329 + #define chipMinorFeatures6_CHIP_ENABLE_LINK 0x00000400 330 + #define chipMinorFeatures6_MULTI_SRC_BLT_1_5_ENHANCEMENT 0x00000800 331 + #define chipMinorFeatures6_MULTI_SRC_BLT_BILINEAR_FILTER 0x00001000 332 + #define chipMinorFeatures6_RA_HZEZ_CLOCK_CONTROL 0x00002000 333 + #define chipMinorFeatures6_CACHE128B256BPERLINE 0x00004000 334 + #define chipMinorFeatures6_V4_COMPRESSION 0x00008000 335 + #define chipMinorFeatures6_PE2D_MAJOR_SUPER_TILE 0x00010000 336 + #define chipMinorFeatures6_PE_32BPC_COLORMASK_FIX 0x00020000 337 + #define chipMinorFeatures6_ALPHA_BLENDING_OPT 0x00040000 338 + #define chipMinorFeatures6_NEW_GPIPE 0x00080000 339 + #define chipMinorFeatures6_PIPELINE_32_ATTRIBUTES 0x00100000 340 + #define chipMinorFeatures6_MSAA_SHADING 0x00200000 341 + #define chipMinorFeatures6_NO_ANISTRO_FILTER 0x00400000 342 + #define chipMinorFeatures6_NO_ASTC 0x00800000 343 + #define chipMinorFeatures6_NO_DXT 0x01000000 344 + #define chipMinorFeatures6_HWTFB 0x02000000 345 + #define chipMinorFeatures6_RA_DEPTH_WRITE_MSAA1X_FIX 0x04000000 346 + #define chipMinorFeatures6_EZHZ_CLOCKGATE_FIX 0x08000000 347 + #define chipMinorFeatures6_SH_SNAP2PAGE_FIX 0x10000000 348 + #define chipMinorFeatures6_SH_HALFDEPENDENCY_FIX 0x20000000 349 + #define chipMinorFeatures6_USC_MCFILL_FIX 0x40000000 350 + #define chipMinorFeatures6_TPG_TCPERF_FIX 0x80000000 351 + #define chipMinorFeatures7_USC_MDFIFO_OVERFLOW_FIX 0x00000001 352 + #define chipMinorFeatures7_SH_TEXLD_BARRIER_IN_CS_FIX 0x00000002 353 + #define chipMinorFeatures7_RS_NEW_BASEADDR 0x00000004 354 + #define chipMinorFeatures7_PE_8BPP_DUALPIPE_FIX 0x00000008 355 + #define chipMinorFeatures7_SH_ADVANCED_INSTR 0x00000010 356 + #define chipMinorFeatures7_SH_FLAT_INTERPOLATION_DUAL16_FIX 0x00000020 357 + #define chipMinorFeatures7_USC_CONTINUOUS_FLUS_FIX 0x00000040 358 + #define chipMinorFeatures7_SH_SUPPORT_V4 0x00000080 359 + #define chipMinorFeatures7_SH_SUPPORT_ALPHA_KILL 0x00000100 360 + #define chipMinorFeatures7_PE_NO_ALPHA_TEST 0x00000200 361 + #define chipMinorFeatures7_TX_LOD_NEAREST_SELECT 0x00000400 362 + #define chipMinorFeatures7_SH_FIX_LDEXP 0x00000800 363 + #define chipMinorFeatures7_SUPPORT_MOVAI 0x00001000 364 + #define chipMinorFeatures7_SH_SNAP2PAGE_MAXPAGES_FIX 0x00002000 365 + #define chipMinorFeatures7_PE_RGBA16I_FIX 0x00004000 366 + #define chipMinorFeatures7_BLT_8bpp_256TILE_FC_FIX 0x00008000 367 + #define chipMinorFeatures7_PE_64BIT_FENCE_FIX 0x00010000 368 + #define chipMinorFeatures7_USC_FULL_CACHE_FIX 0x00020000 369 + #define chipMinorFeatures7_TX_YUV_ASSEMBLER_10BIT 0x00040000 370 + #define chipMinorFeatures7_FE_32BIT_INDEX_FIX 0x00080000 371 + #define chipMinorFeatures7_BLT_64BPP_MASKED_CLEAR_FIX 0x00100000 372 + #define chipMinorFeatures7_BIT_SECURITY 0x00200000 373 + #define chipMinorFeatures7_BIT_ROBUSTNESS 0x00400000 374 + #define chipMinorFeatures7_USC_ATOMIC_FIX 0x00800000 375 + #define chipMinorFeatures7_SH_PSO_MSAA1x_FIX 0x01000000 376 + #define chipMinorFeatures7_BIT_USC_VX_PERF_FIX 0x02000000 377 + #define chipMinorFeatures7_EVIS_NO_ABSDIFF 0x04000000 378 + #define chipMinorFeatures7_EVIS_NO_BITREPLACE 0x08000000 379 + #define chipMinorFeatures7_EVIS_NO_BOXFILTER 0x10000000 380 + #define chipMinorFeatures7_EVIS_NO_CORDIAC 0x20000000 381 + #define chipMinorFeatures7_EVIS_NO_DP32 0x40000000 382 + #define chipMinorFeatures7_EVIS_NO_FILTER 0x80000000 383 + #define chipMinorFeatures8_EVIS_NO_IADD 0x00000001 384 + #define chipMinorFeatures8_EVIS_NO_SELECTADD 0x00000002 385 + #define chipMinorFeatures8_EVIS_LERP_7OUTPUT 0x00000004 386 + #define chipMinorFeatures8_EVIS_ACCSQ_8OUTPUT 0x00000008 387 + #define chipMinorFeatures8_USC_GOS_ADDR_FIX 0x00000010 388 + #define chipMinorFeatures8_TX_8BIT_UVFRAC 0x00000020 389 + #define chipMinorFeatures8_TX_DESC_CACHE_CLOCKGATE_FIX 0x00000040 390 + #define chipMinorFeatures8_RSBLT_MSAA_DECOMPRESSION 0x00000080 391 + #define chipMinorFeatures8_TX_INTEGER_COORDINATE 0x00000100 392 + #define chipMinorFeatures8_DRAWID 0x00000200 393 + #define chipMinorFeatures8_PSIO_SAMPLEMASK_IN_R0ZW_FIX 0x00000400 394 + #define chipMinorFeatures8_TX_INTEGER_COORDINATE_V2 0x00000800 395 + #define chipMinorFeatures8_MULTI_CORE_BLOCK_SET_CONFIG 0x00001000 396 + #define chipMinorFeatures8_VG_RESOLVE_ENGINE 0x00002000 397 + #define chipMinorFeatures8_VG_PE_COLOR_KEY 0x00004000 398 + #define chipMinorFeatures8_VG_IM_INDEX_FORMAT 0x00008000 399 + #define chipMinorFeatures8_SNAPPAGE_CMD 0x00010000 400 + #define chipMinorFeatures8_SH_NO_INDEX_CONST_ON_A0 0x00020000 401 + #define chipMinorFeatures8_SH_NO_ONECONST_LIMIT 0x00040000 402 + #define chipMinorFeatures8_SH_IMG_LDST_ON_TEMP 0x00080000 403 + #define chipMinorFeatures8_COMPUTE_ONLY 0x00100000 404 + #define chipMinorFeatures8_SH_IMG_LDST_CLAMP 0x00200000 405 + #define chipMinorFeatures8_SH_ICACHE_ALLOC_COUNT_FIX 0x00400000 406 + #define chipMinorFeatures8_SH_ICACHE_PREFETCH 0x00800000 407 + #define chipMinorFeatures8_PE2D_SEPARATE_CACHE 0x01000000 408 + #define chipMinorFeatures8_VG_AYUV_INPUT_OUTPUT 0x02000000 409 + #define chipMinorFeatures8_VG_DOUBLE_IMAGE 0x04000000 410 + #define chipMinorFeatures8_VG_RECTANGLE_STRIPE_MODE 0x08000000 411 + #define chipMinorFeatures8_VG_MMU 0x10000000 412 + #define chipMinorFeatures8_VG_IM_FILTER 0x20000000 413 + #define chipMinorFeatures8_VG_IM_YUV_PACKET 0x40000000 414 + #define chipMinorFeatures8_VG_IM_YUV_PLANAR 0x80000000 415 + #define chipMinorFeatures9_VG_PE_YUV_PACKET 0x00000001 416 + #define chipMinorFeatures9_VG_COLOR_PRECISION_8_BIT 0x00000002 417 + #define chipMinorFeatures9_PE_MSAA_OQ_FIX 0x00000004 418 + #define chipMinorFeatures9_PSIO_MSAA_CL_FIX 0x00000008 419 + #define chipMinorFeatures9_USC_DEFER_FILL_FIX 0x00000010 420 + #define chipMinorFeatures9_SH_CLOCK_GATE_FIX 0x00000020 421 + #define chipMinorFeatures9_FE_NEED_DUMMYDRAW 0x00000040 422 + #define chipMinorFeatures9_PE2D_LINEAR_YUV420_OUTPUT 0x00000080 423 + #define chipMinorFeatures9_PE2D_LINEAR_YUV420_10BIT 0x00000100 424 + #define chipMinorFeatures9_MULTI_CLUSTER 0x00000200 425 + #define chipMinorFeatures9_VG_TS_CULLING 0x00000400 426 + #define chipMinorFeatures9_VG_FP25 0x00000800 427 + #define chipMinorFeatures9_SH_MULTI_WG_PACK 0x00001000 428 + #define chipMinorFeatures9_SH_DUAL16_SAMPLEMASK_ZW 0x00002000 429 + #define chipMinorFeatures9_TPG_TRIVIAL_MODE_FIX 0x00004000 430 + #define chipMinorFeatures9_TX_ASTC_MULTISLICE_FIX 0x00008000 431 + #define chipMinorFeatures9_FE_ROBUST_FIX 0x00010000 432 + #define chipMinorFeatures9_SH_GPIPE_ACCESS_FULLTEMPS 0x00020000 433 + #define chipMinorFeatures9_PSIO_INTERLOCK 0x00040000 434 + #define chipMinorFeatures9_PA_WIDELINE_FIX 0x00080000 435 + #define chipMinorFeatures9_WIDELINE_HELPER_FIX 0x00100000 436 + #define chipMinorFeatures9_G2D_3RD_PARTY_COMPRESSION_1_1 0x00200000 437 + #define chipMinorFeatures9_TX_FLUSH_L1CACHE 0x00400000 438 + #define chipMinorFeatures9_PE_DITHER_FIX2 0x00800000 439 + #define chipMinorFeatures9_G2D_DEC400 0x01000000 440 + #define chipMinorFeatures9_SH_TEXLD_U_FIX 0x02000000 441 + #define chipMinorFeatures9_MC_FCCACHE_BYTEMASK 0x04000000 442 + #define chipMinorFeatures9_SH_MULTI_WG_PACK_FIX 0x08000000 443 + #define chipMinorFeatures9_DC_OVERLAY_SCALING 0x10000000 444 + #define chipMinorFeatures9_DC_SOURCE_ROTATION 0x20000000 445 + #define chipMinorFeatures9_DC_TILED 0x40000000 446 + #define chipMinorFeatures9_DC_YUV_L1 0x80000000 447 + #define chipMinorFeatures10_DC_D30_OUTPUT 0x00000001 448 + #define chipMinorFeatures10_DC_MMU 0x00000002 449 + #define chipMinorFeatures10_DC_COMPRESSION 0x00000004 450 + #define chipMinorFeatures10_DC_QOS 0x00000008 451 + #define chipMinorFeatures10_PE_ADVANCE_BLEND_PART0 0x00000010 452 + #define chipMinorFeatures10_FE_PATCHLIST_FETCH_FIX 0x00000020 453 + #define chipMinorFeatures10_RA_CG_FIX 0x00000040 454 + #define chipMinorFeatures10_EVIS_VX2 0x00000080 455 + #define chipMinorFeatures10_NN_FLOAT 0x00000100 456 + #define chipMinorFeatures10_DEC400 0x00000200 457 + #define chipMinorFeatures10_LS_SUPPORT_PERCOMP_DEPENDENCY 0x00000400 458 + #define chipMinorFeatures10_TP_ENGINE 0x00000800 459 + #define chipMinorFeatures10_MULTI_CORE_BLOCK_SET_CONFIG2 0x00001000 460 + #define chipMinorFeatures10_PE_VMSAA_COVERAGE_CACHE_FIX 0x00002000 461 + #define chipMinorFeatures10_SECURITY_AHB 0x00004000 462 + #define chipMinorFeatures10_MULTICORE_SEMAPHORESTALL_V3 0x00008000 463 + #define chipMinorFeatures10_SMALLBATCH 0x00010000 464 + #define chipMinorFeatures10_SH_CMPLX 0x00020000 465 + #define chipMinorFeatures10_SH_IDIV0_SWZL_EHS 0x00040000 466 + #define chipMinorFeatures10_TX_LERP_LESS_BIT 0x00080000 467 + #define chipMinorFeatures10_SH_GM_ENDIAN 0x00100000 468 + #define chipMinorFeatures10_SH_GM_USC_UNALLOC 0x00200000 469 + #define chipMinorFeatures10_SH_END_OF_BB 0x00400000 470 + #define chipMinorFeatures10_VIP_V7 0x00800000 471 + #define chipMinorFeatures10_TX_BORDER_CLAMP_FIX 0x01000000 472 + #define chipMinorFeatures10_SH_IMG_LD_LASTPIXEL_FIX 0x02000000 473 + #define chipMinorFeatures10_ASYNC_BLT 0x04000000 474 + #define chipMinorFeatures10_ASYNC_FE_FENCE_FIX 0x08000000 475 + #define chipMinorFeatures10_PSCS_THROTTLE 0x10000000 476 + #define chipMinorFeatures10_SEPARATE_LS 0x20000000 477 + #define chipMinorFeatures10_MCFE 0x40000000 478 + #define chipMinorFeatures10_WIDELINE_TRIANGLE_EMU 0x80000000 479 + #define chipMinorFeatures11_VG_RESOLUTION_8K 0x00000001 480 + #define chipMinorFeatures11_FENCE_32BIT 0x00000002 481 + #define chipMinorFeatures11_FENCE_64BIT 0x00000004 482 + #define chipMinorFeatures11_NN_INTERLEVE8 0x00000008 483 + #define chipMinorFeatures11_TP_REORDER 0x00000010 484 + #define chipMinorFeatures11_PE_DEPTH_ONLY_OQFIX 0x00000020 318 485 319 486 #endif /* COMMON_XML */

+202 -52

drivers/gpu/drm/etnaviv/state.xml.h

··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 1 #ifndef STATE_XML 3 2 #define STATE_XML 4 3 ··· 8 9 git clone git://0x04.net/rules-ng-ng 9 10 10 11 The rules-ng-ng source files this header was generated from are: 11 - - state.xml ( 18882 bytes, from 2015-03-25 11:42:32) 12 - - common.xml ( 18437 bytes, from 2015-03-25 11:27:41) 13 - - state_hi.xml ( 23420 bytes, from 2015-03-25 11:47:21) 14 - - state_2d.xml ( 51549 bytes, from 2015-03-25 11:25:06) 15 - - state_3d.xml ( 54600 bytes, from 2015-03-25 11:25:19) 16 - - state_vg.xml ( 5973 bytes, from 2015-03-25 11:26:01) 12 + - state.xml ( 26087 bytes, from 2017-12-18 16:51:59) 13 + - common.xml ( 35468 bytes, from 2018-01-22 13:48:54) 14 + - common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) 15 + - state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01) 16 + - copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) 17 + - state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56) 18 + - state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59) 19 + - state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59) 20 + - state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56) 17 21 18 - Copyright (C) 2015 22 + Copyright (C) 2012-2017 by the following authors: 23 + - Wladimir J. van der Laan <laanwj@gmail.com> 24 + - Christian Gmeiner <christian.gmeiner@gmail.com> 25 + - Lucas Stach <l.stach@pengutronix.de> 26 + - Russell King <rmk@arm.linux.org.uk> 27 + 28 + Permission is hereby granted, free of charge, to any person obtaining a 29 + copy of this software and associated documentation files (the "Software"), 30 + to deal in the Software without restriction, including without limitation 31 + the rights to use, copy, modify, merge, publish, distribute, sub license, 32 + and/or sell copies of the Software, and to permit persons to whom the 33 + Software is furnished to do so, subject to the following conditions: 34 + 35 + The above copyright notice and this permission notice (including the 36 + next paragraph) shall be included in all copies or substantial portions 37 + of the Software. 38 + 39 + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 40 + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 41 + FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 42 + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 43 + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 45 + DEALINGS IN THE SOFTWARE. 19 46 */ 20 47 21 48 ··· 49 24 #define VARYING_COMPONENT_USE_USED 0x00000001 50 25 #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002 51 26 #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003 27 + #define FE_DATA_TYPE_BYTE 0x00000000 28 + #define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001 29 + #define FE_DATA_TYPE_SHORT 0x00000002 30 + #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003 31 + #define FE_DATA_TYPE_INT 0x00000004 32 + #define FE_DATA_TYPE_UNSIGNED_INT 0x00000005 33 + #define FE_DATA_TYPE_FLOAT 0x00000008 34 + #define FE_DATA_TYPE_HALF_FLOAT 0x00000009 35 + #define FE_DATA_TYPE_FIXED 0x0000000b 36 + #define FE_DATA_TYPE_INT_10_10_10_2 0x0000000c 37 + #define FE_DATA_TYPE_UNSIGNED_INT_10_10_10_2 0x0000000d 38 + #define FE_DATA_TYPE_BYTE_I 0x0000000e 39 + #define FE_DATA_TYPE_SHORT_I 0x0000000f 52 40 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK 0x000000ff 53 41 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT 0 54 42 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK) 43 + #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK 0x00ff0000 44 + #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT 16 45 + #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK) 55 46 #define VIVS_FE 0x00000000 56 47 57 48 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) ··· 75 34 #define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN 0x00000010 76 35 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK 0x0000000f 77 36 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT 0 78 - #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_BYTE 0x00000000 79 - #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_BYTE 0x00000001 80 - #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_SHORT 0x00000002 81 - #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_SHORT 0x00000003 82 - #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_INT 0x00000004 83 - #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_INT 0x00000005 84 - #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT 0x00000008 85 - #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_HALF_FLOAT 0x00000009 86 - #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FIXED 0x0000000b 87 - #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_INT_10_10_10_2 0x0000000c 88 - #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_INT_10_10_10_2 0x0000000d 37 + #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK) 89 38 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK 0x00000030 90 39 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT 4 91 40 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK) ··· 107 76 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR 0x00000000 108 77 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT 0x00000001 109 78 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT 0x00000002 79 + #define VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART 0x00000100 110 80 111 81 #define VIVS_FE_VERTEX_STREAM_BASE_ADDR 0x0000064c 112 82 ··· 183 151 184 152 #define VIVS_FE_AUTO_FLUSH 0x00000670 185 153 154 + #define VIVS_FE_PRIMITIVE_RESTART_INDEX 0x00000674 155 + 186 156 #define VIVS_FE_UNK00678 0x00000678 187 157 188 158 #define VIVS_FE_UNK0067C 0x0000067c ··· 197 163 198 164 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) 199 165 200 - #define VIVS_FE_UNK00700(i0) (0x00000700 + 0x4*(i0)) 201 - #define VIVS_FE_UNK00700__ESIZE 0x00000004 202 - #define VIVS_FE_UNK00700__LEN 0x00000010 166 + #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) 167 + #define VIVS_FE_GENERIC_ATTRIB__ESIZE 0x00000004 168 + #define VIVS_FE_GENERIC_ATTRIB__LEN 0x00000010 203 169 204 - #define VIVS_FE_UNK00740(i0) (0x00000740 + 0x4*(i0)) 205 - #define VIVS_FE_UNK00740__ESIZE 0x00000004 206 - #define VIVS_FE_UNK00740__LEN 0x00000010 170 + #define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0)) 207 171 208 - #define VIVS_FE_UNK00780(i0) (0x00000780 + 0x4*(i0)) 209 - #define VIVS_FE_UNK00780__ESIZE 0x00000004 210 - #define VIVS_FE_UNK00780__LEN 0x00000010 172 + #define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0)) 173 + 174 + #define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0)) 175 + 176 + #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0)) 177 + 178 + #define VIVS_FE_HALTI5_UNK007C4 0x000007c4 179 + 180 + #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0)) 181 + #define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004 182 + #define VIVS_FE_HALTI5_UNK007D0__LEN 0x00000002 183 + 184 + #define VIVS_FE_HALTI5_UNK007D8 0x000007d8 185 + 186 + #define VIVS_FE_DESC_START 0x000007dc 187 + 188 + #define VIVS_FE_DESC_END 0x000007e0 189 + 190 + #define VIVS_FE_DESC_AVAIL 0x000007e4 191 + #define VIVS_FE_DESC_AVAIL_COUNT__MASK 0x0000007f 192 + #define VIVS_FE_DESC_AVAIL_COUNT__SHIFT 0 193 + #define VIVS_FE_DESC_AVAIL_COUNT(x) (((x) << VIVS_FE_DESC_AVAIL_COUNT__SHIFT) & VIVS_FE_DESC_AVAIL_COUNT__MASK) 194 + 195 + #define VIVS_FE_FENCE_WAIT_DATA_LOW 0x000007e8 196 + 197 + #define VIVS_FE_FENCE_WAIT_DATA_HIGH 0x000007f4 198 + 199 + #define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8 211 200 212 201 #define VIVS_GL 0x00000000 213 202 ··· 245 188 #define VIVS_GL_EVENT_EVENT_ID(x) (((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK) 246 189 #define VIVS_GL_EVENT_FROM_FE 0x00000020 247 190 #define VIVS_GL_EVENT_FROM_PE 0x00000040 191 + #define VIVS_GL_EVENT_FROM_BLT 0x00000080 248 192 #define VIVS_GL_EVENT_SOURCE__MASK 0x00001f00 249 193 #define VIVS_GL_EVENT_SOURCE__SHIFT 8 250 194 #define VIVS_GL_EVENT_SOURCE(x) (((x) << VIVS_GL_EVENT_SOURCE__SHIFT) & VIVS_GL_EVENT_SOURCE__MASK) ··· 257 199 #define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK 0x00001f00 258 200 #define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT 8 259 201 #define VIVS_GL_SEMAPHORE_TOKEN_TO(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK) 202 + #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK 0x30000000 203 + #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT 28 204 + #define VIVS_GL_SEMAPHORE_TOKEN_UNK28(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK) 260 205 261 206 #define VIVS_GL_FLUSH_CACHE 0x0000380c 262 207 #define VIVS_GL_FLUSH_CACHE_DEPTH 0x00000001 ··· 269 208 #define VIVS_GL_FLUSH_CACHE_TEXTUREVS 0x00000010 270 209 #define VIVS_GL_FLUSH_CACHE_SHADER_L1 0x00000020 271 210 #define VIVS_GL_FLUSH_CACHE_SHADER_L2 0x00000040 211 + #define VIVS_GL_FLUSH_CACHE_UNK10 0x00000400 212 + #define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800 213 + #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000 214 + #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000 272 215 273 216 #define VIVS_GL_FLUSH_MMU 0x00003810 274 217 #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001 ··· 309 244 #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x) (((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK) 310 245 311 246 #define VIVS_GL_VARYING_NUM_COMPONENTS 0x00003820 312 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__MASK 0x00000007 313 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__SHIFT 0 314 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__MASK) 315 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__MASK 0x00000070 316 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__SHIFT 4 317 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__MASK) 318 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__MASK 0x00000700 319 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__SHIFT 8 320 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__MASK) 321 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__MASK 0x00007000 322 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__SHIFT 12 323 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__MASK) 324 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__MASK 0x00070000 325 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__SHIFT 16 326 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__MASK) 327 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__MASK 0x00700000 328 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__SHIFT 20 329 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__MASK) 330 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__MASK 0x07000000 331 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__SHIFT 24 332 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__MASK) 333 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__MASK 0x70000000 334 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT 28 335 - #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__MASK) 247 + 248 + #define VIVS_GL_OCCLUSION_QUERY_ADDR 0x00003824 336 249 337 250 #define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0)) 338 251 #define VIVS_GL_VARYING_COMPONENT_USE__ESIZE 0x00000004 ··· 364 321 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT 30 365 322 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK) 366 323 324 + #define VIVS_GL_UNK0382C 0x0000382c 325 + 326 + #define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830 327 + 367 328 #define VIVS_GL_UNK03834 0x00003834 368 329 369 330 #define VIVS_GL_UNK03838 0x00003838 ··· 379 332 380 333 #define VIVS_GL_CONTEXT_POINTER 0x00003850 381 334 335 + #define VIVS_GL_UNK03854 0x00003854 336 + 337 + #define VIVS_GL_BUG_FIXES 0x00003860 338 + 339 + #define VIVS_GL_FENCE_OUT_ADDRESS 0x00003868 340 + 341 + #define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c 342 + 343 + #define VIVS_GL_HALTI5_UNK03884 0x00003884 344 + 345 + #define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888 346 + #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f 347 + #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT 0 348 + #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK) 349 + #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK 0x00007f00 350 + #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT 8 351 + #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK) 352 + #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK 0x007f0000 353 + #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT 16 354 + #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK) 355 + #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK 0xff000000 356 + #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT 24 357 + #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK) 358 + 359 + #define VIVS_GL_GS_UNK0388C 0x0000388c 360 + 361 + #define VIVS_GL_FENCE_OUT_DATA_HIGH 0x00003898 362 + 363 + #define VIVS_GL_SHADER_INDEX 0x0000389c 364 + 365 + #define VIVS_GL_GS_UNK038A0(i0) (0x000038a0 + 0x4*(i0)) 366 + #define VIVS_GL_GS_UNK038A0__ESIZE 0x00000004 367 + #define VIVS_GL_GS_UNK038A0__LEN 0x00000008 368 + 369 + #define VIVS_GL_HALTI5_UNK038C0(i0) (0x000038c0 + 0x4*(i0)) 370 + #define VIVS_GL_HALTI5_UNK038C0__ESIZE 0x00000004 371 + #define VIVS_GL_HALTI5_UNK038C0__LEN 0x00000010 372 + 373 + #define VIVS_GL_SECURITY_UNK3900 0x00003900 374 + 375 + #define VIVS_GL_SECURITY_UNK3904 0x00003904 376 + 382 377 #define VIVS_GL_UNK03A00 0x00003a00 378 + 379 + #define VIVS_GL_UNK03A04 0x00003a04 380 + 381 + #define VIVS_GL_UNK03A08 0x00003a08 382 + 383 + #define VIVS_GL_UNK03A0C 0x00003a0c 384 + 385 + #define VIVS_GL_UNK03A10 0x00003a10 383 386 384 387 #define VIVS_GL_STALL_TOKEN 0x00003c00 385 388 #define VIVS_GL_STALL_TOKEN_FROM__MASK 0x0000001f ··· 440 343 #define VIVS_GL_STALL_TOKEN_TO(x) (((x) << VIVS_GL_STALL_TOKEN_TO__SHIFT) & VIVS_GL_STALL_TOKEN_TO__MASK) 441 344 #define VIVS_GL_STALL_TOKEN_FLIP0 0x40000000 442 345 #define VIVS_GL_STALL_TOKEN_FLIP1 0x80000000 346 + 347 + #define VIVS_NFE 0x00000000 348 + 349 + #define VIVS_NFE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) 350 + #define VIVS_NFE_VERTEX_STREAMS__ESIZE 0x00000004 351 + #define VIVS_NFE_VERTEX_STREAMS__LEN 0x00000010 352 + 353 + #define VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00014600 + 0x4*(i0)) 354 + 355 + #define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0)) 356 + 357 + #define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0) (0x00014680 + 0x4*(i0)) 358 + 359 + #define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0)) 360 + 361 + #define VIVS_NFE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) 362 + #define VIVS_NFE_GENERIC_ATTRIB__ESIZE 0x00000004 363 + #define VIVS_NFE_GENERIC_ATTRIB__LEN 0x00000020 364 + 365 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0) (0x00017800 + 0x4*(i0)) 366 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK 0x0000000f 367 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT 0 368 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK) 369 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK 0x00000030 370 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT 4 371 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK) 372 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK 0x00000700 373 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT 8 374 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK) 375 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK 0x00003000 376 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT 12 377 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK) 378 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK 0x0000c000 379 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__SHIFT 14 380 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF 0x00000000 381 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON 0x00008000 382 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK 0x00ff0000 383 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT 16 384 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK) 385 + 386 + #define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0) (0x00017880 + 0x4*(i0)) 387 + 388 + #define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0) (0x00017900 + 0x4*(i0)) 389 + 390 + #define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0) (0x00017980 + 0x4*(i0)) 391 + 392 + #define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0) (0x00017a00 + 0x4*(i0)) 393 + 394 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0) (0x00017a80 + 0x4*(i0)) 395 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK 0x000000ff 396 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT 0 397 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK) 398 + #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE 0x00000800 443 399 444 400 #define VIVS_DUMMY 0x00000000 445 401

+5

drivers/gpu/drm/etnaviv/state_3d.xml.h

··· 7 7 #define VIVS_TS_FLUSH_CACHE 0x00001650 8 8 #define VIVS_TS_FLUSH_CACHE_FLUSH 0x00000001 9 9 10 + #define VIVS_NTE_DESCRIPTOR_FLUSH 0x00014c44 11 + #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK 0xf0000000 12 + #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT 28 13 + #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28(x) (((x) << VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT) & VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK) 14 + 10 15 #endif /* STATE_3D_XML */

+52

drivers/gpu/drm/etnaviv/state_blt.xml.h

··· 1 + #ifndef STATE_BLT_XML 2 + #define STATE_BLT_XML 3 + 4 + /* Autogenerated file, DO NOT EDIT manually! 5 + 6 + This file was generated by the rules-ng-ng headergen tool in this git repository: 7 + http://0x04.net/cgit/index.cgi/rules-ng-ng 8 + git clone git://0x04.net/rules-ng-ng 9 + 10 + The rules-ng-ng source files this header was generated from are: 11 + - state.xml ( 26087 bytes, from 2017-12-18 16:51:59) 12 + - common.xml ( 35468 bytes, from 2018-01-22 13:48:54) 13 + - common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) 14 + - state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01) 15 + - copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) 16 + - state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56) 17 + - state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59) 18 + - state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59) 19 + - state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56) 20 + 21 + Copyright (C) 2012-2017 by the following authors: 22 + - Wladimir J. van der Laan <laanwj@gmail.com> 23 + - Christian Gmeiner <christian.gmeiner@gmail.com> 24 + - Lucas Stach <l.stach@pengutronix.de> 25 + - Russell King <rmk@arm.linux.org.uk> 26 + 27 + Permission is hereby granted, free of charge, to any person obtaining a 28 + copy of this software and associated documentation files (the "Software"), 29 + to deal in the Software without restriction, including without limitation 30 + the rights to use, copy, modify, merge, publish, distribute, sub license, 31 + and/or sell copies of the Software, and to permit persons to whom the 32 + Software is furnished to do so, subject to the following conditions: 33 + 34 + The above copyright notice and this permission notice (including the 35 + next paragraph) shall be included in all copies or substantial portions 36 + of the Software. 37 + 38 + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 39 + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 40 + FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 41 + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 42 + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 44 + DEALINGS IN THE SOFTWARE. 45 + */ 46 + 47 + /* This is a cut-down version of the state_blt.xml.h file */ 48 + 49 + #define VIVS_BLT_ENABLE 0x000140b8 50 + #define VIVS_BLT_ENABLE_ENABLE 0x00000001 51 + 52 + #endif /* STATE_BLT_XML */

+133 -15

drivers/gpu/drm/etnaviv/state_hi.xml.h

··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 1 #ifndef STATE_HI_XML 3 2 #define STATE_HI_XML 4 3 ··· 8 9 git clone git://0x04.net/rules-ng-ng 9 10 10 11 The rules-ng-ng source files this header was generated from are: 11 - - state_hi.xml ( 25620 bytes, from 2016-08-19 22:07:37) 12 - - common.xml ( 20583 bytes, from 2016-06-07 05:22:38) 12 + - state.xml ( 26087 bytes, from 2017-12-18 16:51:59) 13 + - common.xml ( 35468 bytes, from 2018-01-22 13:48:54) 14 + - common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) 15 + - state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01) 16 + - copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) 17 + - state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56) 18 + - state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59) 19 + - state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59) 20 + - state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56) 13 21 14 - Copyright (C) 2016 22 + Copyright (C) 2012-2018 by the following authors: 23 + - Wladimir J. van der Laan <laanwj@gmail.com> 24 + - Christian Gmeiner <christian.gmeiner@gmail.com> 25 + - Lucas Stach <l.stach@pengutronix.de> 26 + - Russell King <rmk@arm.linux.org.uk> 27 + 28 + Permission is hereby granted, free of charge, to any person obtaining a 29 + copy of this software and associated documentation files (the "Software"), 30 + to deal in the Software without restriction, including without limitation 31 + the rights to use, copy, modify, merge, publish, distribute, sub license, 32 + and/or sell copies of the Software, and to permit persons to whom the 33 + Software is furnished to do so, subject to the following conditions: 34 + 35 + The above copyright notice and this permission notice (including the 36 + next paragraph) shall be included in all copies or substantial portions 37 + of the Software. 38 + 39 + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 40 + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 41 + FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 42 + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 43 + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 45 + DEALINGS IN THE SOFTWARE. 15 46 */ 16 47 17 48 ··· 221 192 #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT 0 222 193 #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK) 223 194 195 + #define VIVS_HI_COMPRESSION_FLAGS 0x00000090 196 + #define VIVS_HI_COMPRESSION_FLAGS_DEC300 0x00000040 197 + 224 198 #define VIVS_HI_CHIP_MINOR_FEATURE_4 0x00000094 225 199 226 200 #define VIVS_HI_CHIP_SPECS_4 0x0000009c ··· 234 202 #define VIVS_HI_CHIP_MINOR_FEATURE_5 0x000000a0 235 203 236 204 #define VIVS_HI_CHIP_PRODUCT_ID 0x000000a8 205 + 206 + #define VIVS_HI_BLT_INTR 0x000000d4 207 + 208 + #define VIVS_HI_AUXBIT 0x000000ec 237 209 238 210 #define VIVS_PM 0x00000000 239 211 ··· 275 239 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX 0x00000080 276 240 277 241 #define VIVS_PM_PULSE_EATER 0x0000010c 242 + #define VIVS_PM_PULSE_EATER_DISABLE 0x00000001 243 + #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK 0x0000ff00 244 + #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT 8 245 + #define VIVS_PM_PULSE_EATER_DVFS_PERIOD(x) (((x) << VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT) & VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK) 246 + #define VIVS_PM_PULSE_EATER_UNK16 0x00010000 247 + #define VIVS_PM_PULSE_EATER_UNK17 0x00020000 248 + #define VIVS_PM_PULSE_EATER_INTERNAL_DFS 0x00040000 249 + #define VIVS_PM_PULSE_EATER_UNK19 0x00080000 250 + #define VIVS_PM_PULSE_EATER_UNK20 0x00100000 251 + #define VIVS_PM_PULSE_EATER_UNK22 0x00400000 252 + #define VIVS_PM_PULSE_EATER_UNK23 0x00800000 278 253 279 254 #define VIVS_MMUv2 0x00000000 280 255 ··· 326 279 #define VIVS_MMUv2_EXCEPTION_ADDR(i0) (0x00000190 + 0x4*(i0)) 327 280 #define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE 0x00000004 328 281 #define VIVS_MMUv2_EXCEPTION_ADDR__LEN 0x00000004 282 + 283 + #define VIVS_MMUv2_PROFILE_BLT_READ 0x000001a4 284 + 285 + #define VIVS_MMUv2_PTA_CONFIG 0x000001ac 286 + #define VIVS_MMUv2_PTA_CONFIG_INDEX__MASK 0x0000ffff 287 + #define VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT 0 288 + #define VIVS_MMUv2_PTA_CONFIG_INDEX(x) (((x) << VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT) & VIVS_MMUv2_PTA_CONFIG_INDEX__MASK) 289 + #define VIVS_MMUv2_PTA_CONFIG_UNK16 0x00010000 290 + 291 + #define VIVS_MMUv2_AXI_POLICY(i0) (0x000001c0 + 0x4*(i0)) 292 + #define VIVS_MMUv2_AXI_POLICY__ESIZE 0x00000004 293 + #define VIVS_MMUv2_AXI_POLICY__LEN 0x00000008 294 + 295 + #define VIVS_MMUv2_SEC_EXCEPTION_ADDR 0x00000380 296 + 297 + #define VIVS_MMUv2_SEC_STATUS 0x00000384 298 + #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK 0x00000003 299 + #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT 0 300 + #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK) 301 + #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK 0x00000030 302 + #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT 4 303 + #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK) 304 + #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK 0x00000300 305 + #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT 8 306 + #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK) 307 + #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK 0x00003000 308 + #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT 12 309 + #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK) 310 + 311 + #define VIVS_MMUv2_SEC_CONTROL 0x00000388 312 + #define VIVS_MMUv2_SEC_CONTROL_ENABLE 0x00000001 313 + 314 + #define VIVS_MMUv2_PTA_ADDRESS_LOW 0x0000038c 315 + 316 + #define VIVS_MMUv2_PTA_ADDRESS_HIGH 0x00000390 317 + 318 + #define VIVS_MMUv2_PTA_CONTROL 0x00000394 319 + #define VIVS_MMUv2_PTA_CONTROL_ENABLE 0x00000001 320 + 321 + #define VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW 0x00000398 322 + 323 + #define VIVS_MMUv2_SEC_SAFE_ADDR_LOW 0x0000039c 324 + 325 + #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG 0x000003a0 326 + #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK 0x000000ff 327 + #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT 0 328 + #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK) 329 + #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK15 0x00008000 330 + #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK 0x00ff0000 331 + #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT 16 332 + #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK) 333 + #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK31 0x80000000 334 + 335 + #define VIVS_MMUv2_SEC_COMMAND_CONTROL 0x000003a4 336 + #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff 337 + #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT 0 338 + #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(x) (((x) << VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK) 339 + #define VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE 0x00010000 340 + 341 + #define VIVS_MMUv2_AHB_CONTROL 0x000003a8 342 + #define VIVS_MMUv2_AHB_CONTROL_RESET 0x00000001 343 + #define VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS 0x00000002 329 344 330 345 #define VIVS_MC 0x00000000 331 346 ··· 449 340 #define VIVS_MC_PROFILE_HI_READ 0x0000046c 450 341 451 342 #define VIVS_MC_PROFILE_CONFIG0 0x00000470 452 - #define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x0000000f 343 + #define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x000000ff 453 344 #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT 0 454 345 #define VIVS_MC_PROFILE_CONFIG0_FE_RESET 0x0000000f 455 - #define VIVS_MC_PROFILE_CONFIG0_DE__MASK 0x00000f00 346 + #define VIVS_MC_PROFILE_CONFIG0_DE__MASK 0x0000ff00 456 347 #define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT 8 457 348 #define VIVS_MC_PROFILE_CONFIG0_DE_RESET 0x00000f00 458 - #define VIVS_MC_PROFILE_CONFIG0_PE__MASK 0x000f0000 349 + #define VIVS_MC_PROFILE_CONFIG0_PE__MASK 0x00ff0000 459 350 #define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT 16 460 351 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE 0x00000000 461 352 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE 0x00010000 ··· 463 354 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE 0x00030000 464 355 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D 0x000b0000 465 356 #define VIVS_MC_PROFILE_CONFIG0_PE_RESET 0x000f0000 466 - #define VIVS_MC_PROFILE_CONFIG0_SH__MASK 0x0f000000 357 + #define VIVS_MC_PROFILE_CONFIG0_SH__MASK 0xff000000 467 358 #define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT 24 468 359 #define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES 0x04000000 469 360 #define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER 0x07000000 ··· 477 368 #define VIVS_MC_PROFILE_CONFIG0_SH_RESET 0x0f000000 478 369 479 370 #define VIVS_MC_PROFILE_CONFIG1 0x00000474 480 - #define VIVS_MC_PROFILE_CONFIG1_PA__MASK 0x0000000f 371 + #define VIVS_MC_PROFILE_CONFIG1_PA__MASK 0x000000ff 481 372 #define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT 0 482 373 #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER 0x00000003 483 374 #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER 0x00000004 ··· 486 377 #define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER 0x00000007 487 378 #define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER 0x00000008 488 379 #define VIVS_MC_PROFILE_CONFIG1_PA_RESET 0x0000000f 489 - #define VIVS_MC_PROFILE_CONFIG1_SE__MASK 0x00000f00 380 + #define VIVS_MC_PROFILE_CONFIG1_SE__MASK 0x0000ff00 490 381 #define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT 8 491 382 #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT 0x00000000 492 383 #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT 0x00000100 493 384 #define VIVS_MC_PROFILE_CONFIG1_SE_RESET 0x00000f00 494 - #define VIVS_MC_PROFILE_CONFIG1_RA__MASK 0x000f0000 385 + #define VIVS_MC_PROFILE_CONFIG1_RA__MASK 0x00ff0000 495 386 #define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT 16 496 387 #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT 0x00000000 497 388 #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT 0x00010000 ··· 501 392 #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER 0x000a0000 502 393 #define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT 0x000b0000 503 394 #define VIVS_MC_PROFILE_CONFIG1_RA_RESET 0x000f0000 504 - #define VIVS_MC_PROFILE_CONFIG1_TX__MASK 0x0f000000 395 + #define VIVS_MC_PROFILE_CONFIG1_TX__MASK 0xff000000 505 396 #define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT 24 506 397 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS 0x00000000 507 398 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS 0x01000000 ··· 516 407 #define VIVS_MC_PROFILE_CONFIG1_TX_RESET 0x0f000000 517 408 518 409 #define VIVS_MC_PROFILE_CONFIG2 0x00000478 519 - #define VIVS_MC_PROFILE_CONFIG2_MC__MASK 0x0000000f 410 + #define VIVS_MC_PROFILE_CONFIG2_MC__MASK 0x000000ff 520 411 #define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT 0 521 412 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE 0x00000001 522 413 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP 0x00000002 523 414 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE 0x00000003 524 415 #define VIVS_MC_PROFILE_CONFIG2_MC_RESET 0x0000000f 525 - #define VIVS_MC_PROFILE_CONFIG2_HI__MASK 0x00000f00 416 + #define VIVS_MC_PROFILE_CONFIG2_HI__MASK 0x0000ff00 526 417 #define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT 8 527 418 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED 0x00000000 528 419 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED 0x00000100 529 420 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED 0x00000200 530 421 #define VIVS_MC_PROFILE_CONFIG2_HI_RESET 0x00000f00 422 + #define VIVS_MC_PROFILE_CONFIG2_BLT__MASK 0xff000000 423 + #define VIVS_MC_PROFILE_CONFIG2_BLT__SHIFT 24 424 + #define VIVS_MC_PROFILE_CONFIG2_BLT_UNK0 0x00000000 531 425 532 426 #define VIVS_MC_PROFILE_CONFIG3 0x0000047c 533 427 ··· 544 432 545 433 #define VIVS_MC_START_COMPOSITION 0x00000554 546 434 547 - #define VIVS_MC_128B_MERGE 0x00000558 435 + #define VIVS_MC_FLAGS 0x00000558 436 + #define VIVS_MC_FLAGS_128B_MERGE 0x00000001 437 + #define VIVS_MC_FLAGS_TPCV11_COMPRESSION 0x08000000 438 + 439 + #define VIVS_MC_L2_CACHE_CONFIG 0x0000055c 440 + 441 + #define VIVS_MC_PROFILE_L2_READ 0x00000564 548 442 549 443 550 444 #endif /* STATE_HI_XML */