tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
spi: mediatek: adjust register to enhance time accuracy
this patch adjust register to enhance time accuracy.
Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Leilk Liu
and committed by
Mark Brown
058fe49d
d27ae103
+42
-5
+40
-5
drivers/spi/spi-mt65xx.c
+40
-5
drivers/spi/spi-mt65xx.c
···
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#define SPI_CMD_REG 0x0018
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#define SPI_STATUS0_REG 0x001c
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#define SPI_PAD_SEL_REG 0x0024
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#define SPI_CFG2_REG 0x0028
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#define SPI_CFG0_SCK_HIGH_OFFSET 0
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#define SPI_CFG0_SCK_LOW_OFFSET 8
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#define SPI_CFG0_CS_HOLD_OFFSET 16
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#define SPI_CFG0_CS_SETUP_OFFSET 24
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#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16
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#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
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#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
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#define SPI_CFG1_CS_IDLE_OFFSET 0
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#define SPI_CFG1_PACKET_LOOP_OFFSET 8
···
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#define SPI_CMD_RST BIT(2)
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#define SPI_CMD_PAUSE_EN BIT(4)
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#define SPI_CMD_DEASSERT BIT(5)
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#define SPI_CMD_SAMPLE_SEL BIT(6)
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#define SPI_CMD_CS_POL BIT(7)
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#define SPI_CMD_CPHA BIT(8)
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#define SPI_CMD_CPOL BIT(9)
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#define SPI_CMD_RX_DMA BIT(10)
···
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bool need_pad_sel;
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/* Must explicitly send dummy Tx bytes to do Rx only transfer */
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bool must_tx;
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/* some IC design adjust cfg register to enhance time accuracy */
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bool enhance_timing;
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};
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struct mtk_spi {
···
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static const struct mtk_chip_config mtk_default_chip_info = {
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.rx_mlsb = 1,
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.tx_mlsb = 1,
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.cs_pol = 0,
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.sample_sel = 0,
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};
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static const struct of_device_id mtk_spi_of_match[] = {
···
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reg_val |= SPI_CMD_RX_ENDIAN;
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#endif
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if (mdata->dev_comp->enhance_timing) {
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if (chip_config->cs_pol)
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reg_val |= SPI_CMD_CS_POL;
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else
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reg_val &= ~SPI_CMD_CS_POL;
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if (chip_config->sample_sel)
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reg_val |= SPI_CMD_SAMPLE_SEL;
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else
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reg_val &= ~SPI_CMD_SAMPLE_SEL;
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}
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/* set finish and pause interrupt always enable */
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reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
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···
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sck_time = (div + 1) / 2;
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cs_time = sck_time * 2;
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-
reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET);
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reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
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reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
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reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
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writel(reg_val, mdata->base + SPI_CFG0_REG);
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if (mdata->dev_comp->enhance_timing) {
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reg_val |= (((sck_time - 1) & 0xffff)
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<< SPI_CFG0_SCK_HIGH_OFFSET);
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reg_val |= (((sck_time - 1) & 0xffff)
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<< SPI_ADJUST_CFG0_SCK_LOW_OFFSET);
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writel(reg_val, mdata->base + SPI_CFG2_REG);
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reg_val |= (((cs_time - 1) & 0xffff)
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<< SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
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reg_val |= (((cs_time - 1) & 0xffff)
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<< SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
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writel(reg_val, mdata->base + SPI_CFG0_REG);
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} else {
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reg_val |= (((sck_time - 1) & 0xff)
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<< SPI_CFG0_SCK_HIGH_OFFSET);
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reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
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reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
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reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
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writel(reg_val, mdata->base + SPI_CFG0_REG);
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}
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reg_val = readl(mdata->base + SPI_CFG1_REG);
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reg_val &= ~SPI_CFG1_CS_IDLE_MASK;