tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

pinctrl: sunxi: Add driver for Allwinner D1

This SoC contains a pinctrl with a new register layout. Use the variant
parameter to set the right register offsets. This pinctrl also increases
the number of functions per pin from 8 to 16, taking advantage of all 4
bits in the mux config field (so far, only functions 0-8 and 14-15 are
used). This increases the maximum possible number of functions.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20220713025233.27248-7-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Samuel Holland and committed by
Linus Walleij 0569af48 622b681e

+863 -5
+5
drivers/pinctrl/sunxi/Kconfig
··· 81 81 default MACH_SUN9I 82 82 select PINCTRL_SUNXI 83 83 84 + config PINCTRL_SUN20I_D1 85 + bool "Support for the Allwinner D1 PIO" 86 + default MACH_SUN8I || (RISCV && ARCH_SUNXI) 87 + select PINCTRL_SUNXI 88 + 84 89 config PINCTRL_SUN50I_A64 85 90 bool "Support for the Allwinner A64 PIO" 86 91 default ARM64 && ARCH_SUNXI
+1
drivers/pinctrl/sunxi/Makefile
··· 20 20 obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o 21 21 obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o 22 22 obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o 23 + obj-$(CONFIG_PINCTRL_SUN20I_D1) += pinctrl-sun20i-d1.o 23 24 obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o 24 25 obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o 25 26 obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o
+840
drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Allwinner D1 SoC pinctrl driver. 4 + * 5 + * Copyright (c) 2020 wuyan@allwinnertech.com 6 + * Copyright (c) 2021-2022 Samuel Holland <samuel@sholland.org> 7 + */ 8 + 9 + #include <linux/module.h> 10 + #include <linux/platform_device.h> 11 + #include <linux/of.h> 12 + #include <linux/of_device.h> 13 + #include <linux/pinctrl/pinctrl.h> 14 + 15 + #include "pinctrl-sunxi.h" 16 + 17 + static const struct sunxi_desc_pin d1_pins[] = { 18 + /* PB */ 19 + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), 20 + SUNXI_FUNCTION(0x0, "gpio_in"), 21 + SUNXI_FUNCTION(0x1, "gpio_out"), 22 + SUNXI_FUNCTION(0x2, "pwm3"), 23 + SUNXI_FUNCTION(0x3, "ir"), /* TX */ 24 + SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */ 25 + SUNXI_FUNCTION(0x5, "spi1"), /* WP */ 26 + SUNXI_FUNCTION(0x6, "uart0"), /* TX */ 27 + SUNXI_FUNCTION(0x7, "uart2"), /* TX */ 28 + SUNXI_FUNCTION(0x8, "spdif"), /* OUT */ 29 + SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 0)), 30 + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), 31 + SUNXI_FUNCTION(0x0, "gpio_in"), 32 + SUNXI_FUNCTION(0x1, "gpio_out"), 33 + SUNXI_FUNCTION(0x2, "pwm4"), 34 + SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT3 */ 35 + SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */ 36 + SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN3 */ 37 + SUNXI_FUNCTION(0x6, "uart0"), /* RX */ 38 + SUNXI_FUNCTION(0x7, "uart2"), /* RX */ 39 + SUNXI_FUNCTION(0x8, "ir"), /* RX */ 40 + SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 1)), 41 + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), 42 + SUNXI_FUNCTION(0x0, "gpio_in"), 43 + SUNXI_FUNCTION(0x1, "gpio_out"), 44 + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ 45 + SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT2 */ 46 + SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */ 47 + SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN2 */ 48 + SUNXI_FUNCTION(0x6, "lcd0"), /* D18 */ 49 + SUNXI_FUNCTION(0x7, "uart4"), /* TX */ 50 + SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 2)), 51 + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), 52 + SUNXI_FUNCTION(0x0, "gpio_in"), 53 + SUNXI_FUNCTION(0x1, "gpio_out"), 54 + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ 55 + SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT1 */ 56 + SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */ 57 + SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN0 */ 58 + SUNXI_FUNCTION(0x6, "lcd0"), /* D19 */ 59 + SUNXI_FUNCTION(0x7, "uart4"), /* RX */ 60 + SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 3)), 61 + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), 62 + SUNXI_FUNCTION(0x0, "gpio_in"), 63 + SUNXI_FUNCTION(0x1, "gpio_out"), 64 + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ 65 + SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT0 */ 66 + SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */ 67 + SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN1 */ 68 + SUNXI_FUNCTION(0x6, "lcd0"), /* D20 */ 69 + SUNXI_FUNCTION(0x7, "uart5"), /* TX */ 70 + SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 4)), 71 + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), 72 + SUNXI_FUNCTION(0x0, "gpio_in"), 73 + SUNXI_FUNCTION(0x1, "gpio_out"), 74 + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ 75 + SUNXI_FUNCTION(0x3, "i2s2"), /* BCLK */ 76 + SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */ 77 + SUNXI_FUNCTION(0x5, "pwm0"), 78 + SUNXI_FUNCTION(0x6, "lcd0"), /* D21 */ 79 + SUNXI_FUNCTION(0x7, "uart5"), /* RX */ 80 + SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 5)), 81 + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), 82 + SUNXI_FUNCTION(0x0, "gpio_in"), 83 + SUNXI_FUNCTION(0x1, "gpio_out"), 84 + SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ 85 + SUNXI_FUNCTION(0x3, "i2s2"), /* LRCK */ 86 + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */ 87 + SUNXI_FUNCTION(0x5, "pwm1"), 88 + SUNXI_FUNCTION(0x6, "lcd0"), /* D22 */ 89 + SUNXI_FUNCTION(0x7, "uart3"), /* TX */ 90 + SUNXI_FUNCTION(0x8, "bist0"), /* BIST_RESULT0 */ 91 + SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 6)), 92 + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), 93 + SUNXI_FUNCTION(0x0, "gpio_in"), 94 + SUNXI_FUNCTION(0x1, "gpio_out"), 95 + SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ 96 + SUNXI_FUNCTION(0x3, "i2s2"), /* MCLK */ 97 + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */ 98 + SUNXI_FUNCTION(0x5, "ir"), /* RX */ 99 + SUNXI_FUNCTION(0x6, "lcd0"), /* D23 */ 100 + SUNXI_FUNCTION(0x7, "uart3"), /* RX */ 101 + SUNXI_FUNCTION(0x8, "bist1"), /* BIST_RESULT1 */ 102 + SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 7)), 103 + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), 104 + SUNXI_FUNCTION(0x0, "gpio_in"), 105 + SUNXI_FUNCTION(0x1, "gpio_out"), 106 + SUNXI_FUNCTION(0x2, "dmic"), /* DATA3 */ 107 + SUNXI_FUNCTION(0x3, "pwm5"), 108 + SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */ 109 + SUNXI_FUNCTION(0x5, "spi1"), /* HOLD */ 110 + SUNXI_FUNCTION(0x6, "uart0"), /* TX */ 111 + SUNXI_FUNCTION(0x7, "uart1"), /* TX */ 112 + SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 8)), 113 + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), 114 + SUNXI_FUNCTION(0x0, "gpio_in"), 115 + SUNXI_FUNCTION(0x1, "gpio_out"), 116 + SUNXI_FUNCTION(0x2, "dmic"), /* DATA2 */ 117 + SUNXI_FUNCTION(0x3, "pwm6"), 118 + SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */ 119 + SUNXI_FUNCTION(0x5, "spi1"), /* MISO */ 120 + SUNXI_FUNCTION(0x6, "uart0"), /* RX */ 121 + SUNXI_FUNCTION(0x7, "uart1"), /* RX */ 122 + SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 9)), 123 + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), 124 + SUNXI_FUNCTION(0x0, "gpio_in"), 125 + SUNXI_FUNCTION(0x1, "gpio_out"), 126 + SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */ 127 + SUNXI_FUNCTION(0x3, "pwm7"), 128 + SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */ 129 + SUNXI_FUNCTION(0x5, "spi1"), /* MOSI */ 130 + SUNXI_FUNCTION(0x6, "clk"), /* FANOUT0 */ 131 + SUNXI_FUNCTION(0x7, "uart1"), /* RTS */ 132 + SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 10)), 133 + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), 134 + SUNXI_FUNCTION(0x0, "gpio_in"), 135 + SUNXI_FUNCTION(0x1, "gpio_out"), 136 + SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */ 137 + SUNXI_FUNCTION(0x3, "pwm2"), 138 + SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */ 139 + SUNXI_FUNCTION(0x5, "spi1"), /* CLK */ 140 + SUNXI_FUNCTION(0x6, "clk"), /* FANOUT1 */ 141 + SUNXI_FUNCTION(0x7, "uart1"), /* CTS */ 142 + SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 11)), 143 + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), 144 + SUNXI_FUNCTION(0x0, "gpio_in"), 145 + SUNXI_FUNCTION(0x1, "gpio_out"), 146 + SUNXI_FUNCTION(0x2, "dmic"), /* CLK */ 147 + SUNXI_FUNCTION(0x3, "pwm0"), 148 + SUNXI_FUNCTION(0x4, "spdif"), /* IN */ 149 + SUNXI_FUNCTION(0x5, "spi1"), /* CS0 */ 150 + SUNXI_FUNCTION(0x6, "clk"), /* FANOUT2 */ 151 + SUNXI_FUNCTION(0x7, "ir"), /* RX */ 152 + SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 12)), 153 + /* PC */ 154 + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 155 + SUNXI_FUNCTION(0x0, "gpio_in"), 156 + SUNXI_FUNCTION(0x1, "gpio_out"), 157 + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ 158 + SUNXI_FUNCTION(0x3, "i2c2"), /* SCK */ 159 + SUNXI_FUNCTION(0x4, "ledc"), 160 + SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 0)), 161 + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), 162 + SUNXI_FUNCTION(0x0, "gpio_in"), 163 + SUNXI_FUNCTION(0x1, "gpio_out"), 164 + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ 165 + SUNXI_FUNCTION(0x3, "i2c2"), /* SDA */ 166 + SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 1)), 167 + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), 168 + SUNXI_FUNCTION(0x0, "gpio_in"), 169 + SUNXI_FUNCTION(0x1, "gpio_out"), 170 + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ 171 + SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */ 172 + SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 2)), 173 + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), 174 + SUNXI_FUNCTION(0x0, "gpio_in"), 175 + SUNXI_FUNCTION(0x1, "gpio_out"), 176 + SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ 177 + SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */ 178 + SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 3)), 179 + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), 180 + SUNXI_FUNCTION(0x0, "gpio_in"), 181 + SUNXI_FUNCTION(0x1, "gpio_out"), 182 + SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ 183 + SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */ 184 + SUNXI_FUNCTION(0x4, "boot"), /* SEL0 */ 185 + SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 4)), 186 + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), 187 + SUNXI_FUNCTION(0x0, "gpio_in"), 188 + SUNXI_FUNCTION(0x1, "gpio_out"), 189 + SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ 190 + SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */ 191 + SUNXI_FUNCTION(0x4, "boot"), /* SEL1 */ 192 + SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 5)), 193 + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), 194 + SUNXI_FUNCTION(0x0, "gpio_in"), 195 + SUNXI_FUNCTION(0x1, "gpio_out"), 196 + SUNXI_FUNCTION(0x2, "spi0"), /* WP */ 197 + SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */ 198 + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ 199 + SUNXI_FUNCTION(0x5, "i2c3"), /* SCK */ 200 + SUNXI_FUNCTION(0x6, "pll"), /* DBG-CLK */ 201 + SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 6)), 202 + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), 203 + SUNXI_FUNCTION(0x0, "gpio_in"), 204 + SUNXI_FUNCTION(0x1, "gpio_out"), 205 + SUNXI_FUNCTION(0x2, "spi0"), /* HOLD */ 206 + SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */ 207 + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ 208 + SUNXI_FUNCTION(0x5, "i2c3"), /* SDA */ 209 + SUNXI_FUNCTION(0x6, "tcon"), /* TRIG0 */ 210 + SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 7)), 211 + /* PD */ 212 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), 213 + SUNXI_FUNCTION(0x0, "gpio_in"), 214 + SUNXI_FUNCTION(0x1, "gpio_out"), 215 + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ 216 + SUNXI_FUNCTION(0x3, "lvds0"), /* V0P */ 217 + SUNXI_FUNCTION(0x4, "dsi"), /* D0P */ 218 + SUNXI_FUNCTION(0x5, "i2c0"), /* SCK */ 219 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 0)), 220 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), 221 + SUNXI_FUNCTION(0x0, "gpio_in"), 222 + SUNXI_FUNCTION(0x1, "gpio_out"), 223 + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ 224 + SUNXI_FUNCTION(0x3, "lvds0"), /* V0N */ 225 + SUNXI_FUNCTION(0x4, "dsi"), /* D0N */ 226 + SUNXI_FUNCTION(0x5, "uart2"), /* TX */ 227 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 1)), 228 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), 229 + SUNXI_FUNCTION(0x0, "gpio_in"), 230 + SUNXI_FUNCTION(0x1, "gpio_out"), 231 + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ 232 + SUNXI_FUNCTION(0x3, "lvds0"), /* V1P */ 233 + SUNXI_FUNCTION(0x4, "dsi"), /* D1P */ 234 + SUNXI_FUNCTION(0x5, "uart2"), /* RX */ 235 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 2)), 236 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), 237 + SUNXI_FUNCTION(0x0, "gpio_in"), 238 + SUNXI_FUNCTION(0x1, "gpio_out"), 239 + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ 240 + SUNXI_FUNCTION(0x3, "lvds0"), /* V1N */ 241 + SUNXI_FUNCTION(0x4, "dsi"), /* D1N */ 242 + SUNXI_FUNCTION(0x5, "uart2"), /* RTS */ 243 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 3)), 244 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), 245 + SUNXI_FUNCTION(0x0, "gpio_in"), 246 + SUNXI_FUNCTION(0x1, "gpio_out"), 247 + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ 248 + SUNXI_FUNCTION(0x3, "lvds0"), /* V2P */ 249 + SUNXI_FUNCTION(0x4, "dsi"), /* CKP */ 250 + SUNXI_FUNCTION(0x5, "uart2"), /* CTS */ 251 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 4)), 252 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), 253 + SUNXI_FUNCTION(0x0, "gpio_in"), 254 + SUNXI_FUNCTION(0x1, "gpio_out"), 255 + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ 256 + SUNXI_FUNCTION(0x3, "lvds0"), /* V2N */ 257 + SUNXI_FUNCTION(0x4, "dsi"), /* CKN */ 258 + SUNXI_FUNCTION(0x5, "uart5"), /* TX */ 259 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 5)), 260 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), 261 + SUNXI_FUNCTION(0x0, "gpio_in"), 262 + SUNXI_FUNCTION(0x1, "gpio_out"), 263 + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ 264 + SUNXI_FUNCTION(0x3, "lvds0"), /* CKP */ 265 + SUNXI_FUNCTION(0x4, "dsi"), /* D2P */ 266 + SUNXI_FUNCTION(0x5, "uart5"), /* RX */ 267 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 6)), 268 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), 269 + SUNXI_FUNCTION(0x0, "gpio_in"), 270 + SUNXI_FUNCTION(0x1, "gpio_out"), 271 + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ 272 + SUNXI_FUNCTION(0x3, "lvds0"), /* CKN */ 273 + SUNXI_FUNCTION(0x4, "dsi"), /* D2N */ 274 + SUNXI_FUNCTION(0x5, "uart4"), /* TX */ 275 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 7)), 276 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), 277 + SUNXI_FUNCTION(0x0, "gpio_in"), 278 + SUNXI_FUNCTION(0x1, "gpio_out"), 279 + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ 280 + SUNXI_FUNCTION(0x3, "lvds0"), /* V3P */ 281 + SUNXI_FUNCTION(0x4, "dsi"), /* D3P */ 282 + SUNXI_FUNCTION(0x5, "uart4"), /* RX */ 283 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 8)), 284 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), 285 + SUNXI_FUNCTION(0x0, "gpio_in"), 286 + SUNXI_FUNCTION(0x1, "gpio_out"), 287 + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ 288 + SUNXI_FUNCTION(0x3, "lvds0"), /* V3N */ 289 + SUNXI_FUNCTION(0x4, "dsi"), /* D3N */ 290 + SUNXI_FUNCTION(0x5, "pwm6"), 291 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 9)), 292 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), 293 + SUNXI_FUNCTION(0x0, "gpio_in"), 294 + SUNXI_FUNCTION(0x1, "gpio_out"), 295 + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ 296 + SUNXI_FUNCTION(0x3, "lvds1"), /* V0P */ 297 + SUNXI_FUNCTION(0x4, "spi1"), /* CS0 */ 298 + SUNXI_FUNCTION(0x5, "uart3"), /* TX */ 299 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 10)), 300 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), 301 + SUNXI_FUNCTION(0x0, "gpio_in"), 302 + SUNXI_FUNCTION(0x1, "gpio_out"), 303 + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ 304 + SUNXI_FUNCTION(0x3, "lvds1"), /* V0N */ 305 + SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ 306 + SUNXI_FUNCTION(0x5, "uart3"), /* RX */ 307 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 11)), 308 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), 309 + SUNXI_FUNCTION(0x0, "gpio_in"), 310 + SUNXI_FUNCTION(0x1, "gpio_out"), 311 + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ 312 + SUNXI_FUNCTION(0x3, "lvds1"), /* V1P */ 313 + SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ 314 + SUNXI_FUNCTION(0x5, "i2c0"), /* SDA */ 315 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 12)), 316 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), 317 + SUNXI_FUNCTION(0x0, "gpio_in"), 318 + SUNXI_FUNCTION(0x1, "gpio_out"), 319 + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ 320 + SUNXI_FUNCTION(0x3, "lvds1"), /* V1N */ 321 + SUNXI_FUNCTION(0x4, "spi1"), /* MISO */ 322 + SUNXI_FUNCTION(0x5, "uart3"), /* RTS */ 323 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 13)), 324 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), 325 + SUNXI_FUNCTION(0x0, "gpio_in"), 326 + SUNXI_FUNCTION(0x1, "gpio_out"), 327 + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ 328 + SUNXI_FUNCTION(0x3, "lvds1"), /* V2P */ 329 + SUNXI_FUNCTION(0x4, "spi1"), /* HOLD */ 330 + SUNXI_FUNCTION(0x5, "uart3"), /* CTS */ 331 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 14)), 332 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), 333 + SUNXI_FUNCTION(0x0, "gpio_in"), 334 + SUNXI_FUNCTION(0x1, "gpio_out"), 335 + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ 336 + SUNXI_FUNCTION(0x3, "lvds1"), /* V2N */ 337 + SUNXI_FUNCTION(0x4, "spi1"), /* WP */ 338 + SUNXI_FUNCTION(0x5, "ir"), /* RX */ 339 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 15)), 340 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), 341 + SUNXI_FUNCTION(0x0, "gpio_in"), 342 + SUNXI_FUNCTION(0x1, "gpio_out"), 343 + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ 344 + SUNXI_FUNCTION(0x3, "lvds1"), /* CKP */ 345 + SUNXI_FUNCTION(0x4, "dmic"), /* DATA3 */ 346 + SUNXI_FUNCTION(0x5, "pwm0"), 347 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 16)), 348 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), 349 + SUNXI_FUNCTION(0x0, "gpio_in"), 350 + SUNXI_FUNCTION(0x1, "gpio_out"), 351 + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ 352 + SUNXI_FUNCTION(0x3, "lvds1"), /* CKN */ 353 + SUNXI_FUNCTION(0x4, "dmic"), /* DATA2 */ 354 + SUNXI_FUNCTION(0x5, "pwm1"), 355 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 17)), 356 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), 357 + SUNXI_FUNCTION(0x0, "gpio_in"), 358 + SUNXI_FUNCTION(0x1, "gpio_out"), 359 + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ 360 + SUNXI_FUNCTION(0x3, "lvds1"), /* V3P */ 361 + SUNXI_FUNCTION(0x4, "dmic"), /* DATA1 */ 362 + SUNXI_FUNCTION(0x5, "pwm2"), 363 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 18)), 364 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), 365 + SUNXI_FUNCTION(0x0, "gpio_in"), 366 + SUNXI_FUNCTION(0x1, "gpio_out"), 367 + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ 368 + SUNXI_FUNCTION(0x3, "lvds1"), /* V3N */ 369 + SUNXI_FUNCTION(0x4, "dmic"), /* DATA0 */ 370 + SUNXI_FUNCTION(0x5, "pwm3"), 371 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 19)), 372 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), 373 + SUNXI_FUNCTION(0x0, "gpio_in"), 374 + SUNXI_FUNCTION(0x1, "gpio_out"), 375 + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ 376 + SUNXI_FUNCTION(0x3, "i2c2"), /* SCK */ 377 + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */ 378 + SUNXI_FUNCTION(0x5, "pwm4"), 379 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 20)), 380 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), 381 + SUNXI_FUNCTION(0x0, "gpio_in"), 382 + SUNXI_FUNCTION(0x1, "gpio_out"), 383 + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ 384 + SUNXI_FUNCTION(0x3, "i2c2"), /* SDA */ 385 + SUNXI_FUNCTION(0x4, "uart1"), /* TX */ 386 + SUNXI_FUNCTION(0x5, "pwm5"), 387 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 21)), 388 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), 389 + SUNXI_FUNCTION(0x0, "gpio_in"), 390 + SUNXI_FUNCTION(0x1, "gpio_out"), 391 + SUNXI_FUNCTION(0x2, "spdif"), /* OUT */ 392 + SUNXI_FUNCTION(0x3, "ir"), /* RX */ 393 + SUNXI_FUNCTION(0x4, "uart1"), /* RX */ 394 + SUNXI_FUNCTION(0x5, "pwm7"), 395 + SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 22)), 396 + /* PE */ 397 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), 398 + SUNXI_FUNCTION(0x0, "gpio_in"), 399 + SUNXI_FUNCTION(0x1, "gpio_out"), 400 + SUNXI_FUNCTION(0x2, "ncsi0"), /* HSYNC */ 401 + SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ 402 + SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */ 403 + SUNXI_FUNCTION(0x5, "lcd0"), /* HSYNC */ 404 + SUNXI_FUNCTION(0x8, "emac"), /* RXCTL/CRS_DV */ 405 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 0)), 406 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), 407 + SUNXI_FUNCTION(0x0, "gpio_in"), 408 + SUNXI_FUNCTION(0x1, "gpio_out"), 409 + SUNXI_FUNCTION(0x2, "ncsi0"), /* VSYNC */ 410 + SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ 411 + SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */ 412 + SUNXI_FUNCTION(0x5, "lcd0"), /* VSYNC */ 413 + SUNXI_FUNCTION(0x8, "emac"), /* RXD0 */ 414 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 1)), 415 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), 416 + SUNXI_FUNCTION(0x0, "gpio_in"), 417 + SUNXI_FUNCTION(0x1, "gpio_out"), 418 + SUNXI_FUNCTION(0x2, "ncsi0"), /* PCLK */ 419 + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ 420 + SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */ 421 + SUNXI_FUNCTION(0x5, "clk"), /* FANOUT0 */ 422 + SUNXI_FUNCTION(0x6, "uart0"), /* TX */ 423 + SUNXI_FUNCTION(0x8, "emac"), /* RXD1 */ 424 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 2)), 425 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), 426 + SUNXI_FUNCTION(0x0, "gpio_in"), 427 + SUNXI_FUNCTION(0x1, "gpio_out"), 428 + SUNXI_FUNCTION(0x2, "ncsi0"), /* MCLK */ 429 + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ 430 + SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */ 431 + SUNXI_FUNCTION(0x5, "clk"), /* FANOUT1 */ 432 + SUNXI_FUNCTION(0x6, "uart0"), /* RX */ 433 + SUNXI_FUNCTION(0x8, "emac"), /* TXCK */ 434 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 3)), 435 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), 436 + SUNXI_FUNCTION(0x0, "gpio_in"), 437 + SUNXI_FUNCTION(0x1, "gpio_out"), 438 + SUNXI_FUNCTION(0x2, "ncsi0"), /* D0 */ 439 + SUNXI_FUNCTION(0x3, "uart4"), /* TX */ 440 + SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */ 441 + SUNXI_FUNCTION(0x5, "clk"), /* FANOUT2 */ 442 + SUNXI_FUNCTION(0x6, "d_jtag"), /* MS */ 443 + SUNXI_FUNCTION(0x7, "r_jtag"), /* MS */ 444 + SUNXI_FUNCTION(0x8, "emac"), /* TXD0 */ 445 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 4)), 446 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), 447 + SUNXI_FUNCTION(0x0, "gpio_in"), 448 + SUNXI_FUNCTION(0x1, "gpio_out"), 449 + SUNXI_FUNCTION(0x2, "ncsi0"), /* D1 */ 450 + SUNXI_FUNCTION(0x3, "uart4"), /* RX */ 451 + SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */ 452 + SUNXI_FUNCTION(0x5, "ledc"), 453 + SUNXI_FUNCTION(0x6, "d_jtag"), /* DI */ 454 + SUNXI_FUNCTION(0x7, "r_jtag"), /* DI */ 455 + SUNXI_FUNCTION(0x8, "emac"), /* TXD1 */ 456 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 5)), 457 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), 458 + SUNXI_FUNCTION(0x0, "gpio_in"), 459 + SUNXI_FUNCTION(0x1, "gpio_out"), 460 + SUNXI_FUNCTION(0x2, "ncsi0"), /* D2 */ 461 + SUNXI_FUNCTION(0x3, "uart5"), /* TX */ 462 + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */ 463 + SUNXI_FUNCTION(0x5, "spdif"), /* IN */ 464 + SUNXI_FUNCTION(0x6, "d_jtag"), /* DO */ 465 + SUNXI_FUNCTION(0x7, "r_jtag"), /* DO */ 466 + SUNXI_FUNCTION(0x8, "emac"), /* TXCTL/TXEN */ 467 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 6)), 468 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), 469 + SUNXI_FUNCTION(0x0, "gpio_in"), 470 + SUNXI_FUNCTION(0x1, "gpio_out"), 471 + SUNXI_FUNCTION(0x2, "ncsi0"), /* D3 */ 472 + SUNXI_FUNCTION(0x3, "uart5"), /* RX */ 473 + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */ 474 + SUNXI_FUNCTION(0x5, "spdif"), /* OUT */ 475 + SUNXI_FUNCTION(0x6, "d_jtag"), /* CK */ 476 + SUNXI_FUNCTION(0x7, "r_jtag"), /* CK */ 477 + SUNXI_FUNCTION(0x8, "emac"), /* CK */ 478 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 7)), 479 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), 480 + SUNXI_FUNCTION(0x0, "gpio_in"), 481 + SUNXI_FUNCTION(0x1, "gpio_out"), 482 + SUNXI_FUNCTION(0x2, "ncsi0"), /* D4 */ 483 + SUNXI_FUNCTION(0x3, "uart1"), /* RTS */ 484 + SUNXI_FUNCTION(0x4, "pwm2"), 485 + SUNXI_FUNCTION(0x5, "uart3"), /* TX */ 486 + SUNXI_FUNCTION(0x6, "jtag"), /* MS */ 487 + SUNXI_FUNCTION(0x8, "emac"), /* MDC */ 488 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 8)), 489 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), 490 + SUNXI_FUNCTION(0x0, "gpio_in"), 491 + SUNXI_FUNCTION(0x1, "gpio_out"), 492 + SUNXI_FUNCTION(0x2, "ncsi0"), /* D5 */ 493 + SUNXI_FUNCTION(0x3, "uart1"), /* CTS */ 494 + SUNXI_FUNCTION(0x4, "pwm3"), 495 + SUNXI_FUNCTION(0x5, "uart3"), /* RX */ 496 + SUNXI_FUNCTION(0x6, "jtag"), /* DI */ 497 + SUNXI_FUNCTION(0x8, "emac"), /* MDIO */ 498 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 9)), 499 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), 500 + SUNXI_FUNCTION(0x0, "gpio_in"), 501 + SUNXI_FUNCTION(0x1, "gpio_out"), 502 + SUNXI_FUNCTION(0x2, "ncsi0"), /* D6 */ 503 + SUNXI_FUNCTION(0x3, "uart1"), /* TX */ 504 + SUNXI_FUNCTION(0x4, "pwm4"), 505 + SUNXI_FUNCTION(0x5, "ir"), /* RX */ 506 + SUNXI_FUNCTION(0x6, "jtag"), /* DO */ 507 + SUNXI_FUNCTION(0x8, "emac"), /* EPHY-25M */ 508 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 10)), 509 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), 510 + SUNXI_FUNCTION(0x0, "gpio_in"), 511 + SUNXI_FUNCTION(0x1, "gpio_out"), 512 + SUNXI_FUNCTION(0x2, "ncsi0"), /* D7 */ 513 + SUNXI_FUNCTION(0x3, "uart1"), /* RX */ 514 + SUNXI_FUNCTION(0x4, "i2s0_dout"), /* DOUT3 */ 515 + SUNXI_FUNCTION(0x5, "i2s0_din"), /* DIN3 */ 516 + SUNXI_FUNCTION(0x6, "jtag"), /* CK */ 517 + SUNXI_FUNCTION(0x8, "emac"), /* TXD2 */ 518 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 11)), 519 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), 520 + SUNXI_FUNCTION(0x0, "gpio_in"), 521 + SUNXI_FUNCTION(0x1, "gpio_out"), 522 + SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */ 523 + SUNXI_FUNCTION(0x3, "ncsi0"), /* FIELD */ 524 + SUNXI_FUNCTION(0x4, "i2s0_dout"), /* DOUT2 */ 525 + SUNXI_FUNCTION(0x5, "i2s0_din"), /* DIN2 */ 526 + SUNXI_FUNCTION(0x8, "emac"), /* TXD3 */ 527 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 12)), 528 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), 529 + SUNXI_FUNCTION(0x0, "gpio_in"), 530 + SUNXI_FUNCTION(0x1, "gpio_out"), 531 + SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */ 532 + SUNXI_FUNCTION(0x3, "pwm5"), 533 + SUNXI_FUNCTION(0x4, "i2s0_dout"), /* DOUT0 */ 534 + SUNXI_FUNCTION(0x5, "i2s0_din"), /* DIN1 */ 535 + SUNXI_FUNCTION(0x6, "dmic"), /* DATA3 */ 536 + SUNXI_FUNCTION(0x8, "emac"), /* RXD2 */ 537 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 13)), 538 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), 539 + SUNXI_FUNCTION(0x0, "gpio_in"), 540 + SUNXI_FUNCTION(0x1, "gpio_out"), 541 + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ 542 + SUNXI_FUNCTION(0x3, "d_jtag"), /* MS */ 543 + SUNXI_FUNCTION(0x4, "i2s0_dout"), /* DOUT1 */ 544 + SUNXI_FUNCTION(0x5, "i2s0_din"), /* DIN0 */ 545 + SUNXI_FUNCTION(0x6, "dmic"), /* DATA2 */ 546 + SUNXI_FUNCTION(0x8, "emac"), /* RXD3 */ 547 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 14)), 548 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), 549 + SUNXI_FUNCTION(0x0, "gpio_in"), 550 + SUNXI_FUNCTION(0x1, "gpio_out"), 551 + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ 552 + SUNXI_FUNCTION(0x3, "d_jtag"), /* DI */ 553 + SUNXI_FUNCTION(0x4, "pwm6"), 554 + SUNXI_FUNCTION(0x5, "i2s0"), /* LRCK */ 555 + SUNXI_FUNCTION(0x6, "dmic"), /* DATA1 */ 556 + SUNXI_FUNCTION(0x8, "emac"), /* RXCK */ 557 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 15)), 558 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), 559 + SUNXI_FUNCTION(0x0, "gpio_in"), 560 + SUNXI_FUNCTION(0x1, "gpio_out"), 561 + SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ 562 + SUNXI_FUNCTION(0x3, "d_jtag"), /* DO */ 563 + SUNXI_FUNCTION(0x4, "pwm7"), 564 + SUNXI_FUNCTION(0x5, "i2s0"), /* BCLK */ 565 + SUNXI_FUNCTION(0x6, "dmic"), /* DATA0 */ 566 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 16)), 567 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), 568 + SUNXI_FUNCTION(0x0, "gpio_in"), 569 + SUNXI_FUNCTION(0x1, "gpio_out"), 570 + SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ 571 + SUNXI_FUNCTION(0x3, "d_jtag"), /* CK */ 572 + SUNXI_FUNCTION(0x4, "ir"), /* TX */ 573 + SUNXI_FUNCTION(0x5, "i2s0"), /* MCLK */ 574 + SUNXI_FUNCTION(0x6, "dmic"), /* CLK */ 575 + SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 17)), 576 + /* PF */ 577 + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 578 + SUNXI_FUNCTION(0x0, "gpio_in"), 579 + SUNXI_FUNCTION(0x1, "gpio_out"), 580 + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 581 + SUNXI_FUNCTION(0x3, "jtag"), /* MS */ 582 + SUNXI_FUNCTION(0x4, "r_jtag"), /* MS */ 583 + SUNXI_FUNCTION(0x5, "i2s2_dout"), /* DOUT1 */ 584 + SUNXI_FUNCTION(0x6, "i2s2_din"), /* DIN0 */ 585 + SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 0)), 586 + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), 587 + SUNXI_FUNCTION(0x0, "gpio_in"), 588 + SUNXI_FUNCTION(0x1, "gpio_out"), 589 + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 590 + SUNXI_FUNCTION(0x3, "jtag"), /* DI */ 591 + SUNXI_FUNCTION(0x4, "r_jtag"), /* DI */ 592 + SUNXI_FUNCTION(0x5, "i2s2_dout"), /* DOUT0 */ 593 + SUNXI_FUNCTION(0x6, "i2s2_din"), /* DIN1 */ 594 + SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 1)), 595 + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), 596 + SUNXI_FUNCTION(0x0, "gpio_in"), 597 + SUNXI_FUNCTION(0x1, "gpio_out"), 598 + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 599 + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ 600 + SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */ 601 + SUNXI_FUNCTION(0x5, "ledc"), 602 + SUNXI_FUNCTION(0x6, "spdif"), /* IN */ 603 + SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 2)), 604 + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), 605 + SUNXI_FUNCTION(0x0, "gpio_in"), 606 + SUNXI_FUNCTION(0x1, "gpio_out"), 607 + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 608 + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ 609 + SUNXI_FUNCTION(0x4, "r_jtag"), /* DO */ 610 + SUNXI_FUNCTION(0x5, "i2s2"), /* BCLK */ 611 + SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 3)), 612 + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), 613 + SUNXI_FUNCTION(0x0, "gpio_in"), 614 + SUNXI_FUNCTION(0x1, "gpio_out"), 615 + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 616 + SUNXI_FUNCTION(0x3, "uart0"), /* RX */ 617 + SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */ 618 + SUNXI_FUNCTION(0x5, "pwm6"), 619 + SUNXI_FUNCTION(0x6, "ir"), /* TX */ 620 + SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 4)), 621 + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), 622 + SUNXI_FUNCTION(0x0, "gpio_in"), 623 + SUNXI_FUNCTION(0x1, "gpio_out"), 624 + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 625 + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ 626 + SUNXI_FUNCTION(0x4, "r_jtag"), /* CK */ 627 + SUNXI_FUNCTION(0x5, "i2s2"), /* LRCK */ 628 + SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 5)), 629 + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), 630 + SUNXI_FUNCTION(0x0, "gpio_in"), 631 + SUNXI_FUNCTION(0x1, "gpio_out"), 632 + SUNXI_FUNCTION(0x3, "spdif"), /* OUT */ 633 + SUNXI_FUNCTION(0x4, "ir"), /* RX */ 634 + SUNXI_FUNCTION(0x5, "i2s2"), /* MCLK */ 635 + SUNXI_FUNCTION(0x6, "pwm5"), 636 + SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 6)), 637 + /* PG */ 638 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 639 + SUNXI_FUNCTION(0x0, "gpio_in"), 640 + SUNXI_FUNCTION(0x1, "gpio_out"), 641 + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 642 + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 643 + SUNXI_FUNCTION(0x4, "emac"), /* RXCTRL/CRS_DV */ 644 + SUNXI_FUNCTION(0x5, "pwm7"), 645 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 0)), 646 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 647 + SUNXI_FUNCTION(0x0, "gpio_in"), 648 + SUNXI_FUNCTION(0x1, "gpio_out"), 649 + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 650 + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 651 + SUNXI_FUNCTION(0x4, "emac"), /* RXD0 */ 652 + SUNXI_FUNCTION(0x5, "pwm6"), 653 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 1)), 654 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 655 + SUNXI_FUNCTION(0x0, "gpio_in"), 656 + SUNXI_FUNCTION(0x1, "gpio_out"), 657 + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ 658 + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ 659 + SUNXI_FUNCTION(0x4, "emac"), /* RXD1 */ 660 + SUNXI_FUNCTION(0x5, "uart4"), /* TX */ 661 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 2)), 662 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 663 + SUNXI_FUNCTION(0x0, "gpio_in"), 664 + SUNXI_FUNCTION(0x1, "gpio_out"), 665 + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ 666 + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 667 + SUNXI_FUNCTION(0x4, "emac"), /* TXCK */ 668 + SUNXI_FUNCTION(0x5, "uart4"), /* RX */ 669 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 3)), 670 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), 671 + SUNXI_FUNCTION(0x0, "gpio_in"), 672 + SUNXI_FUNCTION(0x1, "gpio_out"), 673 + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ 674 + SUNXI_FUNCTION(0x3, "uart5"), /* TX */ 675 + SUNXI_FUNCTION(0x4, "emac"), /* TXD0 */ 676 + SUNXI_FUNCTION(0x5, "pwm5"), 677 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 4)), 678 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), 679 + SUNXI_FUNCTION(0x0, "gpio_in"), 680 + SUNXI_FUNCTION(0x1, "gpio_out"), 681 + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ 682 + SUNXI_FUNCTION(0x3, "uart5"), /* RX */ 683 + SUNXI_FUNCTION(0x4, "emac"), /* TXD1 */ 684 + SUNXI_FUNCTION(0x5, "pwm4"), 685 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 5)), 686 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), 687 + SUNXI_FUNCTION(0x0, "gpio_in"), 688 + SUNXI_FUNCTION(0x1, "gpio_out"), 689 + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ 690 + SUNXI_FUNCTION(0x3, "i2c2"), /* SCK */ 691 + SUNXI_FUNCTION(0x4, "emac"), /* TXD2 */ 692 + SUNXI_FUNCTION(0x5, "pwm1"), 693 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 6)), 694 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), 695 + SUNXI_FUNCTION(0x0, "gpio_in"), 696 + SUNXI_FUNCTION(0x1, "gpio_out"), 697 + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ 698 + SUNXI_FUNCTION(0x3, "i2c2"), /* SDA */ 699 + SUNXI_FUNCTION(0x4, "emac"), /* TXD3 */ 700 + SUNXI_FUNCTION(0x5, "spdif"), /* IN */ 701 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 7)), 702 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), 703 + SUNXI_FUNCTION(0x0, "gpio_in"), 704 + SUNXI_FUNCTION(0x1, "gpio_out"), 705 + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ 706 + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ 707 + SUNXI_FUNCTION(0x4, "emac"), /* RXD2 */ 708 + SUNXI_FUNCTION(0x5, "uart3"), /* TX */ 709 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 8)), 710 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), 711 + SUNXI_FUNCTION(0x0, "gpio_in"), 712 + SUNXI_FUNCTION(0x1, "gpio_out"), 713 + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ 714 + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ 715 + SUNXI_FUNCTION(0x4, "emac"), /* RXD3 */ 716 + SUNXI_FUNCTION(0x5, "uart3"), /* RX */ 717 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 9)), 718 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), 719 + SUNXI_FUNCTION(0x0, "gpio_in"), 720 + SUNXI_FUNCTION(0x1, "gpio_out"), 721 + SUNXI_FUNCTION(0x2, "pwm3"), 722 + SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */ 723 + SUNXI_FUNCTION(0x4, "emac"), /* RXCK */ 724 + SUNXI_FUNCTION(0x5, "clk"), /* FANOUT0 */ 725 + SUNXI_FUNCTION(0x6, "ir"), /* RX */ 726 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 10)), 727 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), 728 + SUNXI_FUNCTION(0x0, "gpio_in"), 729 + SUNXI_FUNCTION(0x1, "gpio_out"), 730 + SUNXI_FUNCTION(0x2, "i2s1"), /* MCLK */ 731 + SUNXI_FUNCTION(0x3, "i2c3"), /* SDA */ 732 + SUNXI_FUNCTION(0x4, "emac"), /* EPHY-25M */ 733 + SUNXI_FUNCTION(0x5, "clk"), /* FANOUT1 */ 734 + SUNXI_FUNCTION(0x6, "tcon"), /* TRIG0 */ 735 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 11)), 736 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), 737 + SUNXI_FUNCTION(0x0, "gpio_in"), 738 + SUNXI_FUNCTION(0x1, "gpio_out"), 739 + SUNXI_FUNCTION(0x2, "i2s1"), /* LRCK */ 740 + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ 741 + SUNXI_FUNCTION(0x4, "emac"), /* TXCTL/TXEN */ 742 + SUNXI_FUNCTION(0x5, "clk"), /* FANOUT2 */ 743 + SUNXI_FUNCTION(0x6, "pwm0"), 744 + SUNXI_FUNCTION(0x7, "uart1"), /* TX */ 745 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 12)), 746 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), 747 + SUNXI_FUNCTION(0x0, "gpio_in"), 748 + SUNXI_FUNCTION(0x1, "gpio_out"), 749 + SUNXI_FUNCTION(0x2, "i2s1"), /* BCLK */ 750 + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ 751 + SUNXI_FUNCTION(0x4, "emac"), /* CLKIN/RXER */ 752 + SUNXI_FUNCTION(0x5, "pwm2"), 753 + SUNXI_FUNCTION(0x6, "ledc"), 754 + SUNXI_FUNCTION(0x7, "uart1"), /* RX */ 755 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 13)), 756 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), 757 + SUNXI_FUNCTION(0x0, "gpio_in"), 758 + SUNXI_FUNCTION(0x1, "gpio_out"), 759 + SUNXI_FUNCTION(0x2, "i2s1_din"), /* DIN0 */ 760 + SUNXI_FUNCTION(0x3, "i2c2"), /* SCK */ 761 + SUNXI_FUNCTION(0x4, "emac"), /* MDC */ 762 + SUNXI_FUNCTION(0x5, "i2s1_dout"), /* DOUT1 */ 763 + SUNXI_FUNCTION(0x6, "spi0"), /* WP */ 764 + SUNXI_FUNCTION(0x7, "uart1"), /* RTS */ 765 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 14)), 766 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15), 767 + SUNXI_FUNCTION(0x0, "gpio_in"), 768 + SUNXI_FUNCTION(0x1, "gpio_out"), 769 + SUNXI_FUNCTION(0x2, "i2s1_dout"), /* DOUT0 */ 770 + SUNXI_FUNCTION(0x3, "i2c2"), /* SDA */ 771 + SUNXI_FUNCTION(0x4, "emac"), /* MDIO */ 772 + SUNXI_FUNCTION(0x5, "i2s1_din"), /* DIN1 */ 773 + SUNXI_FUNCTION(0x6, "spi0"), /* HOLD */ 774 + SUNXI_FUNCTION(0x7, "uart1"), /* CTS */ 775 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 15)), 776 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16), 777 + SUNXI_FUNCTION(0x0, "gpio_in"), 778 + SUNXI_FUNCTION(0x1, "gpio_out"), 779 + SUNXI_FUNCTION(0x2, "ir"), /* RX */ 780 + SUNXI_FUNCTION(0x3, "tcon"), /* TRIG0 */ 781 + SUNXI_FUNCTION(0x4, "pwm5"), 782 + SUNXI_FUNCTION(0x5, "clk"), /* FANOUT2 */ 783 + SUNXI_FUNCTION(0x6, "spdif"), /* IN */ 784 + SUNXI_FUNCTION(0x7, "ledc"), 785 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 16)), 786 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17), 787 + SUNXI_FUNCTION(0x0, "gpio_in"), 788 + SUNXI_FUNCTION(0x1, "gpio_out"), 789 + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ 790 + SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */ 791 + SUNXI_FUNCTION(0x4, "pwm7"), 792 + SUNXI_FUNCTION(0x5, "clk"), /* FANOUT0 */ 793 + SUNXI_FUNCTION(0x6, "ir"), /* TX */ 794 + SUNXI_FUNCTION(0x7, "uart0"), /* TX */ 795 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 17)), 796 + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18), 797 + SUNXI_FUNCTION(0x0, "gpio_in"), 798 + SUNXI_FUNCTION(0x1, "gpio_out"), 799 + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ 800 + SUNXI_FUNCTION(0x3, "i2c3"), /* SDA */ 801 + SUNXI_FUNCTION(0x4, "pwm6"), 802 + SUNXI_FUNCTION(0x5, "clk"), /* FANOUT1 */ 803 + SUNXI_FUNCTION(0x6, "spdif"), /* OUT */ 804 + SUNXI_FUNCTION(0x7, "uart0"), /* RX */ 805 + SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 18)), 806 + }; 807 + 808 + static const unsigned int d1_irq_bank_map[] = { 1, 2, 3, 4, 5, 6 }; 809 + 810 + static const struct sunxi_pinctrl_desc d1_pinctrl_data = { 811 + .pins = d1_pins, 812 + .npins = ARRAY_SIZE(d1_pins), 813 + .irq_banks = ARRAY_SIZE(d1_irq_bank_map), 814 + .irq_bank_map = d1_irq_bank_map, 815 + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL, 816 + }; 817 + 818 + static int d1_pinctrl_probe(struct platform_device *pdev) 819 + { 820 + unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); 821 + 822 + return sunxi_pinctrl_init_with_variant(pdev, &d1_pinctrl_data, variant); 823 + } 824 + 825 + static const struct of_device_id d1_pinctrl_match[] = { 826 + { 827 + .compatible = "allwinner,sun20i-d1-pinctrl", 828 + .data = (void *)PINCTRL_SUN20I_D1 829 + }, 830 + {} 831 + }; 832 + 833 + static struct platform_driver d1_pinctrl_driver = { 834 + .probe = d1_pinctrl_probe, 835 + .driver = { 836 + .name = "sun20i-d1-pinctrl", 837 + .of_match_table = d1_pinctrl_match, 838 + }, 839 + }; 840 + builtin_platform_driver(d1_pinctrl_driver);
+11 -5
drivers/pinctrl/sunxi/pinctrl-sunxi.c
··· 1297 1297 1298 1298 /* 1299 1299 * Find an upper bound for the maximum number of functions: in 1300 - * the worst case we have gpio_in, gpio_out, irq and up to four 1300 + * the worst case we have gpio_in, gpio_out, irq and up to seven 1301 1301 * special functions per pin, plus one entry for the sentinel. 1302 1302 * We'll reallocate that later anyway. 1303 1303 */ 1304 - pctl->functions = kcalloc(4 * pctl->ngroups + 4, 1304 + pctl->functions = kcalloc(7 * pctl->ngroups + 4, 1305 1305 sizeof(*pctl->functions), 1306 1306 GFP_KERNEL); 1307 1307 if (!pctl->functions) ··· 1494 1494 pctl->dev = &pdev->dev; 1495 1495 pctl->desc = desc; 1496 1496 pctl->variant = variant; 1497 - pctl->bank_mem_size = BANK_MEM_SIZE; 1498 - pctl->pull_regs_offset = PULL_REGS_OFFSET; 1499 - pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH; 1497 + if (pctl->variant >= PINCTRL_SUN20I_D1) { 1498 + pctl->bank_mem_size = D1_BANK_MEM_SIZE; 1499 + pctl->pull_regs_offset = D1_PULL_REGS_OFFSET; 1500 + pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH; 1501 + } else { 1502 + pctl->bank_mem_size = BANK_MEM_SIZE; 1503 + pctl->pull_regs_offset = PULL_REGS_OFFSET; 1504 + pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH; 1505 + } 1500 1506 1501 1507 pctl->irq_array = devm_kcalloc(&pdev->dev, 1502 1508 IRQ_PER_BANK * pctl->desc->irq_banks,
+6
drivers/pinctrl/sunxi/pinctrl-sunxi.h
··· 44 44 #define PULL_REGS_OFFSET 0x1c 45 45 #define PULL_FIELD_WIDTH 2 46 46 47 + #define D1_BANK_MEM_SIZE 0x30 48 + #define D1_DLEVEL_FIELD_WIDTH 4 49 + #define D1_PULL_REGS_OFFSET 0x24 50 + 47 51 #define PINS_PER_BANK 32 48 52 49 53 #define IRQ_PER_BANK 32 ··· 92 88 #define PINCTRL_SUN8I_R40 BIT(8) 93 89 #define PINCTRL_SUN8I_V3 BIT(9) 94 90 #define PINCTRL_SUN8I_V3S BIT(10) 91 + /* Variants below here have an updated register layout. */ 92 + #define PINCTRL_SUN20I_D1 BIT(11) 95 93 96 94 #define PIO_POW_MOD_SEL_REG 0x340 97 95 #define PIO_POW_MOD_CTL_REG 0x344