commit 055d8d9eae35ac1edb97fcf70f357cea227bf3b2 · tjh.dev/kernel

+3 -1

drivers/i2c/busses/i2c-designware-master.c

··· 34 34 35 35 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev) 36 36 { 37 - u32 ic_clk = i2c_dw_clk_rate(dev); 38 37 const char *mode_str, *fp_str = ""; 39 38 u32 comp_param1; 40 39 u32 sda_falling_time, scl_falling_time; 41 40 struct i2c_timings *t = &dev->timings; 41 + u32 ic_clk; 42 42 int ret; 43 43 44 44 ret = i2c_dw_acquire_lock(dev); ··· 53 53 54 54 /* Calculate SCL timing parameters for standard mode if not set */ 55 55 if (!dev->ss_hcnt || !dev->ss_lcnt) { 56 + ic_clk = i2c_dw_clk_rate(dev); 56 57 dev->ss_hcnt = 57 58 i2c_dw_scl_hcnt(ic_clk, 58 59 4000, /* tHD;STA = tHIGH = 4.0 us */ ··· 90 89 * needed also in high speed mode. 91 90 */ 92 91 if (!dev->fs_hcnt || !dev->fs_lcnt) { 92 + ic_clk = i2c_dw_clk_rate(dev); 93 93 dev->fs_hcnt = 94 94 i2c_dw_scl_hcnt(ic_clk, 95 95 600, /* tHD;STA = tHIGH = 0.6 us */

+1 -1

drivers/i2c/busses/i2c-isch.c

··· 164 164 * run ~75 kHz instead which should do no harm. 165 165 */ 166 166 dev_notice(&sch_adapter.dev, 167 - "Clock divider unitialized. Setting defaults\n"); 167 + "Clock divider uninitialized. Setting defaults\n"); 168 168 outw(backbone_speed / (4 * 100), SMBHSTCLK); 169 169 } 170 170

+18 -4

drivers/i2c/busses/i2c-qcom-geni.c

··· 367 367 dma_addr_t rx_dma; 368 368 enum geni_se_xfer_mode mode; 369 369 unsigned long time_left = XFER_TIMEOUT; 370 + void *dma_buf; 370 371 371 372 gi2c->cur = msg; 372 - mode = msg->len > 32 ? GENI_SE_DMA : GENI_SE_FIFO; 373 + mode = GENI_SE_FIFO; 374 + dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 375 + if (dma_buf) 376 + mode = GENI_SE_DMA; 377 + 373 378 geni_se_select_mode(&gi2c->se, mode); 374 379 writel_relaxed(msg->len, gi2c->se.base + SE_I2C_RX_TRANS_LEN); 375 380 geni_se_setup_m_cmd(&gi2c->se, I2C_READ, m_param); 376 381 if (mode == GENI_SE_DMA) { 377 382 int ret; 378 383 379 - ret = geni_se_rx_dma_prep(&gi2c->se, msg->buf, msg->len, 384 + ret = geni_se_rx_dma_prep(&gi2c->se, dma_buf, msg->len, 380 385 &rx_dma); 381 386 if (ret) { 382 387 mode = GENI_SE_FIFO; 383 388 geni_se_select_mode(&gi2c->se, mode); 389 + i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 384 390 } 385 391 } 386 392 ··· 399 393 if (gi2c->err) 400 394 geni_i2c_rx_fsm_rst(gi2c); 401 395 geni_se_rx_dma_unprep(&gi2c->se, rx_dma, msg->len); 396 + i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err); 402 397 } 403 398 return gi2c->err; 404 399 } ··· 410 403 dma_addr_t tx_dma; 411 404 enum geni_se_xfer_mode mode; 412 405 unsigned long time_left; 406 + void *dma_buf; 413 407 414 408 gi2c->cur = msg; 415 - mode = msg->len > 32 ? GENI_SE_DMA : GENI_SE_FIFO; 409 + mode = GENI_SE_FIFO; 410 + dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 411 + if (dma_buf) 412 + mode = GENI_SE_DMA; 413 + 416 414 geni_se_select_mode(&gi2c->se, mode); 417 415 writel_relaxed(msg->len, gi2c->se.base + SE_I2C_TX_TRANS_LEN); 418 416 geni_se_setup_m_cmd(&gi2c->se, I2C_WRITE, m_param); 419 417 if (mode == GENI_SE_DMA) { 420 418 int ret; 421 419 422 - ret = geni_se_tx_dma_prep(&gi2c->se, msg->buf, msg->len, 420 + ret = geni_se_tx_dma_prep(&gi2c->se, dma_buf, msg->len, 423 421 &tx_dma); 424 422 if (ret) { 425 423 mode = GENI_SE_FIFO; 426 424 geni_se_select_mode(&gi2c->se, mode); 425 + i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 427 426 } 428 427 } 429 428 ··· 445 432 if (gi2c->err) 446 433 geni_i2c_tx_fsm_rst(gi2c); 447 434 geni_se_tx_dma_unprep(&gi2c->se, tx_dma, msg->len); 435 + i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err); 448 436 } 449 437 return gi2c->err; 450 438 }

+1

drivers/i2c/busses/i2c-scmi.c

··· 152 152 mt_params[3].type = ACPI_TYPE_INTEGER; 153 153 mt_params[3].integer.value = len; 154 154 mt_params[4].type = ACPI_TYPE_BUFFER; 155 + mt_params[4].buffer.length = len; 155 156 mt_params[4].buffer.pointer = data->block + 1; 156 157 } 157 158 break;