MIPS: Unify naming style of vendor CP0.Config6 bits

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Other vendor-defined registers use the vendor name as a prefix, not an
infix, so unify the naming style of CP0.Config6 bits.

Suggested-by: Maciej W. Rozycki" <macro@linux-mips.org>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

authored by

Huacai Chen and committed by

Thomas Bogendoerfer 5 years ago 04ef32af d23c9e06

+27 -27

5 changed files

expand all

arch

mips

include

asm

mipsregs.h

kernel

cpu-probe.c

kvm

vz.c

loongson64

cpucfg-emul.c

c-r4k.c

+14 -14

arch/mips/include/asm/mipsregs.h

··· 689 689 /* Config6 feature bits for proAptiv/P5600 */ 690 690 691 691 /* Jump register cache prediction disable */ 692 - #define MIPS_CONF6_MTI_JRCD (_ULCAST_(1) << 0) 692 + #define MTI_CONF6_JRCD (_ULCAST_(1) << 0) 693 693 /* MIPSr6 extensions enable */ 694 - #define MIPS_CONF6_MTI_R6 (_ULCAST_(1) << 2) 694 + #define MTI_CONF6_R6 (_ULCAST_(1) << 2) 695 695 /* IFU Performance Control */ 696 - #define MIPS_CONF6_MTI_IFUPERFCTL (_ULCAST_(3) << 10) 697 - #define MIPS_CONF6_MTI_SYND (_ULCAST_(1) << 13) 696 + #define MTI_CONF6_IFUPERFCTL (_ULCAST_(3) << 10) 697 + #define MTI_CONF6_SYND (_ULCAST_(1) << 13) 698 698 /* Sleep state performance counter disable */ 699 - #define MIPS_CONF6_MTI_SPCD (_ULCAST_(1) << 14) 699 + #define MTI_CONF6_SPCD (_ULCAST_(1) << 14) 700 700 /* proAptiv FTLB on/off bit */ 701 - #define MIPS_CONF6_MTI_FTLBEN (_ULCAST_(1) << 15) 701 + #define MTI_CONF6_FTLBEN (_ULCAST_(1) << 15) 702 702 /* Disable load/store bonding */ 703 - #define MIPS_CONF6_MTI_DLSB (_ULCAST_(1) << 21) 703 + #define MTI_CONF6_DLSB (_ULCAST_(1) << 21) 704 704 /* FTLB probability bits */ 705 - #define MIPS_CONF6_MTI_FTLBP_SHIFT (16) 705 + #define MTI_CONF6_FTLBP_SHIFT (16) 706 706 707 707 /* Config6 feature bits for Loongson-3 */ 708 708 709 709 /* Loongson-3 internal timer bit */ 710 - #define MIPS_CONF6_LOONGSON_INTIMER (_ULCAST_(1) << 6) 710 + #define LOONGSON_CONF6_INTIMER (_ULCAST_(1) << 6) 711 711 /* Loongson-3 external timer bit */ 712 - #define MIPS_CONF6_LOONGSON_EXTIMER (_ULCAST_(1) << 7) 712 + #define LOONGSON_CONF6_EXTIMER (_ULCAST_(1) << 7) 713 713 /* Loongson-3 SFB on/off bit, STFill in manual */ 714 - #define MIPS_CONF6_LOONGSON_SFBEN (_ULCAST_(1) << 8) 714 + #define LOONGSON_CONF6_SFBEN (_ULCAST_(1) << 8) 715 715 /* Loongson-3's LL on exclusive cacheline */ 716 - #define MIPS_CONF6_LOONGSON_LLEXC (_ULCAST_(1) << 16) 716 + #define LOONGSON_CONF6_LLEXC (_ULCAST_(1) << 16) 717 717 /* Loongson-3's SC has a random delay */ 718 - #define MIPS_CONF6_LOONGSON_SCRAND (_ULCAST_(1) << 17) 718 + #define LOONGSON_CONF6_SCRAND (_ULCAST_(1) << 17) 719 719 /* Loongson-3 FTLB on/off bit, VTLBOnly in manual */ 720 - #define MIPS_CONF6_LOONGSON_FTLBDIS (_ULCAST_(1) << 22) 720 + #define LOONGSON_CONF6_FTLBDIS (_ULCAST_(1) << 22) 721 721 722 722 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 723 723

+6 -6

arch/mips/kernel/cpu-probe.c

··· 635 635 config = read_c0_config6(); 636 636 637 637 if (flags & FTLB_EN) 638 - config |= MIPS_CONF6_MTI_FTLBEN; 638 + config |= MTI_CONF6_FTLBEN; 639 639 else 640 - config &= ~MIPS_CONF6_MTI_FTLBEN; 640 + config &= ~MTI_CONF6_FTLBEN; 641 641 642 642 if (flags & FTLB_SET_PROB) { 643 - config &= ~(3 << MIPS_CONF6_MTI_FTLBP_SHIFT); 643 + config &= ~(3 << MTI_CONF6_FTLBP_SHIFT); 644 644 config |= calculate_ftlb_probability(c) 645 - << MIPS_CONF6_MTI_FTLBP_SHIFT; 645 + << MTI_CONF6_FTLBP_SHIFT; 646 646 } 647 647 648 648 write_c0_config6(config); ··· 662 662 config = read_c0_config6(); 663 663 if (flags & FTLB_EN) 664 664 /* Enable FTLB */ 665 - write_c0_config6(config & ~MIPS_CONF6_LOONGSON_FTLBDIS); 665 + write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS); 666 666 else 667 667 /* Disable FTLB */ 668 - write_c0_config6(config | MIPS_CONF6_LOONGSON_FTLBDIS); 668 + write_c0_config6(config | LOONGSON_CONF6_FTLBDIS); 669 669 break; 670 670 default: 671 671 return 1;

+2 -2

arch/mips/kvm/vz.c

··· 129 129 130 130 static inline unsigned int kvm_vz_config6_guest_wrmask(struct kvm_vcpu *vcpu) 131 131 { 132 - return MIPS_CONF6_LOONGSON_INTIMER | MIPS_CONF6_LOONGSON_EXTIMER; 132 + return LOONGSON_CONF6_INTIMER | LOONGSON_CONF6_EXTIMER; 133 133 } 134 134 135 135 /* ··· 189 189 static inline unsigned int kvm_vz_config6_user_wrmask(struct kvm_vcpu *vcpu) 190 190 { 191 191 return kvm_vz_config6_guest_wrmask(vcpu) | 192 - MIPS_CONF6_LOONGSON_SFBEN | MIPS_CONF6_LOONGSON_FTLBDIS; 192 + LOONGSON_CONF6_SFBEN | LOONGSON_CONF6_FTLBDIS; 193 193 } 194 194 195 195 static gpa_t kvm_vz_gva_to_gpa_cb(gva_t gva)

+3 -3

arch/mips/loongson64/cpucfg-emul.c

··· 57 57 { 58 58 u32 config6 = read_c0_config6(); 59 59 60 - if (config6 & MIPS_CONF6_LOONGSON_SFBEN) 60 + if (config6 & LOONGSON_CONF6_SFBEN) 61 61 c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SFBP; 62 - if (config6 & MIPS_CONF6_LOONGSON_LLEXC) 62 + if (config6 & LOONGSON_CONF6_LLEXC) 63 63 c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LLEXC; 64 - if (config6 & MIPS_CONF6_LOONGSON_SCRAND) 64 + if (config6 & LOONGSON_CONF6_SCRAND) 65 65 c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SCRAND; 66 66 } 67 67

+2 -2

arch/mips/mm/c-r4k.c

··· 1066 1066 if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) 1067 1067 present = 1; 1068 1068 if (rev == PRID_REV_ENCODE_332(2, 4, 0)) 1069 - write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND); 1069 + write_c0_config6(read_c0_config6() | MTI_CONF6_SYND); 1070 1070 break; 1071 1071 case PRID_IMP_1074K: 1072 1072 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { 1073 1073 present = 1; 1074 - write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND); 1074 + write_c0_config6(read_c0_config6() | MTI_CONF6_SYND); 1075 1075 } 1076 1076 break; 1077 1077 default: