Merge branch 'gpio/next' of git://git.secretlab.ca/git/linux-2.6

tjh.dev / kernel

fork atom

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

fork atom

Merge branch 'gpio/next' of git://git.secretlab.ca/git/linux-2.6

* 'gpio/next' of git://git.secretlab.ca/git/linux-2.6:
gpio/pch_gpio: Support new device ML7223
gpio: make gpio_{request,free}_array gpio array parameter const
GPIO: OMAP: move to drivers/gpio
GPIO: OMAP: move register offset defines into <plat/gpio.h>
gpio: Convert gpio_is_valid to return bool
gpio: Move the s5pc100 GPIO to drivers/gpio
gpio: Move the s5pv210 GPIO to drivers/gpio
gpio: Move the exynos4 GPIO to drivers/gpio
gpio: Move to Samsung common GPIO library to drivers/gpio
gpio/nomadik: add function to read GPIO pull down status
gpio/nomadik: show all pins in debug
gpio: move Nomadik GPIO driver to drivers/gpio
gpio: move U300 GPIO driver to drivers/gpio
langwell_gpio: add runtime pm support
gpio/pca953x: Add support for pca9574 and pca9575 devices
gpio/cs5535: Show explicit dependency between gpio_cs5535 and mfd_cs5535

Linus Torvalds 15 years ago 04830fcc 571503e1

+472 -195

27 changed files

expand all collapse all

arch

arm

mach-exynos4

Makefile

mach-nomadik

Kconfig

mach-s5pc100

Makefile

mach-s5pv210

Makefile

mach-u300

Makefile

mach-ux500

Kconfig

plat-nomadik

Kconfig

Makefile

include

plat

gpio.h

plat-omap

Makefile

include

plat

gpio.h

plat-samsung

Makefile

drivers

gpio

Kconfig

Makefile

gpio-exynos4.c

gpio-nomadik.c

gpio-omap.c

gpio-plat-samsung.c

gpio-s5pc100.c

gpio-s5pv210.c

gpio-u300.c

gpiolib.c

langwell_gpio.c

pca953x.c

pch_gpio.c

include

asm-generic

gpio.h

linux

gpio.h

+1 -1

arch/arm/mach-exynos4/Makefile

reviewed

··· 13 13 # Core support for EXYNOS4 system 14 14 15 15 obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o 16 16 - obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o gpiolib.o irq-eint.o dma.o 16 16 + obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o 17 17 obj-$(CONFIG_PM) += pm.o sleep.o 18 18 obj-$(CONFIG_CPU_FREQ) += cpufreq.o 19 19 obj-$(CONFIG_CPU_IDLE) += cpuidle.o

arch/arm/mach-exynos4/gpiolib.c drivers/gpio/gpio-exynos4.c

reviewed

-1

arch/arm/mach-nomadik/Kconfig

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··· 6 6 bool "ST 8815 Nomadik Hardware Kit (evaluation board)" 7 7 select NOMADIK_8815 8 8 select HAS_MTU 9 9 - select NOMADIK_GPIO 10 9 11 10 endmenu 12 11

+1 -1

arch/arm/mach-s5pc100/Makefile

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··· 11 11 12 12 # Core support for S5PC100 system 13 13 14 14 - obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o 14 14 + obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o 15 15 obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o 16 16 obj-$(CONFIG_CPU_S5PC100) += dma.o 17 17

arch/arm/mach-s5pc100/gpiolib.c drivers/gpio/gpio-s5pc100.c

reviewed

+1 -1

arch/arm/mach-s5pv210/Makefile

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··· 12 12 13 13 # Core support for S5PV210 system 14 14 15 15 - obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o gpiolib.o 15 15 + obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o 16 16 obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o 17 17 obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o 18 18 obj-$(CONFIG_CPU_FREQ) += cpufreq.o

arch/arm/mach-s5pv210/gpiolib.c drivers/gpio/gpio-s5pv210.c

reviewed

+1 -1

arch/arm/mach-u300/Makefile

reviewed

··· 2 2 # Makefile for the linux kernel, U300 machine. 3 3 # 4 4 5 5 - obj-y := core.o clock.o timer.o gpio.o padmux.o 5 5 + obj-y := core.o clock.o timer.o padmux.o 6 6 obj-m := 7 7 obj-n := 8 8 obj- :=

arch/arm/mach-u300/gpio.c drivers/gpio/gpio-u300.c

reviewed

-1

arch/arm/mach-ux500/Kconfig

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··· 5 5 default y 6 6 select ARM_GIC 7 7 select HAS_MTU 8 8 - select NOMADIK_GPIO 9 8 select ARM_ERRATA_753970 10 9 11 10 menu "Ux500 SoC"

-5

arch/arm/plat-nomadik/Kconfig

reviewed

··· 21 21 to multiple interrupt generating programmable 22 22 32-bit free running decrementing counters. 23 23 24 24 - config NOMADIK_GPIO 25 25 - bool 26 26 - help 27 27 - Support for the Nomadik GPIO controller. 28 28 - 29 24 endif

-1

arch/arm/plat-nomadik/Makefile

reviewed

··· 3 3 # Licensed under GPLv2 4 4 5 5 obj-$(CONFIG_HAS_MTU) += timer.o 6 6 - obj-$(CONFIG_NOMADIK_GPIO) += gpio.o

+57 -8

arch/arm/plat-nomadik/gpio.c drivers/gpio/gpio-nomadik.c

reviewed

··· 57 57 u32 fwimsc; 58 58 u32 slpm; 59 59 u32 enabled; 60 60 + u32 pull_up; 60 61 }; 61 62 62 63 static struct nmk_gpio_chip * ··· 104 103 u32 pdis; 105 104 106 105 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); 107 107 - if (pull == NMK_GPIO_PULL_NONE) 106 106 + if (pull == NMK_GPIO_PULL_NONE) { 108 107 pdis |= bit; 109 109 - else 108 108 + nmk_chip->pull_up &= ~bit; 109 109 + } else { 110 110 pdis &= ~bit; 111 111 + } 112 112 + 111 113 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); 112 114 113 113 - if (pull == NMK_GPIO_PULL_UP) 115 115 + if (pull == NMK_GPIO_PULL_UP) { 116 116 + nmk_chip->pull_up |= bit; 114 117 writel(bit, nmk_chip->addr + NMK_GPIO_DATS); 115 115 - else if (pull == NMK_GPIO_PULL_DOWN) 118 118 + } else if (pull == NMK_GPIO_PULL_DOWN) { 119 119 + nmk_chip->pull_up &= ~bit; 116 120 writel(bit, nmk_chip->addr + NMK_GPIO_DATC); 121 121 + } 117 122 } 118 123 119 124 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, ··· 818 811 bool pull; 819 812 u32 bit = 1 << i; 820 813 821 821 - if (!label) 822 822 - continue; 823 823 - 824 814 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit; 825 815 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); 826 816 mode = nmk_gpio_get_mode(gpio); 827 817 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", 828 828 - gpio, label, 818 818 + gpio, label ?: "(none)", 829 819 is_out ? "out" : "in ", 830 820 chip->get 831 821 ? (chip->get(chip, i) ? "hi" : "lo") 832 822 : "? ", 833 823 (mode < 0) ? "unknown" : modes[mode], 834 824 pull ? "pull" : "none"); 825 825 + 826 826 + if (label && !is_out) { 827 827 + int irq = gpio_to_irq(gpio); 828 828 + struct irq_desc *desc = irq_to_desc(irq); 829 829 + 830 830 + /* This races with request_irq(), set_irq_type(), 831 831 + * and set_irq_wake() ... but those are "rare". 832 832 + */ 833 833 + if (irq >= 0 && desc->action) { 834 834 + char *trigger; 835 835 + u32 bitmask = nmk_gpio_get_bitmask(gpio); 836 836 + 837 837 + if (nmk_chip->edge_rising & bitmask) 838 838 + trigger = "edge-rising"; 839 839 + else if (nmk_chip->edge_falling & bitmask) 840 840 + trigger = "edge-falling"; 841 841 + else 842 842 + trigger = "edge-undefined"; 843 843 + 844 844 + seq_printf(s, " irq-%d %s%s", 845 845 + irq, trigger, 846 846 + irqd_is_wakeup_set(&desc->irq_data) 847 847 + ? " wakeup" : ""); 848 848 + } 849 849 + } 850 850 + 835 851 seq_printf(s, "\n"); 836 852 } 837 853 } ··· 925 895 926 896 if (cpu_is_u8500v2()) 927 897 writel(chip->slpm, chip->addr + NMK_GPIO_SLPC); 898 898 + } 899 899 + } 900 900 + 901 901 + /* 902 902 + * Read the pull up/pull down status. 903 903 + * A bit set in 'pull_up' means that pull up 904 904 + * is selected if pull is enabled in PDIS register. 905 905 + * Note: only pull up/down set via this driver can 906 906 + * be detected due to HW limitations. 907 907 + */ 908 908 + void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) 909 909 + { 910 910 + if (gpio_bank < NUM_BANKS) { 911 911 + struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; 912 912 + 913 913 + if (!chip) 914 914 + return; 915 915 + 916 916 + *pull_up = chip->pull_up; 928 917 } 929 918 } 930 919

arch/arm/plat-nomadik/include/plat/gpio.h

reviewed

··· 78 78 extern void nmk_gpio_wakeups_suspend(void); 79 79 extern void nmk_gpio_wakeups_resume(void); 80 80 81 81 + extern void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up); 82 82 + 81 83 /* 82 84 * Platform data to register a block: only the initial gpio/irq number. 83 85 */

+1 -1

arch/arm/plat-omap/Makefile

reviewed

··· 3 3 # 4 4 5 5 # Common support 6 6 - obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \ 6 6 + obj-y := common.o sram.o clock.o devices.o dma.o mux.o \ 7 7 usb.o fb.o io.o counter_32k.o 8 8 obj-m := 9 9 obj-n :=

-105

arch/arm/plat-omap/gpio.c drivers/gpio/gpio-omap.c

reviewed

··· 1 1 /* 2 2 - * linux/arch/arm/plat-omap/gpio.c 3 3 - * 4 2 * Support functions for OMAP GPIO 5 3 * 6 4 * Copyright (C) 2003-2005 Nokia Corporation ··· 27 29 #include <mach/irqs.h> 28 30 #include <mach/gpio.h> 29 31 #include <asm/mach/irq.h> 30 30 - 31 31 - /* 32 32 - * OMAP1510 GPIO registers 33 33 - */ 34 34 - #define OMAP1510_GPIO_DATA_INPUT 0x00 35 35 - #define OMAP1510_GPIO_DATA_OUTPUT 0x04 36 36 - #define OMAP1510_GPIO_DIR_CONTROL 0x08 37 37 - #define OMAP1510_GPIO_INT_CONTROL 0x0c 38 38 - #define OMAP1510_GPIO_INT_MASK 0x10 39 39 - #define OMAP1510_GPIO_INT_STATUS 0x14 40 40 - #define OMAP1510_GPIO_PIN_CONTROL 0x18 41 41 - 42 42 - #define OMAP1510_IH_GPIO_BASE 64 43 43 - 44 44 - /* 45 45 - * OMAP1610 specific GPIO registers 46 46 - */ 47 47 - #define OMAP1610_GPIO_REVISION 0x0000 48 48 - #define OMAP1610_GPIO_SYSCONFIG 0x0010 49 49 - #define OMAP1610_GPIO_SYSSTATUS 0x0014 50 50 - #define OMAP1610_GPIO_IRQSTATUS1 0x0018 51 51 - #define OMAP1610_GPIO_IRQENABLE1 0x001c 52 52 - #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 53 53 - #define OMAP1610_GPIO_DATAIN 0x002c 54 54 - #define OMAP1610_GPIO_DATAOUT 0x0030 55 55 - #define OMAP1610_GPIO_DIRECTION 0x0034 56 56 - #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 57 57 - #define OMAP1610_GPIO_EDGE_CTRL2 0x003c 58 58 - #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c 59 59 - #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 60 60 - #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 61 61 - #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc 62 62 - #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 63 63 - #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 64 64 - 65 65 - /* 66 66 - * OMAP7XX specific GPIO registers 67 67 - */ 68 68 - #define OMAP7XX_GPIO_DATA_INPUT 0x00 69 69 - #define OMAP7XX_GPIO_DATA_OUTPUT 0x04 70 70 - #define OMAP7XX_GPIO_DIR_CONTROL 0x08 71 71 - #define OMAP7XX_GPIO_INT_CONTROL 0x0c 72 72 - #define OMAP7XX_GPIO_INT_MASK 0x10 73 73 - #define OMAP7XX_GPIO_INT_STATUS 0x14 74 74 - 75 75 - /* 76 76 - * omap2+ specific GPIO registers 77 77 - */ 78 78 - #define OMAP24XX_GPIO_REVISION 0x0000 79 79 - #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 80 80 - #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 81 81 - #define OMAP24XX_GPIO_IRQENABLE2 0x002c 82 82 - #define OMAP24XX_GPIO_IRQENABLE1 0x001c 83 83 - #define OMAP24XX_GPIO_WAKE_EN 0x0020 84 84 - #define OMAP24XX_GPIO_CTRL 0x0030 85 85 - #define OMAP24XX_GPIO_OE 0x0034 86 86 - #define OMAP24XX_GPIO_DATAIN 0x0038 87 87 - #define OMAP24XX_GPIO_DATAOUT 0x003c 88 88 - #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 89 89 - #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 90 90 - #define OMAP24XX_GPIO_RISINGDETECT 0x0048 91 91 - #define OMAP24XX_GPIO_FALLINGDETECT 0x004c 92 92 - #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 93 93 - #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 94 94 - #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 95 95 - #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 96 96 - #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 97 97 - #define OMAP24XX_GPIO_SETWKUENA 0x0084 98 98 - #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 99 99 - #define OMAP24XX_GPIO_SETDATAOUT 0x0094 100 100 - 101 101 - #define OMAP4_GPIO_REVISION 0x0000 102 102 - #define OMAP4_GPIO_EOI 0x0020 103 103 - #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 104 104 - #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 105 105 - #define OMAP4_GPIO_IRQSTATUS0 0x002c 106 106 - #define OMAP4_GPIO_IRQSTATUS1 0x0030 107 107 - #define OMAP4_GPIO_IRQSTATUSSET0 0x0034 108 108 - #define OMAP4_GPIO_IRQSTATUSSET1 0x0038 109 109 - #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c 110 110 - #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 111 111 - #define OMAP4_GPIO_IRQWAKEN0 0x0044 112 112 - #define OMAP4_GPIO_IRQWAKEN1 0x0048 113 113 - #define OMAP4_GPIO_IRQENABLE1 0x011c 114 114 - #define OMAP4_GPIO_WAKE_EN 0x0120 115 115 - #define OMAP4_GPIO_IRQSTATUS2 0x0128 116 116 - #define OMAP4_GPIO_IRQENABLE2 0x012c 117 117 - #define OMAP4_GPIO_CTRL 0x0130 118 118 - #define OMAP4_GPIO_OE 0x0134 119 119 - #define OMAP4_GPIO_DATAIN 0x0138 120 120 - #define OMAP4_GPIO_DATAOUT 0x013c 121 121 - #define OMAP4_GPIO_LEVELDETECT0 0x0140 122 122 - #define OMAP4_GPIO_LEVELDETECT1 0x0144 123 123 - #define OMAP4_GPIO_RISINGDETECT 0x0148 124 124 - #define OMAP4_GPIO_FALLINGDETECT 0x014c 125 125 - #define OMAP4_GPIO_DEBOUNCENABLE 0x0150 126 126 - #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154 127 127 - #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160 128 128 - #define OMAP4_GPIO_SETIRQENABLE1 0x0164 129 129 - #define OMAP4_GPIO_CLEARWKUENA 0x0180 130 130 - #define OMAP4_GPIO_SETWKUENA 0x0184 131 131 - #define OMAP4_GPIO_CLEARDATAOUT 0x0190 132 132 - #define OMAP4_GPIO_SETDATAOUT 0x0194 133 32 134 33 struct gpio_bank { 135 34 unsigned long pbase;

+103

arch/arm/plat-omap/include/plat/gpio.h

reviewed

··· 52 52 53 53 #define OMAP34XX_NR_GPIOS 6 54 54 55 55 + /* 56 56 + * OMAP1510 GPIO registers 57 57 + */ 58 58 + #define OMAP1510_GPIO_DATA_INPUT 0x00 59 59 + #define OMAP1510_GPIO_DATA_OUTPUT 0x04 60 60 + #define OMAP1510_GPIO_DIR_CONTROL 0x08 61 61 + #define OMAP1510_GPIO_INT_CONTROL 0x0c 62 62 + #define OMAP1510_GPIO_INT_MASK 0x10 63 63 + #define OMAP1510_GPIO_INT_STATUS 0x14 64 64 + #define OMAP1510_GPIO_PIN_CONTROL 0x18 65 65 + 66 66 + #define OMAP1510_IH_GPIO_BASE 64 67 67 + 68 68 + /* 69 69 + * OMAP1610 specific GPIO registers 70 70 + */ 71 71 + #define OMAP1610_GPIO_REVISION 0x0000 72 72 + #define OMAP1610_GPIO_SYSCONFIG 0x0010 73 73 + #define OMAP1610_GPIO_SYSSTATUS 0x0014 74 74 + #define OMAP1610_GPIO_IRQSTATUS1 0x0018 75 75 + #define OMAP1610_GPIO_IRQENABLE1 0x001c 76 76 + #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 77 77 + #define OMAP1610_GPIO_DATAIN 0x002c 78 78 + #define OMAP1610_GPIO_DATAOUT 0x0030 79 79 + #define OMAP1610_GPIO_DIRECTION 0x0034 80 80 + #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 81 81 + #define OMAP1610_GPIO_EDGE_CTRL2 0x003c 82 82 + #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c 83 83 + #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 84 84 + #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 85 85 + #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc 86 86 + #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 87 87 + #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 88 88 + 89 89 + /* 90 90 + * OMAP7XX specific GPIO registers 91 91 + */ 92 92 + #define OMAP7XX_GPIO_DATA_INPUT 0x00 93 93 + #define OMAP7XX_GPIO_DATA_OUTPUT 0x04 94 94 + #define OMAP7XX_GPIO_DIR_CONTROL 0x08 95 95 + #define OMAP7XX_GPIO_INT_CONTROL 0x0c 96 96 + #define OMAP7XX_GPIO_INT_MASK 0x10 97 97 + #define OMAP7XX_GPIO_INT_STATUS 0x14 98 98 + 99 99 + /* 100 100 + * omap2+ specific GPIO registers 101 101 + */ 102 102 + #define OMAP24XX_GPIO_REVISION 0x0000 103 103 + #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 104 104 + #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 105 105 + #define OMAP24XX_GPIO_IRQENABLE2 0x002c 106 106 + #define OMAP24XX_GPIO_IRQENABLE1 0x001c 107 107 + #define OMAP24XX_GPIO_WAKE_EN 0x0020 108 108 + #define OMAP24XX_GPIO_CTRL 0x0030 109 109 + #define OMAP24XX_GPIO_OE 0x0034 110 110 + #define OMAP24XX_GPIO_DATAIN 0x0038 111 111 + #define OMAP24XX_GPIO_DATAOUT 0x003c 112 112 + #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 113 113 + #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 114 114 + #define OMAP24XX_GPIO_RISINGDETECT 0x0048 115 115 + #define OMAP24XX_GPIO_FALLINGDETECT 0x004c 116 116 + #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 117 117 + #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 118 118 + #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 119 119 + #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 120 120 + #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 121 121 + #define OMAP24XX_GPIO_SETWKUENA 0x0084 122 122 + #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 123 123 + #define OMAP24XX_GPIO_SETDATAOUT 0x0094 124 124 + 125 125 + #define OMAP4_GPIO_REVISION 0x0000 126 126 + #define OMAP4_GPIO_EOI 0x0020 127 127 + #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 128 128 + #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 129 129 + #define OMAP4_GPIO_IRQSTATUS0 0x002c 130 130 + #define OMAP4_GPIO_IRQSTATUS1 0x0030 131 131 + #define OMAP4_GPIO_IRQSTATUSSET0 0x0034 132 132 + #define OMAP4_GPIO_IRQSTATUSSET1 0x0038 133 133 + #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c 134 134 + #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 135 135 + #define OMAP4_GPIO_IRQWAKEN0 0x0044 136 136 + #define OMAP4_GPIO_IRQWAKEN1 0x0048 137 137 + #define OMAP4_GPIO_IRQENABLE1 0x011c 138 138 + #define OMAP4_GPIO_WAKE_EN 0x0120 139 139 + #define OMAP4_GPIO_IRQSTATUS2 0x0128 140 140 + #define OMAP4_GPIO_IRQENABLE2 0x012c 141 141 + #define OMAP4_GPIO_CTRL 0x0130 142 142 + #define OMAP4_GPIO_OE 0x0134 143 143 + #define OMAP4_GPIO_DATAIN 0x0138 144 144 + #define OMAP4_GPIO_DATAOUT 0x013c 145 145 + #define OMAP4_GPIO_LEVELDETECT0 0x0140 146 146 + #define OMAP4_GPIO_LEVELDETECT1 0x0144 147 147 + #define OMAP4_GPIO_RISINGDETECT 0x0148 148 148 + #define OMAP4_GPIO_FALLINGDETECT 0x014c 149 149 + #define OMAP4_GPIO_DEBOUNCENABLE 0x0150 150 150 + #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154 151 151 + #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160 152 152 + #define OMAP4_GPIO_SETIRQENABLE1 0x0164 153 153 + #define OMAP4_GPIO_CLEARWKUENA 0x0180 154 154 + #define OMAP4_GPIO_SETWKUENA 0x0184 155 155 + #define OMAP4_GPIO_CLEARDATAOUT 0x0190 156 156 + #define OMAP4_GPIO_SETDATAOUT 0x0194 157 157 + 55 158 #define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) 56 159 #define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) 57 160

-1

arch/arm/plat-samsung/Makefile

reviewed

··· 19 19 obj-y += gpio-config.o 20 20 obj-y += dev-asocdma.o 21 21 22 22 - obj-$(CONFIG_SAMSUNG_GPIOLIB_4BIT) += gpiolib.o 23 22 obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o 24 23 25 24 obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o

arch/arm/plat-samsung/gpiolib.c drivers/gpio/gpio-plat-samsung.c

reviewed

+32 -2

drivers/gpio/Kconfig

reviewed

··· 86 86 help 87 87 Say yes here to support GPIO functionality of IT8761E super I/O chip. 88 88 89 89 + config GPIO_EXYNOS4 90 90 + bool "Samsung Exynos4 GPIO library support" 91 91 + default y if CPU_EXYNOS4210 92 92 + help 93 93 + Say yes here to support Samsung Exynos4 series SoCs GPIO library 94 94 + 95 95 + config GPIO_PLAT_SAMSUNG 96 96 + bool "Samsung SoCs GPIO library support" 97 97 + default y if SAMSUNG_GPIOLIB_4BIT 98 98 + help 99 99 + Say yes here to support Samsung SoCs GPIO library 100 100 + 101 101 + config GPIO_S5PC100 102 102 + bool "Samsung S5PC100 GPIO library support" 103 103 + default y if CPU_S5PC100 104 104 + help 105 105 + Say yes here to support Samsung S5PC100 SoCs GPIO library 106 106 + 107 107 + config GPIO_S5PV210 108 108 + bool "Samsung S5PV210/S5PC110 GPIO library support" 109 109 + default y if CPU_S5PV210 110 110 + help 111 111 + Say yes here to support Samsung S5PV210/S5PC110 SoCs GPIO library 112 112 + 89 113 config GPIO_PL061 90 114 bool "PrimeCell PL061 GPIO support" 91 115 depends on ARM_AMBA ··· 327 303 328 304 config GPIO_CS5535 329 305 tristate "AMD CS5535/CS5536 GPIO support" 330 330 - depends on PCI && X86 && !CS5535_GPIO 306 306 + depends on PCI && X86 && !CS5535_GPIO && MFD_CS5535 331 307 help 332 308 The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that 333 309 can be used for quite a number of things. The CS5535/6 is found on ··· 358 334 Say Y here to support Intel Langwell/Penwell GPIO. 359 335 360 336 config GPIO_PCH 361 361 - tristate "PCH GPIO of Intel Topcliff" 337 337 + tristate "Intel EG20T PCH / OKI SEMICONDUCTOR ML7223 IOH GPIO" 362 338 depends on PCI && X86 363 339 help 364 340 This driver is for PCH(Platform controller Hub) GPIO of Intel Topcliff 365 341 which is an IOH(Input/Output Hub) for x86 embedded processor. 366 342 This driver can access PCH GPIO device. 343 343 + 344 344 + This driver also can be used for OKI SEMICONDUCTOR IOH(Input/ 345 345 + Output Hub), ML7223. 346 346 + ML7223 IOH is for MP(Media Phone) use. 347 347 + ML7223 is companion chip for Intel Atom E6xx series. 348 348 + ML7223 is completely compatible for Intel EG20T PCH. 367 349 368 350 config GPIO_ML_IOH 369 351 tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support"

drivers/gpio/Makefile

reviewed

··· 8 8 obj-$(CONFIG_GPIO_ADP5588) += adp5588-gpio.o 9 9 obj-$(CONFIG_GPIO_BASIC_MMIO_CORE) += basic_mmio_gpio.o 10 10 obj-$(CONFIG_GPIO_BASIC_MMIO) += basic_mmio_gpio.o 11 11 + obj-$(CONFIG_GPIO_EXYNOS4) += gpio-exynos4.o 12 12 + obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o 13 13 + obj-$(CONFIG_GPIO_S5PC100) += gpio-s5pc100.o 14 14 + obj-$(CONFIG_GPIO_S5PV210) += gpio-s5pv210.o 11 15 obj-$(CONFIG_GPIO_LANGWELL) += langwell_gpio.o 12 16 obj-$(CONFIG_GPIO_MAX730X) += max730x.o 13 17 obj-$(CONFIG_GPIO_MAX7300) += max7300.o ··· 20 16 obj-$(CONFIG_GPIO_MC33880) += mc33880.o 21 17 obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o 22 18 obj-$(CONFIG_GPIO_74X164) += 74x164.o 19 19 + obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o 23 20 obj-$(CONFIG_GPIO_PCA953X) += pca953x.o 24 21 obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o 25 22 obj-$(CONFIG_GPIO_PCH) += pch_gpio.o ··· 39 34 obj-$(CONFIG_GPIO_WM8350) += wm8350-gpiolib.o 40 35 obj-$(CONFIG_GPIO_WM8994) += wm8994-gpio.o 41 36 obj-$(CONFIG_GPIO_SCH) += sch_gpio.o 37 37 + obj-$(CONFIG_MACH_U300) += gpio-u300.o 38 38 + obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o 42 39 obj-$(CONFIG_GPIO_RDC321X) += rdc321x-gpio.o 43 40 obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o 44 41 obj-$(CONFIG_GPIO_SX150X) += sx150x.o

+2 -2

drivers/gpio/gpiolib.c

reviewed

··· 1296 1296 * @array: array of the 'struct gpio' 1297 1297 * @num: how many GPIOs in the array 1298 1298 */ 1299 1299 - int gpio_request_array(struct gpio *array, size_t num) 1299 1299 + int gpio_request_array(const struct gpio *array, size_t num) 1300 1300 { 1301 1301 int i, err; 1302 1302 ··· 1319 1319 * @array: array of the 'struct gpio' 1320 1320 * @num: how many GPIOs in the array 1321 1321 */ 1322 1322 - void gpio_free_array(struct gpio *array, size_t num) 1322 1322 + void gpio_free_array(const struct gpio *array, size_t num) 1323 1323 { 1324 1324 while (num--) 1325 1325 gpio_free((array++)->gpio);

+65

drivers/gpio/langwell_gpio.c

reviewed

··· 33 33 #include <linux/io.h> 34 34 #include <linux/gpio.h> 35 35 #include <linux/slab.h> 36 36 + #include <linux/pm_runtime.h> 36 37 37 38 /* 38 39 * Langwell chip has 64 pins and thus there are 2 32bit registers to control ··· 64 63 void *reg_base; 65 64 spinlock_t lock; 66 65 unsigned irq_base; 66 66 + struct pci_dev *pdev; 67 67 }; 68 68 69 69 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset, ··· 106 104 u32 value; 107 105 unsigned long flags; 108 106 107 107 + if (lnw->pdev) 108 108 + pm_runtime_get(&lnw->pdev->dev); 109 109 + 109 110 spin_lock_irqsave(&lnw->lock, flags); 110 111 value = readl(gpdr); 111 112 value &= ~BIT(offset % 32); 112 113 writel(value, gpdr); 113 114 spin_unlock_irqrestore(&lnw->lock, flags); 115 115 + 116 116 + if (lnw->pdev) 117 117 + pm_runtime_put(&lnw->pdev->dev); 118 118 + 114 119 return 0; 115 120 } 116 121 ··· 129 120 unsigned long flags; 130 121 131 122 lnw_gpio_set(chip, offset, value); 123 123 + 124 124 + if (lnw->pdev) 125 125 + pm_runtime_get(&lnw->pdev->dev); 126 126 + 132 127 spin_lock_irqsave(&lnw->lock, flags); 133 128 value = readl(gpdr); 134 129 value |= BIT(offset % 32); 135 130 writel(value, gpdr); 136 131 spin_unlock_irqrestore(&lnw->lock, flags); 132 132 + 133 133 + if (lnw->pdev) 134 134 + pm_runtime_put(&lnw->pdev->dev); 135 135 + 137 136 return 0; 138 137 } 139 138 ··· 162 145 163 146 if (gpio >= lnw->chip.ngpio) 164 147 return -EINVAL; 148 148 + 149 149 + if (lnw->pdev) 150 150 + pm_runtime_get(&lnw->pdev->dev); 151 151 + 165 152 spin_lock_irqsave(&lnw->lock, flags); 166 153 if (type & IRQ_TYPE_EDGE_RISING) 167 154 value = readl(grer) | BIT(gpio % 32); ··· 179 158 value = readl(gfer) & (~BIT(gpio % 32)); 180 159 writel(value, gfer); 181 160 spin_unlock_irqrestore(&lnw->lock, flags); 161 161 + 162 162 + if (lnw->pdev) 163 163 + pm_runtime_put(&lnw->pdev->dev); 182 164 183 165 return 0; 184 166 } ··· 234 210 235 211 chip->irq_eoi(data); 236 212 } 213 213 + 214 214 + #ifdef CONFIG_PM 215 215 + static int lnw_gpio_runtime_resume(struct device *dev) 216 216 + { 217 217 + return 0; 218 218 + } 219 219 + 220 220 + static int lnw_gpio_runtime_suspend(struct device *dev) 221 221 + { 222 222 + return 0; 223 223 + } 224 224 + 225 225 + static int lnw_gpio_runtime_idle(struct device *dev) 226 226 + { 227 227 + int err = pm_schedule_suspend(dev, 500); 228 228 + 229 229 + if (!err) 230 230 + return 0; 231 231 + 232 232 + return -EBUSY; 233 233 + } 234 234 + 235 235 + #else 236 236 + #define lnw_gpio_runtime_suspend NULL 237 237 + #define lnw_gpio_runtime_resume NULL 238 238 + #define lnw_gpio_runtime_idle NULL 239 239 + #endif 240 240 + 241 241 + static const struct dev_pm_ops lnw_gpio_pm_ops = { 242 242 + .runtime_suspend = lnw_gpio_runtime_suspend, 243 243 + .runtime_resume = lnw_gpio_runtime_resume, 244 244 + .runtime_idle = lnw_gpio_runtime_idle, 245 245 + }; 237 246 238 247 static int __devinit lnw_gpio_probe(struct pci_dev *pdev, 239 248 const struct pci_device_id *id) ··· 327 270 lnw->chip.base = gpio_base; 328 271 lnw->chip.ngpio = id->driver_data; 329 272 lnw->chip.can_sleep = 0; 273 273 + lnw->pdev = pdev; 330 274 pci_set_drvdata(pdev, lnw); 331 275 retval = gpiochip_add(&lnw->chip); 332 276 if (retval) { ··· 343 285 } 344 286 345 287 spin_lock_init(&lnw->lock); 288 288 + 289 289 + pm_runtime_put_noidle(&pdev->dev); 290 290 + pm_runtime_allow(&pdev->dev); 291 291 + 346 292 goto done; 347 293 err5: 348 294 kfree(lnw); ··· 364 302 .name = "langwell_gpio", 365 303 .id_table = lnw_gpio_ids, 366 304 .probe = lnw_gpio_probe, 305 305 + .driver = { 306 306 + .pm = &lnw_gpio_pm_ops, 307 307 + }, 367 308 }; 368 309 369 310

+188 -55

drivers/gpio/pca953x.c

reviewed

··· 24 24 #include <linux/of_gpio.h> 25 25 #endif 26 26 27 27 - #define PCA953X_INPUT 0 28 28 - #define PCA953X_OUTPUT 1 29 29 - #define PCA953X_INVERT 2 30 30 - #define PCA953X_DIRECTION 3 27 27 + #define PCA953X_INPUT 0 28 28 + #define PCA953X_OUTPUT 1 29 29 + #define PCA953X_INVERT 2 30 30 + #define PCA953X_DIRECTION 3 31 31 32 32 - #define PCA953X_GPIOS 0x00FF 33 33 - #define PCA953X_INT 0x0100 32 32 + #define PCA957X_IN 0 33 33 + #define PCA957X_INVRT 1 34 34 + #define PCA957X_BKEN 2 35 35 + #define PCA957X_PUPD 3 36 36 + #define PCA957X_CFG 4 37 37 + #define PCA957X_OUT 5 38 38 + #define PCA957X_MSK 6 39 39 + #define PCA957X_INTS 7 40 40 + 41 41 + #define PCA_GPIO_MASK 0x00FF 42 42 + #define PCA_INT 0x0100 43 43 + #define PCA953X_TYPE 0x1000 44 44 + #define PCA957X_TYPE 0x2000 34 45 35 46 static const struct i2c_device_id pca953x_id[] = { 36 36 - { "pca9534", 8 | PCA953X_INT, }, 37 37 - { "pca9535", 16 | PCA953X_INT, }, 38 38 - { "pca9536", 4, }, 39 39 - { "pca9537", 4 | PCA953X_INT, }, 40 40 - { "pca9538", 8 | PCA953X_INT, }, 41 41 - { "pca9539", 16 | PCA953X_INT, }, 42 42 - { "pca9554", 8 | PCA953X_INT, }, 43 43 - { "pca9555", 16 | PCA953X_INT, }, 44 44 - { "pca9556", 8, }, 45 45 - { "pca9557", 8, }, 47 47 + { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, 48 48 + { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, 49 49 + { "pca9536", 4 | PCA953X_TYPE, }, 50 50 + { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, 51 51 + { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, 52 52 + { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, 53 53 + { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, 54 54 + { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, 55 55 + { "pca9556", 8 | PCA953X_TYPE, }, 56 56 + { "pca9557", 8 | PCA953X_TYPE, }, 57 57 + { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, 58 58 + { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, 46 59 47 47 - { "max7310", 8, }, 48 48 - { "max7312", 16 | PCA953X_INT, }, 49 49 - { "max7313", 16 | PCA953X_INT, }, 50 50 - { "max7315", 8 | PCA953X_INT, }, 51 51 - { "pca6107", 8 | PCA953X_INT, }, 52 52 - { "tca6408", 8 | PCA953X_INT, }, 53 53 - { "tca6416", 16 | PCA953X_INT, }, 60 60 + { "max7310", 8 | PCA953X_TYPE, }, 61 61 + { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, 62 62 + { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, 63 63 + { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, 64 64 + { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, 65 65 + { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 66 66 + { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 54 67 /* NYET: { "tca6424", 24, }, */ 55 68 { } 56 69 }; ··· 88 75 struct pca953x_platform_data *dyn_pdata; 89 76 struct gpio_chip gpio_chip; 90 77 const char *const *names; 78 78 + int chip_type; 91 79 }; 92 80 93 81 static int pca953x_write_reg(struct pca953x_chip *chip, int reg, uint16_t val) 94 82 { 95 95 - int ret; 83 83 + int ret = 0; 96 84 97 85 if (chip->gpio_chip.ngpio <= 8) 98 86 ret = i2c_smbus_write_byte_data(chip->client, reg, val); 99 99 - else 100 100 - ret = i2c_smbus_write_word_data(chip->client, reg << 1, val); 87 87 + else { 88 88 + switch (chip->chip_type) { 89 89 + case PCA953X_TYPE: 90 90 + ret = i2c_smbus_write_word_data(chip->client, 91 91 + reg << 1, val); 92 92 + break; 93 93 + case PCA957X_TYPE: 94 94 + ret = i2c_smbus_write_byte_data(chip->client, reg << 1, 95 95 + val & 0xff); 96 96 + if (ret < 0) 97 97 + break; 98 98 + ret = i2c_smbus_write_byte_data(chip->client, 99 99 + (reg << 1) + 1, 100 100 + (val & 0xff00) >> 8); 101 101 + break; 102 102 + } 103 103 + } 101 104 102 105 if (ret < 0) { 103 106 dev_err(&chip->client->dev, "failed writing register\n"); ··· 145 116 { 146 117 struct pca953x_chip *chip; 147 118 uint16_t reg_val; 148 148 - int ret; 119 119 + int ret, offset = 0; 149 120 150 121 chip = container_of(gc, struct pca953x_chip, gpio_chip); 151 122 152 123 mutex_lock(&chip->i2c_lock); 153 124 reg_val = chip->reg_direction | (1u << off); 154 154 - ret = pca953x_write_reg(chip, PCA953X_DIRECTION, reg_val); 125 125 + 126 126 + switch (chip->chip_type) { 127 127 + case PCA953X_TYPE: 128 128 + offset = PCA953X_DIRECTION; 129 129 + break; 130 130 + case PCA957X_TYPE: 131 131 + offset = PCA957X_CFG; 132 132 + break; 133 133 + } 134 134 + ret = pca953x_write_reg(chip, offset, reg_val); 155 135 if (ret) 156 136 goto exit; 157 137 ··· 176 138 { 177 139 struct pca953x_chip *chip; 178 140 uint16_t reg_val; 179 179 - int ret; 141 141 + int ret, offset = 0; 180 142 181 143 chip = container_of(gc, struct pca953x_chip, gpio_chip); 182 144 ··· 187 149 else 188 150 reg_val = chip->reg_output & ~(1u << off); 189 151 190 190 - ret = pca953x_write_reg(chip, PCA953X_OUTPUT, reg_val); 152 152 + switch (chip->chip_type) { 153 153 + case PCA953X_TYPE: 154 154 + offset = PCA953X_OUTPUT; 155 155 + break; 156 156 + case PCA957X_TYPE: 157 157 + offset = PCA957X_OUT; 158 158 + break; 159 159 + } 160 160 + ret = pca953x_write_reg(chip, offset, reg_val); 191 161 if (ret) 192 162 goto exit; 193 163 ··· 203 157 204 158 /* then direction */ 205 159 reg_val = chip->reg_direction & ~(1u << off); 206 206 - ret = pca953x_write_reg(chip, PCA953X_DIRECTION, reg_val); 160 160 + switch (chip->chip_type) { 161 161 + case PCA953X_TYPE: 162 162 + offset = PCA953X_DIRECTION; 163 163 + break; 164 164 + case PCA957X_TYPE: 165 165 + offset = PCA957X_CFG; 166 166 + break; 167 167 + } 168 168 + ret = pca953x_write_reg(chip, offset, reg_val); 207 169 if (ret) 208 170 goto exit; 209 171 ··· 226 172 { 227 173 struct pca953x_chip *chip; 228 174 uint16_t reg_val; 229 229 - int ret; 175 175 + int ret, offset = 0; 230 176 231 177 chip = container_of(gc, struct pca953x_chip, gpio_chip); 232 178 233 179 mutex_lock(&chip->i2c_lock); 234 234 - ret = pca953x_read_reg(chip, PCA953X_INPUT, &reg_val); 180 180 + switch (chip->chip_type) { 181 181 + case PCA953X_TYPE: 182 182 + offset = PCA953X_INPUT; 183 183 + break; 184 184 + case PCA957X_TYPE: 185 185 + offset = PCA957X_IN; 186 186 + break; 187 187 + } 188 188 + ret = pca953x_read_reg(chip, offset, &reg_val); 235 189 mutex_unlock(&chip->i2c_lock); 236 190 if (ret < 0) { 237 191 /* NOTE: diagnostic already emitted; that's all we should ··· 256 194 { 257 195 struct pca953x_chip *chip; 258 196 uint16_t reg_val; 259 259 - int ret; 197 197 + int ret, offset = 0; 260 198 261 199 chip = container_of(gc, struct pca953x_chip, gpio_chip); 262 200 ··· 266 204 else 267 205 reg_val = chip->reg_output & ~(1u << off); 268 206 269 269 - ret = pca953x_write_reg(chip, PCA953X_OUTPUT, reg_val); 207 207 + switch (chip->chip_type) { 208 208 + case PCA953X_TYPE: 209 209 + offset = PCA953X_OUTPUT; 210 210 + break; 211 211 + case PCA957X_TYPE: 212 212 + offset = PCA957X_OUT; 213 213 + break; 214 214 + } 215 215 + ret = pca953x_write_reg(chip, offset, reg_val); 270 216 if (ret) 271 217 goto exit; 272 218 ··· 392 322 uint16_t old_stat; 393 323 uint16_t pending; 394 324 uint16_t trigger; 395 395 - int ret; 325 325 + int ret, offset = 0; 396 326 397 397 - ret = pca953x_read_reg(chip, PCA953X_INPUT, &cur_stat); 327 327 + switch (chip->chip_type) { 328 328 + case PCA953X_TYPE: 329 329 + offset = PCA953X_INPUT; 330 330 + break; 331 331 + case PCA957X_TYPE: 332 332 + offset = PCA957X_IN; 333 333 + break; 334 334 + } 335 335 + ret = pca953x_read_reg(chip, offset, &cur_stat); 398 336 if (ret) 399 337 return 0; 400 338 ··· 450 372 { 451 373 struct i2c_client *client = chip->client; 452 374 struct pca953x_platform_data *pdata = client->dev.platform_data; 453 453 - int ret; 375 375 + int ret, offset = 0; 454 376 455 377 if (pdata->irq_base != -1 456 456 - && (id->driver_data & PCA953X_INT)) { 378 378 + && (id->driver_data & PCA_INT)) { 457 379 int lvl; 458 380 459 459 - ret = pca953x_read_reg(chip, PCA953X_INPUT, 460 460 - &chip->irq_stat); 381 381 + switch (chip->chip_type) { 382 382 + case PCA953X_TYPE: 383 383 + offset = PCA953X_INPUT; 384 384 + break; 385 385 + case PCA957X_TYPE: 386 386 + offset = PCA957X_IN; 387 387 + break; 388 388 + } 389 389 + ret = pca953x_read_reg(chip, offset, &chip->irq_stat); 461 390 if (ret) 462 391 goto out_failed; 463 392 ··· 524 439 struct i2c_client *client = chip->client; 525 440 struct pca953x_platform_data *pdata = client->dev.platform_data; 526 441 527 527 - if (pdata->irq_base != -1 && (id->driver_data & PCA953X_INT)) 442 442 + if (pdata->irq_base != -1 && (id->driver_data & PCA_INT)) 528 443 dev_warn(&client->dev, "interrupt support not compiled in\n"); 529 444 530 445 return 0; ··· 584 499 } 585 500 #endif 586 501 502 502 + static int __devinit device_pca953x_init(struct pca953x_chip *chip, int invert) 503 503 + { 504 504 + int ret; 505 505 + 506 506 + ret = pca953x_read_reg(chip, PCA953X_OUTPUT, &chip->reg_output); 507 507 + if (ret) 508 508 + goto out; 509 509 + 510 510 + ret = pca953x_read_reg(chip, PCA953X_DIRECTION, 511 511 + &chip->reg_direction); 512 512 + if (ret) 513 513 + goto out; 514 514 + 515 515 + /* set platform specific polarity inversion */ 516 516 + ret = pca953x_write_reg(chip, PCA953X_INVERT, invert); 517 517 + if (ret) 518 518 + goto out; 519 519 + return 0; 520 520 + out: 521 521 + return ret; 522 522 + } 523 523 + 524 524 + static int __devinit device_pca957x_init(struct pca953x_chip *chip, int invert) 525 525 + { 526 526 + int ret; 527 527 + uint16_t val = 0; 528 528 + 529 529 + /* Let every port in proper state, that could save power */ 530 530 + pca953x_write_reg(chip, PCA957X_PUPD, 0x0); 531 531 + pca953x_write_reg(chip, PCA957X_CFG, 0xffff); 532 532 + pca953x_write_reg(chip, PCA957X_OUT, 0x0); 533 533 + 534 534 + ret = pca953x_read_reg(chip, PCA957X_IN, &val); 535 535 + if (ret) 536 536 + goto out; 537 537 + ret = pca953x_read_reg(chip, PCA957X_OUT, &chip->reg_output); 538 538 + if (ret) 539 539 + goto out; 540 540 + ret = pca953x_read_reg(chip, PCA957X_CFG, &chip->reg_direction); 541 541 + if (ret) 542 542 + goto out; 543 543 + 544 544 + /* set platform specific polarity inversion */ 545 545 + pca953x_write_reg(chip, PCA957X_INVRT, invert); 546 546 + 547 547 + /* To enable register 6, 7 to controll pull up and pull down */ 548 548 + pca953x_write_reg(chip, PCA957X_BKEN, 0x202); 549 549 + 550 550 + return 0; 551 551 + out: 552 552 + return ret; 553 553 + } 554 554 + 587 555 static int __devinit pca953x_probe(struct i2c_client *client, 588 556 const struct i2c_device_id *id) 589 557 { 590 558 struct pca953x_platform_data *pdata; 591 559 struct pca953x_chip *chip; 592 592 - int ret; 560 560 + int ret = 0; 593 561 594 562 chip = kzalloc(sizeof(struct pca953x_chip), GFP_KERNEL); 595 563 if (chip == NULL) ··· 669 531 chip->gpio_start = pdata->gpio_base; 670 532 671 533 chip->names = pdata->names; 534 534 + chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE); 672 535 673 536 mutex_init(&chip->i2c_lock); 674 537 675 538 /* initialize cached registers from their original values. 676 539 * we can't share this chip with another i2c master. 677 540 */ 678 678 - pca953x_setup_gpio(chip, id->driver_data & PCA953X_GPIOS); 541 541 + pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK); 679 542 680 680 - ret = pca953x_read_reg(chip, PCA953X_OUTPUT, &chip->reg_output); 681 681 - if (ret) 682 682 - goto out_failed; 683 683 - 684 684 - ret = pca953x_read_reg(chip, PCA953X_DIRECTION, &chip->reg_direction); 685 685 - if (ret) 686 686 - goto out_failed; 687 687 - 688 688 - /* set platform specific polarity inversion */ 689 689 - ret = pca953x_write_reg(chip, PCA953X_INVERT, pdata->invert); 690 690 - if (ret) 543 543 + if (chip->chip_type == PCA953X_TYPE) 544 544 + device_pca953x_init(chip, pdata->invert); 545 545 + else if (chip->chip_type == PCA957X_TYPE) 546 546 + device_pca957x_init(chip, pdata->invert); 547 547 + else 691 548 goto out_failed; 692 549 693 550 ret = pca953x_irq_setup(chip, id);

drivers/gpio/pch_gpio.c

reviewed

··· 283 283 #define pch_gpio_resume NULL 284 284 #endif 285 285 286 286 + #define PCI_VENDOR_ID_ROHM 0x10DB 286 287 static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = { 287 288 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) }, 289 289 + { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) }, 288 290 { 0, } 289 291 }; 290 292 MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);

+5 -5

include/asm-generic/gpio.h

reviewed

··· 35 35 * platform data and other tables. 36 36 */ 37 37 38 38 - static inline int gpio_is_valid(int number) 38 38 + static inline bool gpio_is_valid(int number) 39 39 { 40 40 - return ((unsigned)number) < ARCH_NR_GPIOS; 40 40 + return number >= 0 && number < ARCH_NR_GPIOS; 41 41 } 42 42 43 43 struct device; ··· 193 193 }; 194 194 195 195 extern int gpio_request_one(unsigned gpio, unsigned long flags, const char *label); 196 196 - extern int gpio_request_array(struct gpio *array, size_t num); 197 197 - extern void gpio_free_array(struct gpio *array, size_t num); 196 196 + extern int gpio_request_array(const struct gpio *array, size_t num); 197 197 + extern void gpio_free_array(const struct gpio *array, size_t num); 198 198 199 199 #ifdef CONFIG_GPIO_SYSFS 200 200 ··· 212 212 213 213 #else /* !CONFIG_GPIOLIB */ 214 214 215 215 - static inline int gpio_is_valid(int number) 215 215 + static inline bool gpio_is_valid(int number) 216 216 { 217 217 /* only non-negative numbers are valid */ 218 218 return number >= 0;

+4 -4

include/linux/gpio.h

reviewed

··· 25 25 * warning when something is wrongly called. 26 26 */ 27 27 28 28 - static inline int gpio_is_valid(int number) 28 28 + static inline bool gpio_is_valid(int number) 29 29 { 30 30 - return 0; 30 30 + return false; 31 31 } 32 32 33 33 static inline int gpio_request(unsigned gpio, const char *label) ··· 41 41 return -ENOSYS; 42 42 } 43 43 44 44 - static inline int gpio_request_array(struct gpio *array, size_t num) 44 44 + static inline int gpio_request_array(const struct gpio *array, size_t num) 45 45 { 46 46 return -ENOSYS; 47 47 } ··· 54 54 WARN_ON(1); 55 55 } 56 56 57 57 - static inline void gpio_free_array(struct gpio *array, size_t num) 57 57 + static inline void gpio_free_array(const struct gpio *array, size_t num) 58 58 { 59 59 might_sleep(); 60 60